Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

Sorry for the previous question, now I have understood better the core implementation of SPI core, and my previous question was nonsense.. sorry..

I noticed that you have included in the MDK release of August the proper code to link FPGA SPI core to DSP.
Now I have another question about SPI componenet implementation on the top vhdl file:

1) I see you have defined a component called "spi" on the MityDSP_L138_pkg.vhd file ,and an entity called SPI_iface on the SPI_iface.vhd file.

What is the logical link between these blocks?

2)I have to put some spi's (let's say 4, for example) on the fpga, and I need in the meanwhile to have a fifo buffer on each SPI.
Could you please provide an example on how to put together the components on the top vhdl file, to achieve my results?
Or maybe some documentation about this task, or a short explaination about that?

I am newbie on fpga, but I really appreciate your work on it!

Thank you very much in advance,

Michele Canepa

1. The SPI_Iface is designed to support using our IP on an FPGA that is remoted from the module and connected only though a SPI bus instead of the EMIFA bus. It effectively replaces the EMIFA_Iface.vhd. You shouldn't need to use the SPI_Iface module with our standard products.

2. The following snippet of vhdl shows hooking up a SPI unit with a pair of Xilinx core generated FIFOs (.xco file attached).

...

architecture rtl of your_entity is

...
component fifo_dpram64x32
    port (
    clk: IN std_logic;
    rst: IN std_logic;
    din: IN std_logic_VECTOR(31 downto 0);
    wr_en: IN std_logic;
    rd_en: IN std_logic;
    dout: OUT std_logic_VECTOR(31 downto 0);
    full: OUT std_logic;
    empty: OUT std_logic;
    data_count: OUT std_logic_VECTOR(5 downto 0));
end component; 

signal mosi_din : std_logic_VECTOR(31 downto 0);
signal mosi_wr_en : std_logic;
signal mosi_rd_en : std_logic;
signal mosi_dout  : std_logic_VECTOR(31 downto 0);
signal mosi_full : std_logic;
signal mosi_empty : std_logic;
signal mosi_wr_data_count : std_logic_VECTOR(11 downto 0) := (others=>'0');
signal spi_fifo_rst : std_logic := '0';

signal miso_wr_clk : std_logic;
signal miso_rd_clk : std_logic;
signal miso_din : std_logic_VECTOR(31 downto 0);
signal miso_wr_en : std_logic;
signal miso_rd_en : std_logic;
signal miso_dout  : std_logic_VECTOR(31 downto 0);
signal miso_empty : std_logic;
signal miso_rd_data_count : std_logic_VECTOR(11 downto 0) := (others=>'0');
signal spi_cs : std_logic_vector(7 downto 0) := (others=>'1');
signal spi_clk, spi_mosi : std_logic := '0';

begin

...

spi_core : spi
   Port Map (  
      emif_clk       => ema_clk, 
      i_ABus         => addr_r,
      i_DBus         => edi_r,
      o_DBus         => edo(CORE_SPI),
      i_wr_en        => wr_r,
      i_rd_en        => rd_r,
      i_cs           => cs5_r(CORE_SPI),
      o_irq          => irq_map(CORE_SPI_IRQ_LEVEL)(CORE_SPI_IRQ_VECTOR),
      i_ilevel       => CONV_STD_LOGIC_VECTOR(CORE_SPI_IRQ_LEVEL,2),
      i_ivector      => CONV_STD_LOGIC_VECTOR(CORE_SPI_IRQ_VECTOR,4),

      -- SPI interface signals        
      o_sclk         => spi_clk,
      o_cs_n         => spi_cs,
      o_mosi         => spi_mosi,
      i_miso         => i_sdo,

      -- In/Out FIFO interfaces (NO FIRST WORD FALL THROUGH)
      --    Synchronous on emif_clock
      i_fifo_depth          => "010",
      o_mosi_fifo_wr        => mosi_wr_en,
      o_mosi_fifo_rd        => mosi_rd_en,
      o_mosi_fifo_in        => mosi_din,  -- fifo data input
      i_mosi_fifo_out       => mosi_dout,
      i_mosi_write_cnt      => mosi_wr_data_count,
      i_mosi_empty             => mosi_empty,

      o_miso_fifo_wr        => miso_wr_en,
      o_miso_fifo_rd        => miso_rd_en,
      o_miso_fifo_in        => miso_din,
      i_miso_fifo_out       => miso_dout,
      i_miso_read_cnt       => miso_rd_data_count,
      i_miso_empty          => miso_empty,

      o_fifo_rst            => spi_fifo_rst

    );

o_cs_n      <= spi_cs(0);
o_sdi       <= spi_mosi;

mosi_fifo : fifo_dpram64x32
        port map (
            clk => ema_clk,
            rst => spi_fifo_rst,
            din => mosi_din,
            wr_en => mosi_wr_en,
            rd_en => mosi_rd_en,
            dout => mosi_dout,
            full => open,
            empty => mosi_empty,
            data_count => mosi_wr_data_count(5 downto 0));    

miso_fifo : fifo_dpram64x32
        port map (
            clk => ema_clk,
            rst => spi_fifo_rst,
            din => miso_din,
            wr_en => miso_wr_en,
            rd_en => miso_rd_en,
            dout => miso_dout,
            full => open,
            empty => miso_empty,
            data_count => miso_rd_data_count(5 downto 0));    

...

end rtl;

Thank you very much Micheal!!
I will try to implement this in these next days and I will give you feedback about it.

Best Regards,

Michele

Dear all,
I'm trying to understand the behaviour of your SPI core on FPGA with hooked FIFO and wondering how to connect it to a PulSAR ADC (for example AD7980) from Analog Devices, hopefully, on SW side, using your tcDspFpgaSpi Class in core library.

Because I'm choosing the suitable hardware configuration of the ADC on digital side (i.e. the SPI Mode: 3 wire, 4 wire, with or without Busy Signal) I need some information about the exact behaviour of your SPI controller.

The questions are, looking into fpga_spi.h header into /common/ directory:

1- I see sclk_ctrl bit in CSR register, comments "1 = controlled clock" but I did not understand what event controls the clock.

2- Now I'm wondering: the "go" bit in CSR triggers the transfer, so that a 1 on it start triggering (4*dwidth) clock pulses if sclck_ctrl is 1. Am I right?

3- What does exactly delay into SPIDEL register means?

4- The thing I need to do is to trigger an SPI transfer reading the ADC (connected as a slave on the SPI bus) after a suitable conversion time after an interrupt(that is the conversion signal). This conversion signal is routed to the FPGA, to the DSP and to the ARM. What do you suggest to do in my case?
Should I attach the signal to an ISR and then call the Transfer() method inside it, or maybe there's a faster (and more hardware) method to do it that I can't see? The best would be that the SPI controller could automatically fill it's FIFO buffers, clocking out the bits after this external trigger, but I don't know if this is possible.

Thank you in advance,
Best Regards.

Michele Canepa