Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

01/29/2014

06:48 PM FPGA Development: RE: Ethernet Rev B

Hi,
I just received your rev B module. We noticed that the ethernet doesn't work on this revision at all. Is there... Anonymous

01/27/2014

12:56 PM FPGA Development: RE: Load FPGA Timeout Error

Hi Jack,
I'm not sure what else to try other than trying to program the FPGA through a JTAG pod, which I believe y... Daniel Vincelette

01/24/2014

01:57 PM FPGA Development: RE: Load FPGA Timeout Error

Hi Dan,
I did what Adam suggested and it made no difference. I tried it without anything plugged in and still noth... Anonymous

01:21 PM FPGA Development: RE: Load FPGA Timeout Error

Currently I do not believe that is the case, seeing as this problem is happening in both uboot and linux.
Have you... Daniel Vincelette

12:28 PM FPGA Development: RE: Load FPGA Timeout Error

Could this be a OS issue that's causing it?
Can some one direct me the exact link where I can download the img fil... Anonymous

01/22/2014

03:37 PM FPGA Development: RE: Load FPGA Timeout Error

Your MSEL is currently 00000. Try changing S100-position3 to OFF to get an MSEL[4:0] of 00100. This will change the ... Adam Dziedzic

03:11 PM FPGA Development: RE: Load FPGA Timeout Error

Looking through the uboot source code it seems that the HPS is not able to set the FPGA into a reset mode. Which coul... Daniel Vincelette

02:57 PM FPGA Development: RE: Load FPGA Timeout Error

correct Anonymous

02:56 PM FPGA Development: RE: Load FPGA Timeout Error

Is the following the full error you received?... Daniel Vincelette

02:34 PM FPGA Development: RE: Load FPGA Timeout Error

Yes Anonymous

02:33 PM FPGA Development: RE: Load FPGA Timeout Error

was this from the **run fpgaload**? Daniel Vincelette

02:31 PM FPGA Development: RE: Load FPGA Timeout Error

Hi Dan,
I got an error: Failed with error code -1.
Jack Anonymous

02:29 PM FPGA Development: RE: Load FPGA Timeout Error

Hi Jack,
This needs to be run during uboot, which you get to by pressing any key during the first 5 seconds of sta... Daniel Vincelette

02:13 PM FPGA Development: RE: Load FPGA Timeout Error

Hi Dan,
The Linux OS on the board doesn't have run and saveenv. I tried to update it, but it doesn't have the apt-... Anonymous

01:33 PM FPGA Development: RE: Load FPGA Timeout Error

... Daniel Vincelette

12:59 PM FPGA Development: RE: Load FPGA Timeout Error

Hi Dan,
Regarding the uboot procedure, I have never worked with uboot before and the instructions on rocketboard i... Anonymous

12:33 PM FPGA Development: RE: Load FPGA Timeout Error

Hi Adam,
I'm not sure what the default positions for the MSEL or which of the switches on board are for the MSEL. ... Anonymous

12:23 PM FPGA Development: RE: Load FPGA Timeout Error

Hi Jack,
Please check the MSEL dip switches. These should be set to FPPx16 or FPPx32 for the FPGA Manager to be a... Adam Dziedzic

12:07 PM FPGA Development: RE: Load FPGA Timeout Error

Hi Dan,
The same issue still occurs after power cycling.
I'm wondering if it's a hardware issue.
Jack Anonymous

10:43 AM FPGA Development: RE: Load FPGA Timeout Error

Hi Jack,
We have not seen this issue yet. If you power cycle the board did this issue still occur?
Dan Daniel Vincelette

01/20/2014

05:19 PM FPGA Development: Load FPGA Timeout Error

Hi,
I just got back from vacation and tried to run my board and ran into a problem.
I tried to load rbf file as... Anonymous

01/09/2014

08:50 AM FPGA Development: RE: I/O voltage

Thanks, very useful info. Will give it a try over the next couple of weeks.
Nigel. Nigel Doe

01/08/2014

04:57 PM FPGA Development: RE: I/O voltage

Hi Nigel,
Below you will find the details to support additional IO standards. I believe this covers all the neces... Adam Dziedzic

01:53 PM FPGA Development: RE: I/O voltage

Any update on whether the dev kit can be configured for 3.3v I/O?
Thanks,
Nigel. Nigel Doe