Critical Link Support: Alexander Blockhttp://support.criticallink.com/redmine/http://support.criticallink.com/redmine/redmine/favicon.ico?16338348402023-11-16T18:18:06ZCritical Link Support
Redmine MitySOM-5CSX Embedded Vision Developer's Kit for Basler dart BCON - Support: RE: Barrel jack typehttp://support.criticallink.com/redmine/boards/52/topics/6546?r=6548#message-65482023-11-16T18:18:06ZAlexander Blockalex.block@criticallink.com
<p>Marko,</p>
<p>The manufacturer part number used for the barrel jack is PJ-059BH. I have attached the manufacturer datasheet for your reference which has the dimensions you should need.</p>
<p>Alex</p> MitySOM-5CSX Altera Cyclone V - PCB Development: RE: Ethernet PHYhttp://support.criticallink.com/redmine/boards/46/topics/6090?r=6121#message-61212021-09-23T15:52:21ZAlexander Blockalex.block@criticallink.com
<p>Lucas,</p>
<p>Thanks for the followup.</p>
<p>It actually looks like at Gigabit speeds the <strong>KSZ9031</strong> only specifies ~221mA for the 1.2V supply while the <strong>KSZ9021</strong> is 563mA.</p>
<p>When operating in 100Mbit mode the KSZ9021 only draws 158mA which would explain why you didn't have an issue.</p>
<p>Alex</p> MitySOM-5CSX Altera Cyclone V - PCB Development: RE: Note on MM70-314-310B2-1-R500http://support.criticallink.com/redmine/boards/46/topics/6111?r=6116#message-61162021-09-09T23:17:06ZAlexander Blockalex.block@criticallink.com
<p>Eike's post was followed up in this forum post (<a class="external" href="https://support.criticallink.com/redmine/boards/46/topics/6114">https://support.criticallink.com/redmine/boards/46/topics/6114</a>).</p> MitySOM-5CSX Altera Cyclone V - PCB Development: RE: Alternative for MM70-314-310B1-1-R300http://support.criticallink.com/redmine/boards/46/topics/6114?r=6115#message-61152021-09-09T23:01:07ZAlexander Blockalex.block@criticallink.com
<p>We actually have a detailed Wiki page (<a class="external" href="https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/MXM_Connector_Information">https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/MXM_Connector_Information</a>) that covers a number of the alternate connectors that are compatible with the MitySOM-5CSx module families.</p>
The new recommended component from JAE is the MM70-314-B1-2-R300.
<ul>
<li>Same height as the original </li>
<li>Has 314 contacts loaded instead of the 310 for the original</li>
<li>The footprint for the 314 pin version would be slightly different as there are the 4 extra pins
<ul>
<li>These extra pins are not needed on the SOM and can be left as no connects and/or tied accordingly as shown in the Wiki page</li>
</ul></li>
</ul>
<p>Please let us know if you have any further questions,</p>
<p>Alex</p> MitySOM-5CSX Altera Cyclone V - PCB Development: RE: USB Hubhttp://support.criticallink.com/redmine/boards/46/topics/6087?r=6088#message-60882021-06-24T01:27:25ZAlexander Blockalex.block@criticallink.com
<p>Lucas,</p>
<p>The USB Hub you have selected handles both the VBUS enable and Overcurrent detection for each of the ports, please follow the USB2046 recommendations for connecting these signals to the TPS2044D power distribution switches. As such you would not need to connect either the USB1_PS_ON or USB1_FAULT_N signals back to the module and those signals can be left floating at the module connector.</p>
<p>Note:</p>
<ol>
<li>You'll want to tie the USB1_ID (Pin 272) to GND to put the interface into HOST mode.</li>
<li>In prior designs where we implemented a USB hub, different component, we also had the VBUS (Pin 278) pulled up to 5V through a 332 ohm resistor.</li>
</ol>
<p>Let us know if you have any further questions,</p>
<p>Alex</p> MitySOM-5CSX Altera Cyclone V - FPGA Development: RE: Quartus v20.1 errors building mitysom 5csx ...http://support.criticallink.com/redmine/boards/47/topics/6036?r=6039#message-60392020-09-09T23:43:40ZAlexander Blockalex.block@criticallink.com
<p>Tristan,</p>
<p>I wanted to let you know that I installed Quartus Lite 20.1 and attempted to build the FPGA project per our Wiki instructions. I got to the same exact point and error as you. It appears, in my case, that if I manually run the Nios II Command Shell from a CMD prompt I am notified that 'wsl' is not recognized, see attached image.</p>
<p>If your issue is the same as mine then you need to be using an updated version of Windows 10 and install the WSL tools per this instruction from Intel (<a class="external" href="https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/tools/2019/how-do-i-install-the-windows--subsystem-for-linux---wsl--on-wind.html">https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/tools/2019/how-do-i-install-the-windows--subsystem-for-linux---wsl--on-wind.html</a>). At that point you can reboot and try the build again.</p>
<p>Unfortunately it appears that WSL is not supported in Windows 7.</p>
<p>Let me know if you still hit a road block further along the build process.</p>
<p>Alex</p> MitySOM-5CSX Altera Cyclone V - PCB Development: RE: I2C pull-up resistor on mitySOM 5CSE-H4-3YA...http://support.criticallink.com/redmine/boards/46/topics/6027?r=6030#message-60302020-07-28T23:28:41ZAlexander Blockalex.block@criticallink.com
<p>I2C0 is used on the module and cannot be used on a carrier board, it does have the necessary pull ups on it.</p>
<p>I2C2 or 3 do not have pull ups installed on the module. Note that I2C2 can only be accessed if routes through the FPGA fabric.</p>
<p>Alex</p> MitySOM-5CSX Altera Cyclone V - PCB Development: RE: I2C pull-up resistor on mitySOM 5CSE-H4-3YA...http://support.criticallink.com/redmine/boards/46/topics/6027?r=6028#message-60282020-07-28T22:17:25ZAlexander Blockalex.block@criticallink.com
<p>Pablo,</p>
<p>If you are asking about the "I2C1" signals at pins 28 and 30 of the module there are no pull-ups on the module. You would need to place 2.2k pull-ups to 3.3V on your carrier board for those signals if used as I2C.</p>
<p>If those are not the pins in question please comment specifically which module pins you are inquiring about.</p>
<p>Thanks,</p>
<p>Alex</p> MitySOM-5CSX Altera Cyclone V - FPGA Development: RE: MitySOM-5CSX-H6-42A files generation issueshttp://support.criticallink.com/redmine/boards/47/topics/5920?r=5921#message-59212020-02-12T20:27:06ZAlexander Blockalex.block@criticallink.com
<p>Dario,</p>
<p>It sounds like you may need to modify some of your environment variables to properly boot from the new Kernel/device tree images you have created.</p>
<p>Can you please provide a complete boot log including the output of your environment variables?</p>
<p>We'll review those and provide further followup.</p>
<p>Thanks,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: L138-FX-225-RC not available at D...http://support.criticallink.com/redmine/boards/10/topics/5865?r=5868#message-58682019-10-25T15:42:57ZAlexander Blockalex.block@criticallink.com
<p>Happy to hear you're all set and thanks for bringing the description issue to our attention.</p>
<p>I have forwarded your comments to our marketing team to look into it.</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: L138-FX-225-RC not available at D...http://support.criticallink.com/redmine/boards/10/topics/5865?r=5866#message-58662019-10-24T21:27:40ZAlexander Blockalex.block@criticallink.com
<p>The MityDSP-L138 family (both with and without the FPGA) is still in active production and is planned to be over the next 5 years plus.</p>
<p>The issue you are running into is actually due to this PCN20180209000 (<a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Module_Product_Change_Notifications">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Module_Product_Change_Notifications</a>) which discusses the fact that the 8MB NOR part went obsolete. Due to this we had to switch to a 16MB sized NOR which is why you are finding the "225" modules as unavailable from distribution but the "325" are, or will be, available. We are currently working on providing inventory to our distribution partners of the new "325" variants.</p>
<p>If you still need assistance in obtaining product feel free to contact us using our <a class="email" href="mailto:info@criticallink.com">info@criticallink.com</a> e-mail and someone from our sales team can provide further assistance. Please be sure to include information about how many units you need if you make such an inquiry.</p>
<p>Thanks,</p>
<p>Alex</p> MityCCD Scientific Cameras - Support: RE: Newport Instaspec X CCD camera http://support.criticallink.com/redmine/boards/20/topics/5854?r=5857#message-58572019-09-16T18:00:56ZAlexander Blockalex.block@criticallink.com
<p>Mirko,</p>
<p>Looking at the hardware, this is not one of our designs. Based on the datasheet, the sensor requires 5-6 different voltages. There should be a separate power supply unit from Newport that creates these voltages and passes them to the camera. Sorry I could not be more helpful.</p>
<p>Jaime</p> MityCCD Scientific Cameras - Support: RE: Newport Instaspec X CCD camera http://support.criticallink.com/redmine/boards/20/topics/5854?r=5855#message-58552019-09-16T15:51:29ZAlexander Blockalex.block@criticallink.com
<p>Dear Mirko,</p>
<p>Thank you for your inquiry. Unfortunately, we do not use the same serial identification numbers as Newport. Critical Link has designed a couple of different E2V camera packages. If you can provide pictures of the camera, I should be able to tell you the correct power supply for your camera.</p>
<p>Thank you,</p>
<p>Jaime Wilkie</p> MitySOM-5CSX Altera Cyclone V - Software Development: RE: LinuxPTP: 1PPS output is running at 0.1Hz http://support.criticallink.com/redmine/boards/45/topics/5755?r=5756#message-57562018-10-09T22:26:41ZAlexander Blockalex.block@criticallink.com
<p>Vidar,</p>
<p>If you look through your boot log do you see either of the following debug printouts?<br /><pre>
PTP rate #
</pre><br />or<br /><pre>
PTP uses main clock
</pre></p>
<p>According to the stmmac driver device tree documentation ( Documentation / devicetree / bindings / net / stmmac.txt) you would need to specify the PTP reference clock node, clk_ptp_ref, in your device tree.</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: RE: OMAP L138 HPIhttp://support.criticallink.com/redmine/boards/11/topics/5726?r=5734#message-57342018-08-28T15:18:21ZAlexander Blockalex.block@criticallink.com
<p>Unfortunately during my initial review of the modules with and without FPGA I confused the RESETOUT (T17) pin connection for the FPGA module.</p>
<p>As you have found T17 from the L138 is not connected to an FPGA IO but is connected to a dedicated pin of the FPGA, V2 which is the PROGRAM_B_2 function. As shown in the Xilinx FPGA documentation (<a class="external" href="https://www.xilinx.com/support/documentation/user_guides/ug385.pdf">https://www.xilinx.com/support/documentation/user_guides/ug385.pdf</a>) this pin is an input only and it's function is a "active-low asynchronous reset to configuration logic".</p>
<p>It currently has a 4.7K pull-up to 1.8V. Presumably when configured as an input on the OMAP-L138 (in the case of the UHPI_HAS# signal) it will always be high (due to the pull-up) at the OMAP-l138 processor and isn't controllable from the FPGA.</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: RE: OMAP L138 HPIhttp://support.criticallink.com/redmine/boards/11/topics/5726?r=5732#message-57322018-08-24T23:12:33ZAlexander Blockalex.block@criticallink.com
<p>You can find the pin-out between the FPGA and the OMAP-L138 processor of the module in the Carrier Board Design Guide (Table 4):</p>
<p><a class="external" href="https://www.criticallink.com/wp-content/uploads/2014/01/MityDSP-L138F-Carrier-Board-Design-Guide.pdf">https://www.criticallink.com/wp-content/uploads/2014/01/MityDSP-L138F-Carrier-Board-Design-Guide.pdf</a></p>
<p>Please let us know if you have any further questions.</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: RE: OMAP L138 HPIhttp://support.criticallink.com/redmine/boards/11/topics/5726?r=5727#message-57272018-08-23T20:15:55ZAlexander Blockalex.block@criticallink.com
<p>I'm not sure that we've used the UHPI interface in any designs nor am I aware of any customers that have utilized the UHPI.</p>
<p>Are you interested in the MityDSP-L138 with or without the FPGA?</p>
<ul>
<li>For the module without the FPGA the UHPI_HINT# (OMAP-L138 Ball R16), UHPI_HRDY (OMAP-L138 Ball R17) and UHPI_DS2# (OMAP-l138 Ball T18) signals are NOT available external to the module. </li>
<li>For the module with the FPGA all UHPI signals are routed to the FPGA so it's possible that they could be interfaced with but a custom FPGA would need to be written.</li>
</ul>
<p>Can you share some details about the Host MPU you are looking to interface with and/or details about the required interface rate and signals required?</p>
<p>Thanks,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: RE: New Design Bringup Questionhttp://support.criticallink.com/redmine/boards/11/topics/5665?r=5674#message-56742018-05-23T14:24:18ZAlexander Blockalex.block@criticallink.com
<p>Thank you for the update! Happy to hear all is working now.</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: RE: New Design Bringup Questionhttp://support.criticallink.com/redmine/boards/11/topics/5665?r=5670#message-56702018-05-22T18:11:06ZAlexander Blockalex.block@criticallink.com
<p>Tom,</p>
<p>Can you comment on J700 concerning the "where" used for +3.3V, SCLK, SIMO and SOMI? I see U901 mentioned for SCLK and SIMO but I'm guessing that's just a typo and it should be U902?</p>
<p>Thanks,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: RE: New Design Bringup Questionhttp://support.criticallink.com/redmine/boards/11/topics/5665?r=5667#message-56672018-05-22T16:48:56ZAlexander Blockalex.block@criticallink.com
<p>Tom,</p>
<p>Sorry for the delay in getting back to you on this issue.</p>
<p>The first step you can take is to see if the MityDSP-L138F processor is working/alive. An easy test would be to power on the module with the serial port connected and then hold the "Boot Me" button on the industrial IO. While holding the "boot me" button down press and release the "Reset" switch on the industrial IO board. You should then see the word "BOOTME" printed on the serial port each time you press the reset button while holding "boot me".</p>
<p>Second you mentioned that you are using some SPI pins from the expansion headers. The pins below interface with the SPI1 interface that has the on-SoM SPI NOR memory which is where UBoot is loaded from by default. Can you confirm if you have anything connected to Industrial IO board expansion header J700 Pin 29 (Module Pin 53)? Additionally do you have anything connected to J700 Pin 11, 13 and 15?</p>
<p>Thank you and hopefully we can resolve this quickly,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: RE: Supplying an external PCBhttp://support.criticallink.com/redmine/boards/11/topics/5526?r=5533#message-55332017-11-28T22:11:37ZAlexander Blockalex.block@criticallink.com
<p>Tom,</p>
<p>We have used these (<a class="external" href="https://www.digikey.com/products/en?keywords=87759-5050">https://www.digikey.com/products/en?keywords=87759-5050</a>) on a couple of our expansion boards for the Industrial IO board. Note that they are surface mount headers.</p>
<p>I believe these (<a class="external" href="https://www.digikey.com/products/en?keywords=0877585016">https://www.digikey.com/products/en?keywords=0877585016</a>) would be a comparable through-hole version but that was just from filtering through the Digikey options and not something I'm aware that we've used.</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: RE: MightyDspL138 Factory Test and labelinghttp://support.criticallink.com/redmine/boards/11/topics/5464?r=5470#message-54702017-10-16T15:13:48ZAlexander Blockalex.block@criticallink.com
<p>Fred,</p>
<p>Thank you for reaching out to us about this question.</p>
<p>During production test the FPGA IO pins at the edge connector are tested as well as those between the OMAP and FPGA. Prior to having you return/RMA the module can you provide a copy of the UCF file that is used for your FPGA image? I'd like to review all the pins that are mapped between the processor and FPGA for your use case. If the UCF is sensitive in nature feel free to e-mail me at <a class="email" href="mailto:block@criticallink.com">block@criticallink.com</a>.</p>
<p>Additionally is this module one that had been operating normally for some amount of time and then began experiencing "warped" data or was it a brand new unit that failed during initial testing?</p>
<p>The best identifier on our products is going to be the lot code which is noted as YY-MM-BB (YY = Year of build, MM = Month of build and BB = build # of the month) on the last line of the product label. For example all units with the 15-03-01 lot code would have been built at the same time.</p>
<p>Sorry for the inconvenience,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - FPGA Development: RE: L138F breakout adapter pinouthttp://support.criticallink.com/redmine/boards/12/topics/5436?r=5438#message-54382017-09-26T19:22:33ZAlexander Blockalex.block@criticallink.com
<p>Tom,</p>
<p>You can find the pin-out of the JTAG adapter board in the datasheet for the board (<a class="external" href="http://www.criticallink.com/wp-content/uploads/80-000286_L138_Debug_Adapter.pdf">http://www.criticallink.com/wp-content/uploads/80-000286_L138_Debug_Adapter.pdf</a>).</p>
<p>Please let us know if you need anything else,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: To make the connection between DS...http://support.criticallink.com/redmine/boards/10/topics/5350?r=5353#message-53532017-06-28T17:22:26ZAlexander Blockalex.block@criticallink.com
<p>Our MDK provides an example utilizing TI's DSPLINK software to share data between the ARM and DSP cores of the OMAP-L138 processor. Other example DSP example code is also included in the MDK.</p>
<p>This wiki page (<a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Quick_Start">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Quick_Start</a>) describes what example is included in the MDK and how to use it under the "Quick Start using ARM/linux to load Application via DSPLINK" section at the bottom of the page.</p>
<p>The MDK can be downloaded from this wiki page (<a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Board_Support_Package">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Board_Support_Package</a>) with the latest release still being the Jan-2014 release.</p>
<p>Please let us know if you still have questions after reviewing the above information.</p>
<p>Thank you,</p>
<p>Alex</p> MitySOM-5CSX Altera Cyclone V - FPGA Development: RE: Power fail interruphttp://support.criticallink.com/redmine/boards/47/topics/5343?r=5346#message-53462017-06-20T17:59:19ZAlexander Blockalex.block@criticallink.com
<p>Clyde,</p>
<p>Offhand our recommendation would be to utilize an HPS GPIO and have it configured in the GPIO controller as an interrupt.</p>
<p>Additionally it would be pertinent to know how long you expect power to persist after this interrupt is triggered. A lot of our specific software recommendations depend on the time the module remains powered.</p>
<p>Can you please describe what you are trying to protect with these "necessary precautions". Are you trying to prevent data loss, allow your application to complete its current process, shut-down the OS completely or something else? With this information we can provide a more detailed response and recommendation.</p>
<p>Thank you,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: RE: Analog input and outpurhttp://support.criticallink.com/redmine/boards/11/topics/5340?r=5341#message-53412017-06-19T18:59:09ZAlexander Blockalex.block@criticallink.com
<p>Andri,</p>
<p>Thank you for your inquiry.</p>
<p>Our standard MitySOM-L138F development kit (<a class="external" href="http://www.criticallink.com/product/mitydsp-l138f-dev-kit/">http://www.criticallink.com/product/mitydsp-l138f-dev-kit/</a>) does not feature either an analog to digital converter (ADC) or digital to analog converters (DAC).</p>
<p>Are you using a custom carrier board that has ADC or DAC components? If so please provide detailed part numbers and I can see if we have any sample software that may be helpful.</p>
<p>Thank you,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: Increasing Memory RAMhttp://support.criticallink.com/redmine/boards/10/topics/5319?r=5320#message-53202017-06-01T22:37:04ZAlexander Blockalex.block@criticallink.com
<p>Alex,</p>
<p>To begin with can you confirm the module model number you are utilizing specifically? I.e. 1810-DG-225-RC</p>
<p>Unfortunately the AM1810/OMAP-L138 family of processors is limited to a maximum of memory space of 256MByte as shown in the processor datasheet Section 6.11 (<a class="external" href="http://www.ti.com/lit/ds/symlink/am1810.pdf">http://www.ti.com/lit/ds/symlink/am1810.pdf</a>) or (<a class="external" href="http://www.ti.com/lit/ds/symlink/omap-l138.pdf">http://www.ti.com/lit/ds/symlink/omap-l138.pdf</a>). We do have modules available that feature the maximum supported 256MB RAM size.</p>
<p>Can you please provide some details about your specific design requirement and goals? We'd like to see if we can find an alternative solution to needing such a large amount of physical RAM, i.e. can some other storage type be used on the module or carrier board to meet your goals.</p>
<p>Thanks,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: Does BUSY led mean something on f...http://support.criticallink.com/redmine/boards/10/topics/5200?r=5221#message-52212017-04-10T18:47:30ZAlexander Blockalex.block@criticallink.com
<p>Jacek,</p>
<p>Thank you for confirming which processor was used in the replacement. Based on the lack of the "BOOTME" from the processor it certainly sounds like the module is unrecoverable.</p>
<p>In the future please note that if we are notified about a suspect module failure you could have worked with the supplier where the module/dev kit was purchased from to get the unit replaced under our standard 1 year warranty. However replacing the processor yourself voids any warranty that Critical Link would have provided.</p>
<p>Our recommendation is to obtain another module from one of our distribution partners and to "scrap" this module.</p>
<p>Please let me know if you require any assistance in purchasing a replacement.</p>
<p>Thank you,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: Does BUSY led mean something on f...http://support.criticallink.com/redmine/boards/10/topics/5200?r=5217#message-52172017-04-06T15:04:47ZAlexander Blockalex.block@criticallink.com
<p>Thank you for confirming the part markings on the OMAP-L138 processor. Best I can tell mean this is likely not a secure boot enabled processor. Unfortunately I could not find a document from TI that covers the package markings enough to confirm how/where the marking to show Secure Boot would be shown. To confirm if this were a secure boot enabled processor I would need the part number that was ordered.</p>
<p>Taking a step back have you confirmed that even the "BOOTME" message is not shown by the OMAP-L138 boot-rom?<br />1) Connect your PC serial port to the Industrial IO Dev Board (115200 8-n-1) A NULL modem adapter typically is needed, be sure to confirm this with the working board you have to ensure the setup is correct.<br />2) With the problem module installed hold the "BOOT" button the dev board<br />3) Apply power to the dev board<br />4) You shout see a single "BOOTME" printed on the serial port</p>
<p>However again based on the operation of the BUSY led and inability to boot it sounds like the module has become damaged during the removal and re-installation of the processor. At this time we would recommend you purchase a new module from the same distributor used to obtain the original. Can you share with me what you were trying to accomplish by replacing the processor, if not for secure boot?</p>
<p>Thank you,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: Does BUSY led mean something on f...http://support.criticallink.com/redmine/boards/10/topics/5200?r=5214#message-52142017-04-05T14:02:01ZAlexander Blockalex.block@criticallink.com
<p>Unfortunately we need more clarification on the part number of the processor that was installed. The "B" would presumably be in reference to the revision field (Rev 2.0 or 2.1) and an "E" for that field would be Rev 2.3. However the "Secure Boot" enabled processor is denoted by an "E" at the end of processor part number. Please provide the part number of the processor installed (i.e. OMAPL138EZWTD4E).</p>
<p>In either case it appears that the FPGA became damaged during the removal and/or re-installation process of the OMAP_L138 processor as again we do not expect that LED to be lit under normal circumstances unless programmed to do so.</p>
<p>If the OMAP-L138 processor that was originally installed on our module has been removed and replaced with the "Secure Boot" enabled version we would not expect you to be able to boot the module unless you have developed a compatible secure boot enabled bootloader.</p>
<p>At this time Critical Link does not offer support for the Secure Boot enabled processors.</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - FPGA Development: RE: FPGA pins in Mity DSP L138Fhttp://support.criticallink.com/redmine/boards/12/topics/5211?r=5213#message-52132017-04-05T13:51:46ZAlexander Blockalex.block@criticallink.com
<p>Shalini,</p>
<p>You can find the mapping of MityDSP-L138F pins from the Edge Connector to the specific balls on both the OMAP-L138 processor and Xilinx Spartan 6 FPGA from the module datasheet (<a class="external" href="http://www.criticallink.com/wp-content/uploads/2014/01/MityDSP-L138F_Spec.pdf">http://www.criticallink.com/wp-content/uploads/2014/01/MityDSP-L138F_Spec.pdf</a>). This is located in Table 1 of that document on pages 5 to 7.</p>
<p>The Xilinx Spartan 6 package used on the module is the CSG324 type. Each module variant utilizes one of a few different specific Xilinx part numbers and we would recommend that you refer to the part markings on your specific module to determine which FPGA is installed (i.e. LX16 Industrial Temperature vs LX45 Commercial Temperature, etc.).</p>
<p>I hope this answers your questions but let us know if you need any further assistance,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: Does BUSY led mean something on f...http://support.criticallink.com/redmine/boards/10/topics/5200?r=5205#message-52052017-04-04T19:21:52ZAlexander Blockalex.block@criticallink.com
<p>Jacek,</p>
<p>Sorry to hear that you're having an issue with one of the modules.</p>
<p>Can you please provide the serial number of the module which is located on a label on the back/bottom side of the module and is 8 numeric characters in length?</p>
<p>The "BUSY" LED is tied to the FPGA DOUT_BUSY signal which during initial boot into UBoot should not be lit under normal operation. Even when programmed the BUSY LED is typically not utilized unless programmed to do so in the FPGA.</p>
<p>What carrier board is this module being used in, custom or a MityDSP-L138 Industrial IO Dev Board? Additionally any history about the modules prior operation/history would be helpful.</p>
<p>Thank you,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: RE: FPGA CLOCK LOCATIONhttp://support.criticallink.com/redmine/boards/11/topics/5152?r=5153#message-51532017-01-31T18:48:17ZAlexander Blockalex.block@criticallink.com
<p>Alex,</p>
<p>Thank you for reaching out to us about this question.</p>
<p>On our MitySOM-L138F family modules we have the EMIF bus from the OMAP-L138 connected to the Xilinx Spartan 6 FPGA to allow for communications of cores between the processor and FPGA (as shown on this Architecture Wiki page <a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/MityDSP-L138_Architecture">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/MityDSP-L138_Architecture</a>).</p>
<p>As such the 100MHz clock from the EMIF bus is available at the FPGA. In our example FPGA project that is included with the MityDSP-L138 MDK (<a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Board_Support_Package">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Board_Support_Package</a>) we have the following signal:</p>
<pre>
i_ema_clk : in std_logic; -- 100 MHz EMIF clock
</pre>
<p>That signal is connected in our UCF file to ball T8 of the FPGA</p>
<pre>
NET "i_ema_clk" LOC = "T8" | IOSTANDARD = LVCMOS33 ;
</pre>
<p>Which is wired on the MitySOM-L138 PCB between the FPGA and OMAP-L138 processor.</p>
<p>You can find this example FPGA top level .vhdl file in the MDK under the following location</p>
<pre>
MDK_2014-01-13\examples\industrial_io\fpga\vhdl\IndustrialIO_top.vhd
and corresponding UCF
MDK_2014-01-13\examples\industrial_io\fpga\vhdl\IndustrialIO_rev_C.ucf
</pre>
<p>If you are working in the Windows OS for ISE you can download a copy of the MDK in .zip format for Windows from this link (<a class="external" href="https://www.dropbox.com/s/aczq8eevf74a1x5/MDK_2014-01-13.zip?dl=0">https://www.dropbox.com/s/aczq8eevf74a1x5/MDK_2014-01-13.zip?dl=0</a>)</p>
<hr />
<p>Please note that we do provide a number of FPGA cores which include both ARM and DSP drivers for said cores, including a UART core. We would highly recommend that you start with our example as the basis for your project to properly utilize the EMIF interface between the L138 and FPGA and then add in the necessary cores to your design. This page (<a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Core_Device_Drivers">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Core_Device_Drivers</a>) provides more information about our FPGA Cores and an example of implementing one.</p>
<p>Hopefully this answers your question but please let us know if we can help further.</p>
<p>Alex</p> MitySOM-5CSX Altera Cyclone V - Software Development: RE: 5CSX-H6-42A Dev.Kit does not boot from SDhttp://support.criticallink.com/redmine/boards/45/topics/5135?r=5146#message-51462017-01-16T17:17:26ZAlexander Blockalex.block@criticallink.com
<p>Ben,</p>
<p>Thank you for providing the device specific details.</p>
<p>I wanted to let you know that on Friday 1/13/2017 I sent you an e-mail requesting additional company specific information, that I wasn't sure you would want to post on the forum, to better assist with this issue and RMA if necessary.</p>
<p>Thank you,</p>
<p>Alex</p> MitySOM-335x Maker Transition Kit - Transforming Maker Prototype to Production-Ready Design.pdfhttp://support.criticallink.com/redmine/attachments/13194/Transforming%20Maker%20Prototype%20to%20Production-Ready%20Design.pdf2016-12-14T10:30:09ZAlexander Blockalex.block@criticallink.comMitySOM-335x Maker Transition Kit - 60-000019_MitySOM-335x_Maker_Transition_Kit_User_Guide.pdfhttp://support.criticallink.com/redmine/attachments/13192/60-000019_MitySOM-335x_Maker_Transition_Kit_User_Guide.pdf2016-12-14T10:25:44ZAlexander Blockalex.block@criticallink.comMityDSP-L138 (ARM9 Based Platforms) - FPGA Development: RE: Communication EGD or ModBus/TCP Coreshttp://support.criticallink.com/redmine/boards/12/topics/4946?r=4953#message-49532016-07-26T16:41:03ZAlexander Blockalex.block@criticallink.com
<p>Hector,</p>
<p>Concerning the Vivado question:</p>
<p>At this time we do not recommend using Vivado as it does not support the Spartan 6 based devices. We recommend Xilinx ISE 14.X and frankly to begin with you can start with their free webpack versions until you need to implement chipscope or other features of the paid version.</p>
<p><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Overview">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Overview</a></p>
<p>Hope this helps,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - FPGA Development: RE: Communication EGD or ModBus/TCP Coreshttp://support.criticallink.com/redmine/boards/12/topics/4946?r=4948#message-49482016-07-20T15:21:28ZAlexander Blockalex.block@criticallink.com
<p>Hector,</p>
<p>I spoke with Jon C. about this issue and we have a little more followup.</p>
<p>In the past for the MitySOM/DSP-L138 family of modules we have utilized Modbus/TCP however it was implemented on the ARM processor in Linux using the <a href="http://libmodbus.org/" class="external">libmodbus</a> library. We have done Modbus implementations on other processor platforms as well but never in the FPGA itself. If you have a reason to implement it in the FPGA we unfortunately don't have guidance at this time.</p>
<p>There is a 5 year old Modbus FPGA core from <a href="http://opencores.org/project,modbus" class="external">OpenCores</a> however we have no experience with it.</p>
<p>We have never implemented EGD to my knowledge.</p>
<p>Thank you,</p>
<p>Alex</p> MitySOM-5CSX Altera Cyclone V - Software Development: RE: Why do I get a "CALIBRATION FAILED" err...http://support.criticallink.com/redmine/boards/45/topics/4919?r=4927#message-49272016-06-30T11:08:23ZAlexander Blockalex.block@criticallink.com
<p>Malcolm,</p>
<p>Thanks for catching the typo, it's been updated.</p>
<p>With the CSEL "properly" set and the module still not operating as expected it does still appear that an RMA will still need to be done for us to dig into the issue further.</p>
<p>Alex</p> MitySOM-5CSX Altera Cyclone V - Software Development: RE: Why do I get a "CALIBRATION FAILED" err...http://support.criticallink.com/redmine/boards/45/topics/4919?r=4924#message-49242016-06-29T10:01:42ZAlexander Blockalex.block@criticallink.com
<p>Malcolm,</p>
<p>Dan and Adam brought this issue to my attention and I will followup concerning the RMA replacement via e-mail.</p>
<p>Please note that the current Development Kit Hardware Quickstart Guide (<a class="external" href="https://support.criticallink.com/redmine/documents/248">https://support.criticallink.com/redmine/documents/248</a>) directs customers to utilize the "00" CSEL setting which matches how current development boards are shipped. We actually added some comments about the CSEL settings (and a number of other items) in the following Wiki page (<a class="external" href="https://support.criticallink.com/redmine/projects/5csxbase/wiki/Carrier_Board_Design_Gotchas">https://support.criticallink.com/redmine/projects/5csxbase/wiki/Carrier_Board_Design_Gotchas</a>).</p>
<p>Thank you,</p>
<p>Alex</p> MitySOM-5CSX Altera Cyclone V - PCB Development: RE: Development Kit 2.5V VIO, change to 3.0 or 3.3http://support.criticallink.com/redmine/boards/46/topics/4912?r=4916#message-49162016-06-23T16:47:00ZAlexander Blockalex.block@criticallink.com
<p>Stephen,</p>
<p>Thanks for reaching out to us about this question.</p>
<p>Please note that making any modification to the carrier board, such as this, will void any warranty for both the carrier board and any module used in that board.</p>
Unfortunately the only way to easily change the IO bank voltages to support 3.0V/3.3V is to do as you described, change the output voltage of the U601 component from 2.5V to your desired voltage. This change is not expected to cause any negative impact however you will NEED to ensure the following:
<ul>
<li>Your FPGA project must be rebuilt to support the new voltage levels for the affected pins. </li>
<li>Your SD card/boot media must be updated with pre-loader and UBoot as well based upon the new FPGA image.</li>
<li>All Bank 3B, 4A, 8A and 3A5A5B (for expanded IO modules) IO pins are affected</li>
<li>Thus all HSMC pins will be affected by the change to U601</li>
</ul>
For the specific case of setting U601 to output <strong>3.3V</strong> you would need to change the combination of R603 (ships as 12.1K) and R613 (ships as 12.1K) to total ~36.0K ohms on the development board.
<ul>
<li>Remove either R603 or R613 and replace ONE of them with a ~23.7K ohm 1% resistor</li>
<li>Please note that these are 0402 sized SMD resistors</li>
<li>The value change for R603 or R613 was determined based upon leaving R616 as the original 11.5K value</li>
</ul>
<p>Please reference the LT3502IDC#TRMPBF datasheet (<a class="external" href="http://cds.linear.com/docs/en/datasheet/3502fd.pdf">http://cds.linear.com/docs/en/datasheet/3502fd.pdf</a>), page 21, for their "typical application" resistor values and page 10 for the FB resistor calculation.</p>
<p>Please note that we have operated the development board at voltages other than the 3.3V discussed above and the standard 2.5V (i.e .3,0V and 1.8V). Please follow the LT3502 datasheet calculations closely if utilizing other voltage levels.</p>
<p>Thank you,</p>
<p>Alex</p> MitySOM-5CSX Altera Cyclone V - Software Development: RE: Building BSP for 5csehttp://support.criticallink.com/redmine/boards/45/topics/4911?r=4913#message-49132016-06-23T11:17:45ZAlexander Blockalex.block@criticallink.com
<p>Sam,</p>
<p>I believe that the issue you ran into if following the Yocto wiki steps is that you may have selected the "mitysom-5csx" machine type as shown in the instructions. In your specific case you would actually want to select the "mitysom-5cse" machine type as that corresponds to the 80-000708 dev kit.</p>
<p>We have updated the Yocto wiki page to cover the different module types during the filesystem build process (<a class="external" href="https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Yocto_for_MitySOM-5CSX">https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Yocto_for_MitySOM-5CSX</a>).</p>
<p>After performing a build with the correct machine type you should be able to untar the rootfs onto the SD card and boot properly.</p>
<p>Let us know if that doesn't resolve your problem and we'll continue looking into it further.</p>
<p>Thanks,</p>
<p>Alex</p> MitySOM-5CSX Altera Cyclone V - FPGA Development: RE: HDMI Output and Quartus Versionshttp://support.criticallink.com/redmine/boards/47/topics/4904?r=4906#message-49062016-06-20T13:15:33ZAlexander Blockalex.block@criticallink.com
<p>Steve,</p>
<p>We have successfully rebuilt the <a href="https://support.criticallink.com/redmine/projects/5csxbase/wiki/HDMI_Output" class="external">HDMI example</a> using Quartus 14.1 however you will require a license to support the VIP Suite (Video and Image Processing Suite MegaCore Functions).</p>
<p>You can find out information about licensing from this page: <a class="external" href="https://www.altera.com/products/intellectual-property/ip/dsp/m-alt-vipsuite.html">https://www.altera.com/products/intellectual-property/ip/dsp/m-alt-vipsuite.html</a></p>
<p>Thank you,</p>
<p>Alex</p> MitySOM-5CSX Altera Cyclone V - Software Development: RE: How to add aditional HPS GPIO'shttp://support.criticallink.com/redmine/boards/45/topics/4148?r=4905#message-49052016-06-20T13:10:05ZAlexander Blockalex.block@criticallink.com
<p>Maetthew,</p>
<p>Good catch. Apparently when I did the mapping I started off by one. We have updated the post above to have the correct mapping and also the associated wiki page (<a class="external" href="https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Linux_GPIO_Chip_Mapping">https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Linux_GPIO_Chip_Mapping</a>).</p>
<p>You are correct that you need to remove the switches from the device tree to use them as GPIO's.</p>
<p>Thanks,<br />Alex</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: RE: Questions about my product versionhttp://support.criticallink.com/redmine/boards/11/topics/4861?r=4863#message-48632016-06-02T13:22:20ZAlexander Blockalex.block@criticallink.com
<p>Hector,</p>
<p>To determine the model of a specific module please refer to the label that is located on the bottom side of the module.</p>
<p>For example you would see the 1810-FG-225-RC which would mean that the module is an AM1810 processor. Other information is included on that label but the model number is what you are looking for.</p>
<p>The naming and labeling you mention on the top of the PCB has changed over time and as you can see different variants exist. The label on the bottom is the most reliable way of identification.</p>
<p>Let us know if you have any other questions.</p>
<p>Alex</p> MitySOM-5CSX Baseboard - MitySOM-5CSX_Quickstart_94-900274-2_RevD.pdfhttp://support.criticallink.com/redmine/attachments/11081/MitySOM-5CSX_Quickstart_94-900274-2_RevD.pdf2016-05-26T06:49:54ZAlexander Blockalex.block@criticallink.comMityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: No Prompt from Uboothttp://support.criticallink.com/redmine/boards/10/topics/4774?r=4783#message-47832016-04-19T16:35:32ZAlexander Blockalex.block@criticallink.com
<p>Ian,</p>
<p>Can you let us know if the behavior changes when this module is used in the Industrial IO Development Board (80-000268) assuming you have one? I believe all of your testing has been done with/in your own custom carrier board correct?</p>
<p>Additionally do you have a second module with which you can attempt to reproduce the problems you are experiencing or is this the only module you have?</p>
<p>Please feel free to provide the serial number from the label of the module and I can check into the warranty status of the module with our production team.</p>
<p>Thank you,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: Problem using XDS200 USB emulator.http://support.criticallink.com/redmine/boards/10/topics/4735?r=4736#message-47362016-04-07T15:46:23ZAlexander Blockalex.block@criticallink.com
<p>Edwin,</p>
<p>Unfortunately we have not used the XDS200 on any platform so we don't even have one to try and reproduce this issue. I'm sure this is just outdated information but section 7.1 of this wiki <a class="external" href="http://processors.wiki.ti.com/index.php/OMAP-L138_Software_Design_Guide#TI_XDS_Hardware_Emulators">http://processors.wiki.ti.com/index.php/OMAP-L138_Software_Design_Guide#TI_XDS_Hardware_Emulators</a> only recommends the XDS100, XDS510 and XDS560 emulators.</p>
<p>That being said this E2E post mentions that a Full License must be used on CCS to support the Emulator (<a class="external" href="https://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/287193">https://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/287193</a>).</p>
<p>Our recommended emulator is the XDS510 (<a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Development_Tools">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Development_Tools</a>) where possible.</p>
<p>Thanks,</p>
<p>Alex</p> MitySOM-5CSX Altera Cyclone V - Software Development: RE: Xubuntu VM corrupt zip errorhttp://support.criticallink.com/redmine/boards/45/topics/4677?r=4685#message-46852016-02-23T12:34:30ZAlexander Blockalex.block@criticallink.com
<p>John,</p>
<p>Thank you for updating us on this, happy to hear you're up and running.</p>
<p>Keep in mind that we have additional information about this module fmaily/development kit on this wiki page (<a class="external" href="https://support.criticallink.com/redmine/projects/5csxbase/wiki">https://support.criticallink.com/redmine/projects/5csxbase/wiki</a>).</p>
<p>Alex</p> MitySOM-5CSX Altera Cyclone V - Software Development: RE: Xubuntu VM corrupt zip errorhttp://support.criticallink.com/redmine/boards/45/topics/4677?r=4679#message-46792016-02-22T16:57:46ZAlexander Blockalex.block@criticallink.com
<p>John,</p>
<p>Sorry about the delay in getting back to you. We have received your e-mail as well.</p>
<p>As you have found it appears that a number of the USB drives were copied with a corrupt .ova file and were not caught prior to shipment. We've improved our process to perform additional checks but prior stock did not get updated.</p>
<p>The latest version of the VM can be found from a link on this wiki page (<a class="external" href="https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Linux_Build_Virtual_Machine">https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Linux_Build_Virtual_Machine</a>). By downloading the latest .ova file directly from there your issues should be resolved.</p>
<p>Of course let us know if you still are having problems and we can look into it further.</p>
<p>Thanks,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: LCD Framebuffer Problemhttp://support.criticallink.com/redmine/boards/10/topics/4558?r=4579#message-45792015-12-04T15:11:57ZAlexander Blockalex.block@criticallink.com
<p>Se-Sang,</p>
<p>Please download the following .zip file (<a class="external" href="https://www.dropbox.com/s/hf8l6wqtxa72a04/lcd_xilinx_13_2-2-1-13.zip?dl=0">https://www.dropbox.com/s/hf8l6wqtxa72a04/lcd_xilinx_13_2-2-1-13.zip?dl=0</a>) which contains source code as well as a pre-built LX45 binary image that supports the LCD display for the L138 development kit. The binary image you would want to use is the "industrialio_lcd_lx45.bin". This was built using Xilinx 13.2.</p>
<p>Additionally I have attached a sample script that can be used to load the FPGA from Linux, the necessary drivers and set the backlight as well. Note that once loaded you should see a blue screen displayed on the LCD display even without using the fb_fill test. This script is based upon all items being located in the /home/root/ directory.</p>
<p>Hopefully this FPGA build resolves the issue but please let us know the outcome.</p>
<p>I have attached a copy of the driver boards schematic in PDF format as well.</p>
<p>Thank you,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: FPGA load failhttp://support.criticallink.com/redmine/boards/10/topics/4416?r=4478#message-44782015-07-01T10:21:09ZAlexander Blockalex.block@criticallink.com
<p>Bruce,</p>
<p>1) Can you please provide a complete boot log spanning from when the module is first powered on and including the CRC checks you are performing on the NAND memory?</p>
<p>2) Can you confirm how many months these units have been sitting in storage more exactly?</p>
<p>We are looking into providing some further guidance but want to have a better idea of what code base is being utilized by the module (Uboot) currently.</p>
<p>Thank you.</p> MitySOM-5CSX Altera Cyclone V - FPGA Development: RE: HSMC1 pinouthttp://support.criticallink.com/redmine/boards/47/topics/4434?r=4444#message-44442015-05-28T11:08:44ZAlexander Blockalex.block@criticallink.com
<p>Floria,</p>
<p>A) We confirmed that the .tcl script is in fact incorrect for that pin-assignment.</p>
<p>Correct pin assignment (as you noted):</p>
<pre>
set_location_assignment PIN_AF27 -to HSMC1_SMSCL
set_location_assignment PIN_AF28 -to HSMC1_SMSDA
</pre>
<p>Note that we have more up to date examples and .tcl scripts in our example project GIT repos however the SCL/SDA pin swap is still present, but will be addressed in the next release/update.</p>
<table>
<tr>
<td> </td>
<td> <strong>On the Virtual Machine</strong> </td>
<td> <strong>On the Support git Server</strong> </td>
</tr>
<tr>
<td> <strong>5CSX Base</strong> </td>
<td> /home/user/mitysom_5csx_dev_board/base_project </td>
<td> <a class="external" href="http://support.criticallink.com/gitweb/?p=mitysom-5cs/mitysom_5csx_dev_board.git;a=summary">http://support.criticallink.com/gitweb/?p=mitysom-5cs/mitysom_5csx_dev_board.git;a=summary</a> </td>
</tr>
<tr>
<td> <strong>5CSE Expanded IO</strong> </td>
<td> /home/user/mitysom_5cse_dev_board/dev_exp_5cse_l2_3y8_base </td>
<td> <a class="external" href="http://support.criticallink.com/gitweb/?p=mitysom-5cs/mitysom_5cse_dev_board.git;a=summary">http://support.criticallink.com/gitweb/?p=mitysom-5cs/mitysom_5cse_dev_board.git;a=summary</a> </td>
</tr>
</table>
<p>B) Concerning the datasheet discrepancy it has HSMC1_SMSDA and HSMC1_SMSCL mapped to the proper HSMC pins however the SoM pin column is incorrect for these pins. HSMC1_SMSDA should be SoM pin 52 and HSMC1_SMSCL should be SoM pin 54. You are correct on the bank voltage 3B vs 4A discrepancies.</p>
<p>We have created action items for these discrepancies (the datasheet ones were already noted just not published yet unfortunately) and will get them addressed.</p>
<p>C) Concerning the direction change for the HSMC1 pins mentioned if your usage for them is low speed then that should be fine however if you are trying to do high speed, I.E. use the HSMC1_CLKOUT0 as a CLK input, you may run into issues. If you have further concerns about this please let us know what specific use case you have planned for each pin and we can provide some feedback and/or recommendations.</p>
<p>Thanks,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: FPGA load failhttp://support.criticallink.com/redmine/boards/10/topics/4416?r=4432#message-44322015-05-20T11:27:02ZAlexander Blockalex.block@criticallink.com
<p>Bruce,</p>
<p>I am working with our team here to determine the best way we can assist you further with this issue/request.</p>
<p>I did want to check concerning the NOR memory option, did that end up not working for you?</p>
<p>Thanks,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: FPGA load failhttp://support.criticallink.com/redmine/boards/10/topics/4416?r=4426#message-44262015-05-14T16:04:29ZAlexander Blockalex.block@criticallink.com
<p>Bruce,</p>
<p>The architecture for the SPI NOR is accurate.</p>
<p>Ideally you would use the 7MB of space starting at 0x100000 for your images. The reserved space starting at 0x600000 is not used for anything and can be used for user files.</p>
<p>Hopefully that provides enough room for your images.</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: FPGA load failhttp://support.criticallink.com/redmine/boards/10/topics/4416?r=4423#message-44232015-05-13T16:03:20ZAlexander Blockalex.block@criticallink.com
<p>Bruce,</p>
<p>Sorry that you are running into this issue.</p>
<p>As shown in our standard MityDSP-L138 architecture page (<a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/MityDSP-L138_Architecture">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/MityDSP-L138_Architecture</a>) we only usually store the file systems in NAND, not the kernel or FPGA images.</p>
<p>I definitely would recommend that you use the SPI NOR to store your FPGA image as that is where we typically load it from. Typically NAND is used to store the FPGA image if we are using Linux and the image is store in the root/user filesystem.</p>
<p>This wiki page covers the steps on storing and booting the FPGA image from NOR: <a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA</a></p>
<p>Keep us updated!</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: DSP core startinghttp://support.criticallink.com/redmine/boards/10/topics/4401?r=4408#message-44082015-04-23T12:02:50ZAlexander Blockalex.block@criticallink.com
<p>Oleh,</p>
<p>I have updated the programming Wiki (<a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Quick_Start">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Quick_Start</a>) to include how to store your DSP.out file to the SPI NOR Flash memory and how to boot the DSP from that memory device during the boot process automatically.</p>
<p>It's possible that you can use NAND or an SD card as well but in this case where the ARM processor will not be used the NOR memory is ideal as we place the DSP image into the Kernel address space of the NOR memory.</p>
<p>Thanks,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: DSP core startinghttp://support.criticallink.com/redmine/boards/10/topics/4401?r=4404#message-44042015-04-22T16:56:50ZAlexander Blockalex.block@criticallink.com
<p>Oleh,</p>
<p>I am working on adding some documentation to our DSP programming Wiki.</p>
<p>However in the meantime can you confirm if you are looking to use the ARM core (and Linux) in addition to the DSP or are you just trying to treat the module as a DSP only device? I.E. never booting past UBoot</p>
<p>Thanks,</p>
<p>Alex</p> MitySOM-5CSX Baseboard - MitySOM-5CSx_VM_Setup_Procedure_RevB.pdfhttp://support.criticallink.com/redmine/attachments/7838/MitySOM-5CSx_VM_Setup_Procedure_RevB.pdf2015-04-16T15:39:37ZAlexander Blockalex.block@criticallink.comMityDSP-L138 (ARM9 Based Platforms) - FPGA Development: RE: Mity L138F FPGA -> OMAP interrupt lineshttp://support.criticallink.com/redmine/boards/12/topics/4198?r=4382#message-43822015-03-23T17:08:47ZAlexander Blockalex.block@criticallink.com
<p>Chris,</p>
<p>Hopefully you happened upon this on your own but the details for the pin-configuration, voltage standards, can be found in the sample .ucf files we provide in the MDK BSP (<a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Board_Support_Package">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Board_Support_Package</a>).</p>
<p>From that file:<br /><pre>
NET "o_nmi_n" LOC = "N8" | IOSTANDARD = LVCMOS33 ;
NET "o_int<0>" LOC = "K6" | IOSTANDARD = LVCMOS18;
NET "o_int<1>" LOC = "F2" | IOSTANDARD = LVCMOS18;
</pre></p> MityDSP-L138 (ARM9 Based Platforms) - FPGA Development: RE: FPGA serial programming interfacehttp://support.criticallink.com/redmine/boards/12/topics/4375?r=4381#message-43812015-03-12T11:06:27ZAlexander Blockalex.block@criticallink.com
<p>We are happy to provide further assistance with this issue, however I will be contacting you directly at your e-mail address that is on-file.</p>
<p>Thank you.</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - FPGA Development: RE: FPGA serial programming interfacehttp://support.criticallink.com/redmine/boards/12/topics/4375?r=4379#message-43792015-03-11T10:18:51ZAlexander Blockalex.block@criticallink.com
<p>I discussed this with one of our engineers here and it may be possible however they is likely a bit of work required in order to make it functional.</p>
<p>As well he wanted to know what the reasoning is behind programming the FPGA in the Slave Serial mode vs the current 8-bit parallel?</p>
<p>Thank you.</p> MityDSP-L138 (ARM9 Based Platforms) - FPGA Development: RE: FPGA serial programming interfacehttp://support.criticallink.com/redmine/boards/12/topics/4375?r=4378#message-43782015-03-11T08:32:54ZAlexander Blockalex.block@criticallink.com
<p>SB,</p>
<p>I apologize.</p>
<p>The M0 and M1 FPGA pins are tied to resistors on the module to GND (M0) and 3.3V (M1) forcing the mode to Slave SelectMAP. The CCLK and DIN connections are tied to the OMAP-L138 processor.</p>
<p>It may be possible to "remove" the M0 and M1 resistors which would allow the internal default pull-up signals to allow the Slave Serial mode to be used (Note 4 - Page 23: <a class="external" href="http://www.xilinx.com/support/documentation/user_guides/ug380.pdf">http://www.xilinx.com/support/documentation/user_guides/ug380.pdf</a>). I will work with some of our engineering staff to see if there are any further considerations.</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - FPGA Development: RE: FPGA serial programming interfacehttp://support.criticallink.com/redmine/boards/12/topics/4375?r=4376#message-43762015-03-10T17:01:06ZAlexander Blockalex.block@criticallink.com
<p>SB,</p>
<p>The FPGA is configured using 8 bit parallel slave select mode via the EMIFA bus connection to the Omap L138 processor.</p>
<p>Please reference this Wiki page for information about programming the FPGA: <a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA</a></p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: DSP/BIOS issue MityDSP-L138http://support.criticallink.com/redmine/boards/10/topics/4278?r=4280#message-42802014-12-18T22:41:26ZAlexander Blockalex.block@criticallink.com
<p>Oleh,</p>
<p>Can you please share some more details about this issue if it is still occurring?</p>
<p>It looks to me like Uboot is interpreting the file as text and trying to execute the commands.</p>
<p>Presumably the DSP has not taken control of the UART which is why UBoot/the ARM processor is handling the file. Can you provide some details about this file you are trying to send and the method you are doing so in Hyperterm?</p>
<p>Thank you,</p>
<p>Alex</p> MitySOM-5CSX Altera Cyclone V - FPGA Development: 100MHz Input clock (CLK2 - DDR3) Issuehttp://support.criticallink.com/redmine/boards/47/topics/42792014-12-11T19:50:32ZAlexander Blockalex.block@criticallink.com
<p>A customer has the 100MHz DDR3 clock being fed into the module through Pins 117 and 119 on a custom carrier board and is using it to clock some ADC data. However after a little run-time it stops working as noted below:</p>
<pre>
I'm having a really weird problem with the DDR3 100Mhz clock. I included this in my design from your eval board, however I am not
using it as a clock for the FPGA RAM. I'm using it to clock out two ADC clocks. That aspect of the design works fine. Its when I use the
clock internally that I run into problems.
Case in point: I have a logic block that uses this clock as a count down to initiate a burst of a FIFO-full of ADC input data. With this clock,
I set a timer to fill the buffer full of data every 5 seconds. The frustrating part of this is that it WORKS for about 10-15 fifo-fuls of data but then
it stops. As best I can tell, the millisecond strobe I use based off this clock stops being registered by the logic so it sits in the idle stage.
When I used the 100Mhz HPS user 0 clock instead, it works like a charm.
The DDR3Clock goes through an altera_pll block with a multiplier of 1 so it just basically goes through.
Any idea how I can get this to work?
</pre> MityCAM Vision Cameras - Support: Welcome to the MityCAM Support Forumshttp://support.criticallink.com/redmine/boards/21/topics/42512014-11-11T11:41:10ZAlexander Blockalex.block@criticallink.com
<p>Thank you for visiting our MityCAM support forums.</p>
<p>Please feel free to post regarding any of our MityCAM products here. Please include the following so our engineering team, whom monitors these forums, can assist you quickly:</p>
<ul>
<li>Camera Model Number</li>
<li>Image Capture Mode/Device (Cameralink, ethernet, USB, etc.)</li>
<li>Image viewer application and version (MityViewer, EPIX, National Instruments, etc.)</li>
<li>Detailed background of the issue and current behaviors</li>
</ul>
<p>With that information and more our team will be happy to assist you with your MityCAM product(s).</p> MitySOM-335x (ARM Cortex-A8 Based Products) - Software Development: RE: Communicating with an 8-b...http://support.criticallink.com/redmine/boards/28/topics/4231?r=4240#message-42402014-10-27T16:10:11ZAlexander Blockalex.block@criticallink.com
<p>Updated question(s) from the customer:</p>
<p>I've been looking into using GPMC. The Technical Reference Manual for the AM335x says that GPMC has a 512MB address space. Since the module I have has a 512MB NAND flash on GPMC, configuring another chip select to control my hardware interface within that same address range would generate a fault. But you advertise a maximum of 1GB NAND flash on this module. I'm puzzled about how this is possible. I found basically the same question on a TI wiki page (<a class="external" href="http://e2e.ti.com/support/arm/sitara_arm/f/791/t/282915.aspx">http://e2e.ti.com/support/arm/sitara_arm/f/791/t/282915.aspx</a> ) where a TI employee suggests using a GPIO pin to switch between 2 - 512MB memories. Is this how you manage to get 1GB of Flash on this module? This would allow you to use the same GPMC chip select for both flashes, but that leaves me with the problem of how to configure a different chip select within the same address space. I believe your WiFi adaptor is also in the same GPMC address space. How is that chip select configured?</p>
<p>Answer(s):</p>
<p>1) With NAND devices the GPMC address 'A' type pins are not used for the addressing as it issues the address over the Data 'AD' pins. Because the NAND is not memory mapped the limit (per the TRM table 26-14) is not 512MB but 8GB. This post covers max NAND size vs the GPMC address sizes: <a class="external" href="http://e2e.ti.com/support/arm/sitara_arm/f/791/t/163815.aspx">http://e2e.ti.com/support/arm/sitara_arm/f/791/t/163815.aspx</a></p>
<p>2) With the "GPMC" mode the 512MByte maximum is across all 8 chip selects, a single device/chip select is limited to 512Mbit. (Page 620 TRM)</p>
<p>Followup Question:</p>
<p>We need to understand how you plan on using the GPMC interface for your custom device/driver and do you plan on needing/using the NAND memory as well.</p> MitySOM-335x (ARM Cortex-A8 Based Products) - Software Development: Communicating with an 8-bit p...http://support.criticallink.com/redmine/boards/28/topics/42312014-10-20T16:55:57ZAlexander Blockalex.block@criticallink.com
<p>Posting this on behalf of a customer:</p>
<p>The interface to their networking chip and other peripheral boards on their current motherboard is through memory mapped I/O. The customer would like to recreate this with the MitySOM-335x and is exploring the options available to them both in general with the MitySOM-335x and with respect to any development board limitations for a proof of concept.</p>
<pre>
I've experimented with userspace GPIO and I can toggle pins at 300kHz which might be fast enough, but implementing a bi-directional 8 bit data bus with 8 discrete GPIO pins would be very messy. I looked into the GPMC pins that are available on the Expansion I/O connector. You had said that only pins AD8 - AD15 would be available as GPIO pins, which made me wonder if you are using that memory bus for some flash on the MitySOM module.
</pre>
<p>The module being used currently is a 3354-HX-X38-RC which has 512MB of NAND memory on the GPMC bus. For this reason it was stated that only AD8 through AD15 would be available as GPIO pins. If a memory maped device is used then you can utilize the GPMC control signals and AD0 through AD7 for that device in addition to a new chip select. All of these pins are available from the dev board on J700.</p>
<pre>
Would I be able to use that connector (J700) for external memory mapped I/O? Would I be able to slow down the memory access cycle times to work with my peripherals without messing up what you have on the MitySOM? If I can use it, do you have any example code to access absolute addresses from a userspace program?
I am also looking into using an SPI port to handle the 8-bit data bus in combination with GPIO pins. I'm currently stuck trying to create a /dev/spiB.C (B=bus, C=chip select) device. Do I need to edit a device tree .dts file somewhere?
</pre> MitySOM-5CSX Altera Cyclone V - FPGA Development: RE: Load FPGA Timeout Errorhttp://support.criticallink.com/redmine/boards/47/topics/3551?r=4193#message-41932014-09-17T11:29:24ZAlexander Blockalex.block@criticallink.com
<p>Max,</p>
<p>Thank you for posting that.</p>
<p>You are correct that if VBAT is too low the module will either not boot at all and/or will not allow the FPGA to be programmed. We believe that on earlier development kits the ESD bags may have contacted the battery terminals on the bottom of the board and caused some amount of premature discharging. We now use some Kapton tape to cover these terminals to help prevent such discharge.</p>
<p>In the newest module designs we have added a diode-or circuit to the VBAT input which will allow the module to boot in the event that the RTC battery has failed.</p>
<p>We will post an VBAT/RTC wiki page to cover these concerns and apologize for the amount of time it took to determine the cause in your case.</p>
<p>Thanks,</p>
<p>Alex</p> MitySOM-5CSX Altera Cyclone V - Software Development: Memory Aligned Byte Arrayhttp://support.criticallink.com/redmine/boards/45/topics/41612014-08-26T15:16:20ZAlexander Blockalex.block@criticallink.com
<p>Posted on behalf of a customer:</p>
<p>I have a byte array in my Linux application into which I want my DMA firmware to write. I need the byte array to be memory aligned <br />to a certain offset. From what the compiler is telling me, the most I can align a char[] by is 15 bits (a 32K boundary). Is there a way <br />to make this boundary larger? How large?</p>
<p>ARMs documentation says its compiler is able to do alignments right up to 32 bits. What am I doing wrong?</p>
<p>Thank you.</p> MitySOM-5CSX Altera Cyclone V - Software Development: RE: How to add aditional HPS GPIO'shttp://support.criticallink.com/redmine/boards/45/topics/4148?r=4149#message-41492014-08-15T13:44:47ZAlexander Blockalex.block@criticallink.com
<p>In the case described of wanting to add GPIO's to drive/control an LED (output from the HPS) you do not need to alter the DTS file. The DTS additions were for Switch based GPIO's which are a special case in which their is a Linux driver that handles additional things like switch debouncing. So the process for adding and accessing the additional 4 GPIO's mentioned would be as follows:</p>
<p>1) In your QSys project open the "HPS" peripheral settings from the "System Contents" tab.<br />2) Go to the "Peripheral Pin Multiplexing" Tab and scroll down to the bottom of the window in Qsys and from there select the *GPIO mode for each 53, 48, 29 and 50. Note that by doing this you may change/disable another HPS feature (i.e. GPIO53 could have been defined as CAN1).<br />3) "Finish" making your changes and then export the changes to your top level entity.<br />4) Rebuild your FPGA project<br />5) Rebuild your pre-loader<br />6) Replace your pre-loader on your MitySOM-5CSX system and boot into Linux<br />7) From within Linux you can now work on accessing the new GPIO pins. To do this you need to first determine the pin number in Linux for each GPIO you enabled in QSys. The table below has the Linux GPIO number on the left and the HPS GPIO number on the right.</p>
<p>So in this specific case:<br />GPIO 53 is #222<br />GPIO 50 is #219<br />GPIO 49 is #218<br />GPIO 48 is #217</p>
<table>
<tr>
<td> Virtual gpio base </td>
<td> Linux GPIO Numbers </td>
<td> <---> </td>
<td> Hardware (HPS) gpio </td>
</tr>
<tr>
<td> gpiochip227 </td>
<td> 227 to 255 </td>
<td> <---> </td>
<td> GPIO0 to GPIO28 </td>
</tr>
<tr>
<td> gpiochip198 </td>
<td> 198 to 226 </td>
<td> <---> </td>
<td> GPIO29 to GPIO57 </td>
</tr>
<tr>
<td> gpiochip171 </td>
<td> 171 to 179 </td>
<td> <---> </td>
<td> GPIO58 to GPIO66 </td>
</tr>
</table>
<p>8) Example using GPIO 49 (#217)</p>
<p>8a) First confirm that your Linux Kernel has the GPIO drivers configured. To do this "cd" to the /sys/class/gpio/ directory. Do a file listing in the directory as shown below nad you should see gpiochip listings 227, 198 and 171:</p>
<pre>
root@mitysom-5csx:/sys/class/gpio# ls
export gpiochip171 gpiochip198 gpiochip227 unexport
</pre>
<p>8b) In Linux you first need to export the GPIO:</p>
<pre>
root@mitysom-5csx:/sys/class/gpio# echo "217" > /sys/class/gpio/export
</pre>
<p>Confirm that the GPIO has been exported by doing an 'ls' in the GPIO directory. You should see an entry for "gpio217" added.</p>
<pre>
root@mitysom-5csx:/sys/class/gpio# ls
export gpio217 gpiochip171 gpiochip198 gpiochip227 unexport
</pre>
<p>8c) Now we need to set the direction to be an output (controlling an LED)</p>
<pre>
echo "out" > /sys/class/gpio/gpio217/direction
</pre>
<p>You can confirm the direction by running the 'cat' command and see that it show "out"</p>
<pre>
root@mitysom-5csx:/sys/class/gpio# cat /sys/class/gpio/gpio217/direction
out
</pre>
<p>For an "input" change the "out" to "in" when setting the direction</p>
<p>8d) Now we can set the state of the GPIO High/Low</p>
<p>High<br /><pre>
echo "1" > /sys/class/gpio/gpio217/value
</pre></p>
<p>Low<br /><pre>
echo "0" > /sys/class/gpio/gpio217/value
</pre></p> MitySOM-5CSX Altera Cyclone V - Software Development: How to add aditional HPS GPIO'shttp://support.criticallink.com/redmine/boards/45/topics/41482014-08-14T10:51:56ZAlexander Blockalex.block@criticallink.com
<p>Posting on behalf of a customer:</p>
<p>On the MitySom .dts file, you specify some GPIOS like this:</p>
<pre>
/* GPIO 56 */
button@1 {
label = "Switch 1";
linux,code = <0x101>;
gpios = <&gpio1 8 1>;
debounce-interval = <100>;
};
/* GPIO 55 */
button@2 {
label = "Switch 2";
linux,code = <0x102>;
gpios = <&gpio1 11 1>;
debounce-interval = <100>;
};
/* GPIO 54 */
button@3 {
label = "Switch 3";
linux,code = <0x103>;
gpios = <&gpio1 12 1>;
debounce-interval = <100>;
</pre>
<p>In my new design I want to use GPIO 53, 48, 49, and 50 to drive some LEDs. <br />How do I add these?</p> MitySOM-5CSX Altera Cyclone V - Software Development: RE: PCI-e Device Driver - munmap related errorhttp://support.criticallink.com/redmine/boards/45/topics/4085?r=4147#message-41472014-08-14T10:49:48ZAlexander Blockalex.block@criticallink.com
<p>Reporting that the customer solved their problem:</p>
<p>I've solved the problem. <br />Thread A which was signaling Thread B to terminate was doing a pthread_join after doing so.</p>
<p>I commented out the pthread_join and it worked perfectly fine after.</p> MitySOM-5CSX Altera Cyclone V - Software Development: PCI-e Device Driver - munmap related errorhttp://support.criticallink.com/redmine/boards/45/topics/40852014-07-25T13:52:29ZAlexander Blockalex.block@criticallink.com
<p>Posting on behalf of a customer:</p>
<p>I'm having some sporadic problems with the device driver I made for our pci-e device. <br />It works great in general but it seems like every other run, I get a segfault when trying to <br />close() the device file and when I try to munmap() the pci-e device space from my user program <br />space. The segfault occurs exactly when one of those two functions is called.</p>
<p>I've already made absolutely sure that there are no accesses to the mapped area after <br />munmap. There are also no reads or writes happening when munmap and close are called.</p>
<p>Can you see if anyone has any insight as to what the problem is?</p> MitySOM-5CSX Altera Cyclone V - FPGA Development: RE: How to access FPGA internal memory through ...http://support.criticallink.com/redmine/boards/47/topics/3961?r=4000#message-40002014-07-02T21:27:52ZAlexander Blockalex.block@criticallink.com
<p>Information on how to make an SD card based upon the current Development Kit SD card image (Rev 1B) can be found on this wiki page (<a class="external" href="https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_SD_Card_Image">https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_SD_Card_Image</a>) in the "Development Kit SD Card Image" section.</p>
<p>-Alex</p> MityDSP-L138 (ARM9 Based Platforms) - FPGA Development: RE: DSP to FPGA SPI Setup Questionhttp://support.criticallink.com/redmine/boards/12/topics/3903?r=3942#message-39422014-06-25T10:39:25ZAlexander Blockalex.block@criticallink.com
<p>Update and followup question from the customer:</p>
<p>We have made the SPI work, but transmitting the word to word is slow.(about 11 uSec to send a 24bit word).</p>
<p>This is the code we run in the DSP:</p>
<p>spi = new tcDspFpgaSpi((void *)my_base_addr);<br />spi->ConfigCS(0, 0, 0, 50000000, tcDspFpgaSpi::ee24Bit);<br />while(1)<br /> spi->Transfer(outData, NULL, 1, 0);</p>
<p>We suspect that the EMIFA communication is the bottleneck.</p>
<p><strong>Is this the bandwidth we should expect from EMIFA?</strong></p> MitySOM-5CSX Altera Cyclone V - Software Development: I2C Access with 5CSX Development Boardhttp://support.criticallink.com/redmine/boards/45/topics/38702014-06-13T12:42:28ZAlexander Blockalex.block@criticallink.com
<p>Posting on behalf of a customer and for future reference as well:</p>
<p>1) How do I access the +5V I2C current monitor IC interface on the Critical Link development board, WITHOUT using i2cSet and i2cGet? I do not have these programs installed under linux.</p>
<p>2) Under the /dev folder, there are two "files" named i2c-0 and i2c-1. Can I use these to interact with the power I2C and if so,</p>
<p>3) How do I interact with them via software to get/set parameters on the power I2C? Are there examples?</p>
<p>Thanks,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: How to run bin application via u-...http://support.criticallink.com/redmine/boards/10/topics/3827?r=3841#message-38412014-05-29T16:29:52ZAlexander Blockalex.block@criticallink.com
<p>Ahmed,</p>
<p>I believe Mike was suggesting that you build the application as a "release" version without any debugging and see what the resulting application file size is?</p>
<p>I.E. if it was 5MB in debug maybe it's 2MB in release, thus no need to bother with the binary conversion.</p>
<p>If that is not the case as you saying that when you built your application in a "release" mode it stopped working, again still as the .out (elf) format?</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: How to run bin application via u-...http://support.criticallink.com/redmine/boards/10/topics/3827?r=3837#message-38372014-05-29T13:48:42ZAlexander Blockalex.block@criticallink.com
<p>Posting some previous direct followup e-mails from the customer.</p>
<p>I have followed the steps of the Starterware wiki ([[<a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/StarterWare]]">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/StarterWare]]</a>) and I could run elf (UART_MITY_ARM.out) format successfully.<br />Now, I need to know if I could convert .out to .bin (which size is smaller than the out (ELF) image) and I need to know how to save it into SPI flash, but i didn't find Uboot cmd to run bin format only elf format (.bin - bootelf).</p>
<p>So, how do I run the bin format for an ARM app?</p>
<p>The reason behind why i want to use .bin instead of .out is as follows:</p>
<p>I'll put the <abbr title="ARM">CPU</abbr> application and FPGA image in SPI NOR Flash and the problem is the .out size is very large (5 Mbyte and may increase as the application is under development) unlike the .bin which size is 400 Kbyte.<br />So i want to use .bin instead of .out (ELF).</p>
<p>I have tried loadb and go Uboot commands as follows:</p>
<pre>
Hit any key to stop autoboot: 0
U-Boot > loadb 0xc0700000
## Ready for binary (kermit) download to 0xc0700000 at 115200 bps...
## Total Size = 0x0000b650 = 46672 Bytes
## Start Addr = 0xc0700000
U-Boot > go 0xc0700000
## Starting application at 0xc0700000
</pre>
<p>But as you see it didn't work.</p>
<p>I have already tried to load .out/.bin in the following addresses :<br />0xC3000000 and 0xC30078C8 (which is the entry point in the map file ), but nothing works.</p>
<p>So if you got time could you try the following steps on a Mity kit and let me know the result:<br />1- load "UART_MITY_ARM.out" using either "tftp" or "loadb" U-boot commands.<br />2- use "go" command.</p>
<p>I really appreciate your guidance.</p>
<p>Note:<br />I have done the previous steps on Starterware .out example and it didn't work either.</p>
<p>Attached is the zip file containing the sample projects the customer is trying to run. They were built in CCS 5.3 and he is using an XDS 100 v3 emulator.</p> MitySOM-335x (ARM Cortex-A8 Based Products) - PCB Development: RE: Using RMII1 and JTAGhttp://support.criticallink.com/redmine/boards/29/topics/3812?r=3815#message-38152014-05-16T13:50:37ZAlexander Blockalex.block@criticallink.com
<p>This specific issue is/has been dealt with through e-mail contact directly. However for others who may have similar questions I will provide answers here as well.</p>
<p>You are correct that Revision 1 Silicon modules are still in distribution at this point. For the large majority of customers there is no issue with Rev 1 silicon unless a faster CPU speed is needed (800MHz in Rev 2) or RMII2 access which was made available with Rev 2 AM335x Silicon. Arrangements are being made to allow for an exchange to Rev 2 modules in this instance.</p>
<p>It is not advised to use the I2C1_SDA pin in the RMII1_CRS_DV mode as that pin is connected to the modules EEPROM and there could be the possibility of corruption. This wiki page (<a class="external" href="https://support.criticallink.com/redmine/projects/armc8-platforms/wiki/Ethernet_Phy_Selection">https://support.criticallink.com/redmine/projects/armc8-platforms/wiki/Ethernet_Phy_Selection</a>) discusses the available Ethernet MAC interfaces.</p>
<p>Concerning the Emulator and the M3 core we are not directly familiar with trying to debug that core. We tried to find some guidance from TI about the M3 and the only details really cover using the power management features and ensuring that the firmware for the core is in the proper place when a kernel is built. Here are the pages that contained some of this data but nothing about actually debugging the core:</p>
<p><a class="external" href="http://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/216177.aspx">http://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/216177.aspx</a><br /><a class="external" href="http://processors.wiki.ti.com/index.php/AM335x_Linux_Power_Management_User_Guide">http://processors.wiki.ti.com/index.php/AM335x_Linux_Power_Management_User_Guide</a></p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - FPGA Development: RE: Broken i_ema_a<8>http://support.criticallink.com/redmine/boards/12/topics/3505?r=3768#message-37682014-04-12T14:43:17ZAlexander Blockalex.block@criticallink.com
<p>Lukasz,</p>
<p>I have found the RMA request e-mail you have mentioned and have replied to that e-mail accordingly.</p>
<p>Thank you,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: Error while connecting to ARM9 http://support.criticallink.com/redmine/boards/10/topics/3718?r=3765#message-37652014-04-11T16:27:16ZAlexander Blockalex.block@criticallink.com
<p>The issue of debugging the ARM is that you cannot use CCS JTAG / the emulator when the Linux OS's memory manager is running. When you stop the module from booting, hold it in UBoot, that memory manager has not been initialized yet as the Linux kernel is not running.</p>
<p>If you want to debug an application while Linux is running you need to use GDB server which is outlined in our Wiki here (<a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Debugging_ARM_Apps_with_Eclipse">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Debugging_ARM_Apps_with_Eclipse</a>).</p>
<p>Thanks for the question.</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: Not able to update opkg on MityDS...http://support.criticallink.com/redmine/boards/10/topics/3755?r=3764#message-37642014-04-11T15:52:32ZAlexander Blockalex.block@criticallink.com
<p>Sorry for the delay.</p>
<p>We are confirming the status of the Angstrom OPKG feeds and are working on providing guidance on how to resolve the issue.</p>
<p>Thank you for providing the screenshot as that will be helpful.</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: MityDSP-L138 CCS 5.5 XDS510http://support.criticallink.com/redmine/boards/10/topics/3754?r=3763#message-37632014-04-11T15:47:46ZAlexander Blockalex.block@criticallink.com
<p>Update after phone call with customer:</p>
<p>1) Created a new project that was able to run a "Hello World" sample application on the ARM processor through the XDS510 emulator. Initially the debug download was failing however that was because the unit was booted into Linux and the ARM was not in reset, stopped the module in UBoot and was able to connect and execute the application.</p>
<p>2) After we confirmed that CCS had the proper drivers and the emulator worked we compared the settings in the project that the customer was provided. We determined that the debug adapter settings needed to be set through the project "debug" properties dialog in order to allow the XDS510 to be used properly by CCS; editing the XML did not work.</p>
<p>The original issue appears to be resolved and was the cause appears to be the configuration of the debug emulator from the third-party that provided the sample application.</p> MitySOM-5CSX Altera Cyclone V - Software Development: Yocto Plug-In Python.exe Errorhttp://support.criticallink.com/redmine/boards/45/topics/36012014-02-03T15:55:41ZAlexander Blockalex.block@criticallink.com
<p>Posting on behalf of a customer:</p>
<pre>
I started diving in with the SOC embedded design suite and had some trouble running the yocto plug-in. Namely, whenever
I try to build, I get a python.exe error stating it should not find the bitbake file or directory which is impossible as the directory it
calls out is precisely the one that has the bitbake file.
How do I fix this?
</pre> MitySOM-335x (ARM Cortex-A8 Based Products) - Software Development: MityARM Kernel Versions, TI S...http://support.criticallink.com/redmine/boards/28/topics/35982014-01-31T09:44:53ZAlexander Blockalex.block@criticallink.com
<p>Posting this on behalf of a customer:</p>
<pre>
1. The CL and TI website suggest Ubuntu 10.04 LTS, but the LINUX kernel version is 2.6.37. How is possible to build 3.2 kernel for SoM on this Ubuntu version?
2. The CL website suggests to download TI SDK 05.0.2.03 version, but I can get only 06.00.00 SDK from TI website how should I proceed?
3. I am little bit confused about how to use PSP and the SDK. Any comments or suggestions.
</pre>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: "Regarding handling UART on Mityd...http://support.criticallink.com/redmine/boards/10/topics/3548?r=3596#message-35962014-01-30T14:22:38ZAlexander Blockalex.block@criticallink.com
<p>Naveen,</p>
<p>The first UART is used for the debug/console port, UART1.</p>
<p>You would like to use the second UART in your DSP/ARM code to trigger some processing to occur correct? On the VDK this would be the J504 connector. I have verified that with the standard VDK Kernel in Linux I could use /ttyS2 (the second UART) so it is enabled in the kernel. This was using a RS232 adapter board hooked to a PC (microcom -s 9600 /dev/ttyS2).</p>
<p>Please confirm if you want the DSP to use the UART or the ARM processor. With that we should be able to dig up an example that may assist you.</p>
<p>Please note that the VDK does not provide an RS232 adapter, what signal levels/device are you planning to interface with?</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: "Reagrding spi NOR flash memory u...http://support.criticallink.com/redmine/boards/10/topics/3572?r=3595#message-35952014-01-30T13:17:40ZAlexander Blockalex.block@criticallink.com
<p>Naveen,</p>
<p>I'm assuming that the question here is how would you get the updated Kernel from your host PC onto the MityDSP-L138 module to update the kernel in the NOR memory?</p>
<p>1) You are going to be executing the commands over the debug serial port on your carrier board, in the case of the Industrial IO board that will be J502 with the 10-pin to DB9 adapter.</p>
<p>2) Follow the steps in the Linux Kernel Wiki under (Installing the Kernel on SPI - FLASH). below are 3 different options of getting the kernel onto your module to program it permanently</p>
<p>2a) You can use a TFTP server running on your Linux PC/Virtual Machine with your newly built kernel image and follow the instructions of #2 supplementing your specific server information. I have also had success in using TFTPD 32/64 (<a class="external" href="http://tftpd32.jounin.net/">http://tftpd32.jounin.net/</a>) on my windows PC with relative ease (this is assuming you have the uImage kernel file off your build pc).</p>
<p>2b) You could create an SD card in either the EXT2 (as provided with the VDK) or FAT32 filesystem and place your new kernel image on it and access it in Uboot in one of the following ways:</p>
<pre>
(for EXT2 formated) u-Boot> ext2load mmc 0:1 c0700000 /boot/uImage
(for FAT formatted) u-Boot> fatload mmc 0:1 c0700000 /boot/uImage
Note that for either you would alter the /boot/uImage location based on your specific SD card placement
</pre>
<p>2c) You can use an NFS server for the kernel which is outlined in the Linux Root File System Wiki (<a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Linux_Root_File_System">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Linux_Root_File_System</a>) under "Booting from an NFS server". Note that the Linux Virtual Machine that ships with our L138 Dev kits should have the NFS server running already and you can find the folder under \home\mitydsp\nfs\</p>
<p>3) Don't forget that after you have loaded your kernel from whatever storage device to write it to the NOR</p>
<pre>
u-Boot> sf probe 0
u-Boot> sf erase 0x100000 0x280000
u-Boot> sf write 0xC0700000 0x100000 ${filesize}
</pre> MitySOM-335x (ARM Cortex-A8 Based Products) - Software Development: 3.1 vs 3.2 Kernel MityARM-33...http://support.criticallink.com/redmine/boards/28/topics/35322014-01-10T19:56:23ZAlexander Blockalex.block@criticallink.com
<p>This is being posted on behalf of a customer.</p>
<pre>
The HDMI output of MityARM-335x development kit with latest image (kernel 3.2) doesn’t work, but old image works fine (kernel 3.1). If I break boot process and manually initialize the HDMI chip (i2c mw 38 8 3d ; i2c mw 38 33 0) the output works fine. The uenv.txt files for old and newest images almost the same. Could you tell me how to fix it.
</pre>
<p>Thank you.</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: "JTAG Interface on MitydspL138F kit"http://support.criticallink.com/redmine/boards/10/topics/3519?r=3531#message-35312014-01-10T10:15:33ZAlexander Blockalex.block@criticallink.com
<p>Naveen,</p>
<p>The Critical Link debug adapter is included with the Vision Development Kit.</p>
<p>The following datasheet describes the included debug adapter: <a class="external" href="http://www.mitydsp.com/images/upload/File/80-000286_Debug_Adapter.pdf">http://www.mitydsp.com/images/upload/File/80-000286_Debug_Adapter.pdf</a></p>
<p>The rest of the contents for the Vision Development Kit are outlined in the Quickstart guide which I have attached.</p>
<p>Please let us know if we can assist with anything else.</p>
<p>Alex</p> MitySOM-335x (ARM Cortex-A8 Based Products) - Software Development: RE: Ethernet RMII2 working in...http://support.criticallink.com/redmine/boards/28/topics/3280?r=3292#message-32922013-10-25T10:23:30ZAlexander Blockalex.block@criticallink.com
<p>Could you post an updated patch to show what was changed to resolve the issue?</p>
<p>Thank you.</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: U-Boot Source Codehttp://support.criticallink.com/redmine/boards/10/topics/2370?r=2373#message-23732013-02-12T17:00:02ZAlexander Blockalex.block@criticallink.com
<p>Terrence,</p>
<p>The U-Boot source code is maintained in a GIT repository and not wholly contained in the MDK however a seed version of the GIT repository is included but you should update it to the latest.</p>
<p>Considerable information is on the Das U-Boot Port Wiki page here: [[<a class="external" href="http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Das_U-Boot_Port">http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Das_U-Boot_Port</a>]]</p>
<p>Please let us know after looking through the Wiki if you have any further questions.</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - FPGA Development: RE: Pinout on L138-FG-225-RChttp://support.criticallink.com/redmine/boards/12/topics/2118?r=2199#message-21992012-12-20T21:49:36ZAlexander Blockalex.block@criticallink.com
<p>Michele,</p>
<p>In response to your GPIO bank question:</p>
<p>Yes you can use a single core in the FPGA and have it utilize pins from both banks (I have done it in a couple of my designs and have had no issues).</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: RE: SATA board connectorhttp://support.criticallink.com/redmine/boards/11/topics/1984?r=2198#message-21982012-12-20T21:44:05ZAlexander Blockalex.block@criticallink.com
<p>Scott,</p>
<p>Just wondering if you found a drop in replacement. We actually just tried doing this on an in-house test fixture here and I selected a Molex 19103 which is pin-compatible however the footprint isn't quite right and the pins had to be bent a little but the connector ended up flush on fully soldered on the board.</p>
<p><a class="external" href="http://www.digikey.com/product-detail/en/0678008005/WM19103-ND/1499151">http://www.digikey.com/product-detail/en/0678008005/WM19103-ND/1499151</a></p>
<p>If you found a replacement can you post what it was exactly?</p>
<p>Thanks,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: tftp access violationhttp://support.criticallink.com/redmine/boards/10/topics/2115?r=2197#message-21972012-12-20T21:39:28ZAlexander Blockalex.block@criticallink.com
<p>Wade,</p>
<p>I'm going to take a stab in the dark here on a suggestion to give you something to try. If you think you may have overwritten some important memory areas than it may be advised to reflash the board with the UBoot image that is provided in the MDK builds following the "Reprogramming a dead board" guide (<a class="external" href="http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Reprogramming_a_Dead_Board">http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Reprogramming_a_Dead_Board</a>).</p>
<p>Hopefully that will net some good result.</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: The Jtag Interfacehttp://support.criticallink.com/redmine/boards/10/topics/1505?r=2196#message-21962012-12-20T21:26:08ZAlexander Blockalex.block@criticallink.com
<p>If you can wait approximately a week or two Digikey should have them in stock for ordering (<a class="external" href="http://www.digikey.com/product-search/en?x=0&y=0&KeyWords=80-000286">http://www.digikey.com/product-search/en?x=0&y=0&KeyWords=80-000286</a>).</p>
<p>Otherwise please send an e-mail to <a class="email" href="mailto:info@criticallink.com">info@criticallink.com</a> citing this post and your contact information and we can get one out to you shortly.</p>
<p>Thank you,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: Using RAM as temporary storagehttp://support.criticallink.com/redmine/boards/10/topics/21172012-11-30T22:18:24ZAlexander Blockalex.block@criticallink.com
<p>Posting on behalf of a customer:</p>
<p>Customer wants to store data to the SD card but believes they will be bursting more than the write speeds that we have tested for the SD card interface (<a class="external" href="http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/MMCSD_Card_Throughput">http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/MMCSD_Card_Throughput</a>). They had the following question in regards to a possible solution:</p>
<p>Do I have access to the on board 128MB DDR memory? Can I use it for my temporary storage needs? If so, how much storage space will I have? <br />This is important since if this memory is not accessible I must add an additional memory chip on my base board.</p>
<p>Thank you,</p>
<p>Alex</p> MitySOM-335x (ARM Cortex-A8 Based Products) - PCB Development: RE: Is VIO_3P3 NC? http://support.criticallink.com/redmine/boards/29/topics/1982?r=2058#message-20582012-11-06T20:41:10ZAlexander Blockalex.block@criticallink.com
<p>I will take a look at the schematics by Friday and update the link as necessary. I believe you are correct...the Rev B and Rev C point to the same schematic.</p>
<p>Sorry about the delay on this issue,</p>
<p>Alex</p> MitySOM-335x (ARM Cortex-A8 Based Products) - PCB Development: RE: Caution on MityARM SO-DIMM PCB...http://support.criticallink.com/redmine/boards/29/topics/1902?r=1908#message-19082012-10-01T12:22:59ZAlexander Blockalex.block@criticallink.com
<p>Mark,</p>
<p>Thank you for pointing out that lack of information. It has now been addressed and the design guide has been updated, October 1, 2012 1.2 version.</p>
<p>Thanks again,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: RE: MMCSDhttp://support.criticallink.com/redmine/boards/11/topics/1743?r=1901#message-19012012-09-27T16:04:41ZAlexander Blockalex.block@criticallink.com
<p>Conor,</p>
<p>We have addressed the MMC issues in the datasheet which can be found here by selecting the latest board version: <a class="external" href="http://support.criticallink.com/redmine/projects/indio/wiki/Industrial_IO_Revision_Information">http://support.criticallink.com/redmine/projects/indio/wiki/Industrial_IO_Revision_Information</a></p>
<p>During the review of the datasheet we also found that some of the FPGA IO pins (beyond the one on J700 you mentioned) that were mislabeled compared to the development kit baseboard schematic.</p>
<p>Thank you,</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: RE: MityDSP-L138F Mounting Holes (Posted o...http://support.criticallink.com/redmine/boards/11/topics/1558?r=1663#message-16632012-07-31T15:49:45ZAlexander Blockalex.block@criticallink.com
<p>Now I've attached the updated PDF.</p>
<p>Alex</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: RE: MityDSP-L138F Mounting Holes (Posted o...http://support.criticallink.com/redmine/boards/11/topics/1558?r=1662#message-16622012-07-31T15:48:56ZAlexander Blockalex.block@criticallink.com
<p>Emmett,</p>
<p>Sorry about the late reply on this issue. Hopefully you have resolved it satisfactorily but if not I believe I have the dimension you requested:</p>
<p>From the Center Line of Pin 1 to the Center Line of the SODIMM connector is 161mil.</p>
<p>Thank you for pointing out that there was a discrepancy between the footprint and the datasheet. The issue found was that in reality the footprint should have had the outside edge of the MityDSP-L138 module moved in towards the connector 20mil due to insertion into the connector. Originally we had that outline of the module start at the center-line of the connector but in reality that was incorrect. So the outline was moved and the holes stayed in the same place. Everything now makes sense to me and hopefully the attached PDF corrects the issues you found.</p>
<p>If this is still wrong please let me know.</p>
<p>Thanks,<br />Alex</p> MitySOM-335x (ARM Cortex-A8 Based Products) - Software Development: RE: Connecting JTAG to Mityar...http://support.criticallink.com/redmine/boards/28/topics/1422?r=1475#message-14752012-05-30T17:21:35ZAlexander Blockalex.block@criticallink.com
<p>Raja,</p>
<p>Typically we load the kernel over either tftp/nfs and write it onto the MityARM-3359 flash memory or boot from nfs (<a class="external" href="http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Linux_Kernel">http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Linux_Kernel</a>). Previously we have loaded the kernel, booted the module and then ran our application on the module with GDB server and connected via GDB to CCS to do debugging (<a class="external" href="http://processors.wiki.ti.com/index.php/Linux_Debug_in_CCSv5">http://processors.wiki.ti.com/index.php/Linux_Debug_in_CCSv5</a>).</p>
<p>Can you please try and explain exactly it is that you're end goal is with this debugging and some further details on how you are trying to do it?</p>
<p>Also please provide a Link to the "Linux Debug in CCSv5" web page you are referencing, that may help me understand what you're trying to accomplish as well.</p>
<p>Thank you and hopefully we'll get this sorted out,</p>
<p>Alex</p> MitySOM-335x (ARM Cortex-A8 Based Products) - Software Development: RE: Connecting JTAG to Mityar...http://support.criticallink.com/redmine/boards/28/topics/1422?r=1439#message-14392012-05-17T21:54:13ZAlexander Blockalex.block@criticallink.com
<p>Raja,</p>
<p>Sorry about the delay but I did want to update the fact that I was able to have the debugger connect to my MityARM-3359 SoM through the 335x Development Kit from CCS5 using the XDS100v2 emulator.</p>
<p>Offhand I'm not sure which XIP setting you want to be using but I used our "default" setting of 000100000000 (J106). At the UBoot prompt (did not allow it continue booting) I was then able to get CCS to connect over the emulator.</p>
<p>Attached is a new ccxml file that is using the XDS100V2.</p>
<p>Please let me know how its going for you and if you've been successful or had any issues.</p>
<p>Alex</p> MitySOM-335x (ARM Cortex-A8 Based Products) - Software Development: RE: Connecting JTAG to Mityar...http://support.criticallink.com/redmine/boards/28/topics/1422?r=1430#message-14302012-05-16T14:11:29ZAlexander Blockalex.block@criticallink.com
<p>Hello Raja,</p>
<p>Attached are both a gel file and a ccxml file that hopefully will get you going. The gel file has been used previously and should work for you with the MityARM-3359 SoM.</p>
<p>The ccxml file is setup for use with the XDS510 USB emulator. You may want to try and use this file and change the Emulator specific settings to the one you are using. As well one must have setting in this ccxml file is this line:</p>
<p><property Type="filepathfield" Value="..\..\..\..\projects\internal\mityarm335x\sw\gel\AM335x.gel" id="GEL File"/></p>
<p>In the GUI that value is set from the Advanced tab for the debugger configuration.</p>
<p>I am planning on trying to locate the same emulator (XDS100V2) that you are using and giving this process a try myself.</p>
<p>Thanks,</p>
<p>Alex</p> MityDSP (TI TMS320C6xxx Based Products) - PCB Development: RE: MityDSP-Pro FPGA questions ... http://support.criticallink.com/redmine/boards/9/topics/1073?r=1302#message-13022012-04-03T15:22:29ZAlexander Blockalex.block@criticallink.com
<p>Minor changes</p>
<p>Update to Step 1:<br />Depending on the version of MityGUI (or how it is installed) you should simply right-click on your MityGUI shortcut and view "properties" from there you want to find the location of the exe file it is executing. Broswe on your PC to that location and you will find the .ini file you need to modify.</p>
<p>Update to Step 3:<br />Instead of Admin=1 should should enter Authorized=1 into the .ini file</p> MityDSP (TI TMS320C6xxx Based Products) - PCB Development: RE: MityDSP-Pro FPGA questions ... http://support.criticallink.com/redmine/boards/9/topics/1073?r=1301#message-13012012-04-02T16:02:05ZAlexander Blockalex.block@criticallink.com
<p>Hello,</p>
<p>I wanted to update this issue with a interim Boot SW and FPGA that addresses the issue stated. Attached are two files that you will need to program your MityDSP-Pro module with. These are bootloader files NOT application files. As such you will need to follow the following steps to program the Bootloader using MityGUI.</p>
<p>*<strong><b></strong>*</b>**<strong>**</strong>***<br />NOTE: Doing this can "brick" a MityDSP module therefore it is highly recommended that these files ONLY be updated with ones provided by Critical Link.
*<strong><b></strong>*</b>**<strong>**</strong>***<br />1) With MityGUI closed go into the MItyGUI install directory (currently C:\MityGUI\4.0\software\tools\<br />2) Open/edit the "MityDSPGUI.ini" file<br />3) Add the following line at the end of the file "Admin=1" <br />4) Save and close the "MityDSPGUI.ini" file<br />5) Now start the MityGUI application<br />6) You should now have the following list of options to program your module with</p>
<blockquote>
<p>A) Application (Previously available)<br />B) Application FPGA (Previously available)<br />C) Bootloader (New - this is for the provided hex file)<br />D) Bootloader FPGA (New - this is for the provided mcs file)<br />E) Bootstrapper (New - will not use this)<br />F) Configuration (New - will not use this)<br />G) Full Image (New - will not use this)</p>
</blockquote>
<p>7) You will need specify the Bootloader file and direct the GUI to use the attached "BootloaderPro_EthLED.hex" file<br />8) Download the file to the module<br />9) You will need specify the Bootloader FPGA file and direct the GUI to use the attached "mitydsp_pro_EthLED.mcs" file<br />10) Download the file to the module<br />11) Reboot/power cycle the module</p>
<p>At this time if you have the ethernet connected the orange speed LED (On = 100 MBit and Off = 10 MBit) and green Link/Activity (ON for Link and blinking for activity) should be working.</p>
<p>This version of the Bootloader will be included in the 2.12 version of the MDK.</p> MitySOM-335x (ARM Cortex-A8 Based Products) - PCB Development: RE: Power supply requirementshttp://support.criticallink.com/redmine/boards/29/topics/1268?r=1296#message-12962012-03-30T18:04:39ZAlexander Blockalex.block@criticallink.com
<p>Tom,</p>
<p>Here are a couple power usage numbers I was able to gather with a 3.3V input voltage to a MityARM-3359 module:</p>
<p>Measured a low usage, Linux only no demo or other applications, power usage of 760mW.<br />Measured a high usage, Demo Application displaying 3D demo on HDMI display, power usage of 1580mW</p>
<p>Please reference <a class="external" href="http://support.criticallink.com/redmine/projects/armc8-platforms/wiki/MityARM-335x_Power_Supply_Requirements">http://support.criticallink.com/redmine/projects/armc8-platforms/wiki/MityARM-335x_Power_Supply_Requirements</a> for more details and future power usage updates for the 335x line of SoM's</p>
<p>Alex Block</p>