Critical Link Support: Thomas Catalinohttp://support.criticallink.com/redmine/http://support.criticallink.com/redmine/redmine/favicon.ico?16338348402023-10-26T02:24:00ZCritical Link Support
Redmine MitySOM-5CSX Altera Cyclone V - FPGA Development: Link missing on System Design Overview wiki page http://support.criticallink.com/redmine/boards/47/topics/65282023-10-26T02:24:00ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>on this URL:</p>
<p><a class="external" href="https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/System_Design_Overview">https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/System_Design_Overview</a></p>
<p>it says:</p>
<p>"Create a new project or start from the Critical Link MityARM-5CSX reference project <link to file here>"</p>
<p>Note, it says "<link to file here>", but there is no link. Can you please let me know what that project link is?</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: linux-v4.19 kernelhttp://support.criticallink.com/redmine/boards/10/topics/65032023-10-03T15:40:06ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>I currently have a project with to revisit a system based on the MityDSP-L138 platform, mainly to update the system's self-test and calibration procedures.</p>
<p>I've started blowing the dust off our build environment, but are coming up against quite a few issues due to the age of it. For example, the version of buildroot we are using points to stale versions of most of the libraries it needs.</p>
<p>I've seen that there are still commits going into your linux-davinci repository and even an updated linux-v4.19 kernel. I've given this a very quick try with a modern buildroot, but not getting very far (no kernel output).</p>
<p>Could I ask what environment (e.g. gcc, u-boot, kernel and buildroot) you'd currently recommend I start from?</p> MitySOM-AM62 & MitySOM-AM62A - Software Development: Error building kernel and rootfs on host hav...http://support.criticallink.com/redmine/boards/62/topics/64702023-09-07T14:18:49ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of customer)</p>
<p>We were trying to develop environment for Kernel and Rootfs development using following link on host having Ubuntu 23.04 with docker, but ended up with some error</p>
<p><a class="external" href="https://support.criticallink.com/redmine/projects/mitysom_am62x/wiki/Yoctomitysomam62">https://support.criticallink.com/redmine/projects/mitysom_am62x/wiki/Yoctomitysomam62</a></p>
<p>ERROR: linux-cl-ti-5.10.158+gitAUTOINC+c66d84b258-r0 do_kernel_version_sanity_check: Package Version (5.10.158+gitAUTOINC+c66d84b258) does not match of kernel being built (5.10.168). Please update the PV variable to match the kernel source or set KERNEL_VERSION_SANITY_SKIP="1" in your recipe.<br />ERROR: linux-cl-ti-5.10.158+gitAUTOINC+c66d84b258-r0 do_kernel_version_sanity_check: Execution of '/work/build/arago-tmp-external-arm-glibc/work/mitysom_am62x-linux/linux-cl-ti/5.10.158+gitAUTOINC+c66d84b258-r0/temp/run.do_kernel_version_sanity_check.1301' failed with exit code 1<br />ERROR: Logfile of failure stored in: /work/build/arago-tmp-external-arm-glibc/work/mitysom_am62x-linux/linux-cl-ti/5.10.158+gitAUTOINC+c66d84b258-r0/temp/log.do_kernel_version_sanity_check.1301<br />ERROR: Task (/work/sources/meta-mitysom/recipes-kernel/linux/linux-cl-ti_5.10.bb:do_kernel_version_sanity_check) failed with exit code '1'</p> MitySOM-AM57X - PCB Development: RE: Is the USB SS connection correct?http://support.criticallink.com/redmine/boards/60/topics/6411?r=6421#message-64212023-07-17T14:15:05ZThomas Catalinotom.catalino@criticallink.com
<p>Thanks, Jon!</p>
<p>Tom</p> MitySOM-AM57X - PCB Development: RE: about MECHANICAL INTERFACE in AM57x DataSheethttp://support.criticallink.com/redmine/boards/60/topics/6407?r=6408#message-64082023-07-10T13:57:37ZThomas Catalinotom.catalino@criticallink.com
<p>Thank you for pointing this out. We will repair the figure references in the next revision of the datasheet. In both cases the erroneous reference is to the figures directly below the text where the error appears.</p> MitySOM-AM57X - PCB Development: Unconnected pins, board dimensions and hole positionshttp://support.criticallink.com/redmine/boards/60/topics/63912023-06-23T18:51:11ZThomas Catalinotom.catalino@criticallink.com
<p>Posting on behalf of customer:</p>
<p>1.The J1 and J3 connectors of MitySOM-AM57 are described as “MFIO” for “Type”.<br />"If this pin is not used, can it be left unconnected?" <br />(Table 6, Table 7 in MitySOM-AM57_datasheet.pdf)</p>
<p>2.Is it okay to leave it unconnected even if it is not used with “ModuleFixed-FunctionPin (FF)”?<br />(Table 6, Table 7 in MitySOM-AM57_datasheet.pdf)</p>
<p>3. I read the board dimensions and hole positions of ”MitySOM-AM57” from the ODB data of ”MitySOM-AM57F-DevKit”, but there are differences from the data sheet of ”MitySOM-AM57”.<br />"Which is correct, the ODB data or the datasheet?" <br />See attached file: Dimensions read from ODB data are in red<br />(I think there is also an inch-mm conversion error, but the maximum is 0.3 mm.)</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: Modification of flashing program - sf...http://support.criticallink.com/redmine/boards/10/topics/63842023-06-06T13:01:18ZThomas Catalinotom.catalino@criticallink.com
<p>(Posted by Tom on behalf of customer -- I am working to resolve the locked account issue)</p>
<p>in my work I use your L138-FX-325-RC chips, to which I added self-built base boards with peripherals.<br />Recently, I built a prototype of a measuring device that uses both processors at the same time: DSP for numerical calculations, ARM9 for peripherals and communication.<br />The whole system is managed by ARM9 (working without OS). I am using a 456MHz clock in my project. Using CCS of TI I obtained two files: dsp.out and arm9.out which I combined into one file Analyzer_1.bin using AISgen_d800k008.exe with accordingly changed the configuration file MITY_UART1_OMAPL138_LCDK_AISGen_Config.cfg (attached). I boot the device by uploading the Analyzer_1.bin program to RAM using the UartHost.exe program and UATR1 of the board, equipped with the FT232R chip (converting USB to serial UART interface). Everything works OK - the program starts on both processors right after booting (ARM9 starts DSP).<br />The next step was an attempt to upload the program to Flash NAND memory. For this purpose, using AISgen_d800k008.exe with the configuration file MITY_NAND_OMAPL138_LCDK_AISGen_Config.cfg (attached),<br />I created the file Analyzer_1_NAND.bin which I wanted to upload to the NAND memory. For this purpose, I used the sfh_OMAP-L138.exe program downloaded from the TI website.<br />First, to clear the NAND memory, I used the following command:</p>
<p>sfh_OMAP-L138.exe -flashType NAND -targetType OMAPL138 -erase -p COM4 -v</p>
<p>(also in simplified versions, e.g.: sfh_OMAP-L138.exe -flashType NAND -erase -p COM4)</p>
<p>After resetting the device, the program first successfully connects to the device and then stops after issuing the command:</p>
<p>Waiting for SFI on the OMAP-L138...</p>
<p>There are no progress bars showing memory erasing - the program is waiting!!! Why?</p>
<p>I get a similar effect when trying to upload the Analyzer_1_NAND.bin program to the NAND memory using the command:</p>
<p>sfh_OMAP-L138.exe -flash_noubl -flashType NAND -p COM4 Analyzer_1_NAND.bin</p>
<p>I use the -flash_noubl parameter because I don't need to upload the UBL file because my arm9.out program runs the dsp.out program.</p>
<p>On page</p>
<p><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Reprogramming_a_Dead_Board">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Reprogramming_a_Dead_Board</a></p>
<p>I found information that I should use the rebuilt sfh_OMAP-L138.exe program. For this purpose, I should download the package from the website</p>
<pre><code>"Dead Board Programming Files"</code></pre>
<p>But I can't do it because I can't log in because the old account has expired and I don't see the option to create a new account anywhere on the website?!?!</p>
<p>In turn on the page</p>
<p><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/User_Boot_Loader">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/User_Boot_Loader</a></p>
<p>I found information</p>
<p>"The user boot loader requires a couple of small modifications to support the Critical Link SoM, including:</p>
<pre><code>Setting the EMIFA clock rate to 100 MHz instead of 25 MHz for FPGA operation.<br /> Providing a 312 MHz CPU clock rate (optional) for Profibus support on the Industrial I/O Board.</code></pre>
<p>A tarball of the source code including the modifications made by Critical Link is included in the releases, below."</p>
<p>(due to not being logged in, I can't download the UBLandFLashUtils_2010_10_26.tgz software package either).</p>
<p>In my project, the speed of the DSP processor (TMS320C6748) is important, hence the clock frequency is 456 MHz and at the same time I do not use Profibus because I do not use the Industrial I/O Board!!<br />The L138-FX-325-RC system does not have an FPGA, so I do not have to change the DSP clock frequency.<br />On the other hand, in my system, the EMIFA port works at 38 MHz. For this frequency, I selected the time constants of the ADC converter that reads the parallel port.</p>
<p>Will I have to change it all??!!<br />Currently, when I boot the device via UART1, uploading the Analyzer_1.bin program to RAM with<br />UartHost.exe program, everything works OK!!!</p>
<p>Please help me, preferably by providing me with a properly reprogrammed sfh_OMAP-L138.exe program, which will allow me to upload the program to the Flash NAND memory in the current version. This version of the program best suits my needs. The second option is to allow me to re-create my account at <a class="external" href="https://support.criticallink.com">https://support.criticallink.com</a><br />I prefer the first variant!</p> MitySOM-5CSX Altera Cyclone V - Software Development: RE: HPS RGMII EMAC connection to external M...http://support.criticallink.com/redmine/boards/45/topics/6268?r=6275#message-62752023-03-08T18:58:06ZThomas Catalinotom.catalino@criticallink.com
<p>Thank you for the update, it was great to meet you today!</p>
<p>Tom</p> MitySOM-5CSX Altera Cyclone V - PCB Development: RE: Switching MitySOM modules in DevKithttp://support.criticallink.com/redmine/boards/46/topics/6240?r=6241#message-62412022-11-03T21:41:21ZThomas Catalinotom.catalino@criticallink.com
<p>Yes, the development kit is compatible with all modules in the 5CSX/5CSE family</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: MityDSP-L138 Starterware Example ...http://support.criticallink.com/redmine/boards/10/topics/1500?r=6053#message-60532021-01-11T19:45:57ZThomas Catalinotom.catalino@criticallink.com
<p>Hello -</p>
<p>You may wish to post this on one of the TI forums.</p>
<p>We are unable to support TI development kits.</p>
<p>If you are using one of our OMAPL138 based SOM modules in a product we may be able to help.</p>
<p>Thank you</p> MitySOM-335x (ARM Cortex-A8 Based Products) - PCB Development: RE: 1GHz AM335xhttp://support.criticallink.com/redmine/boards/29/topics/2631?r=2635#message-26352013-04-24T00:07:20ZThomas Catalinotom.catalino@criticallink.com
<p>Hi Mark -</p>
<p>The revision "A" silicon from TI refers to silicon revision 2.0. The current revisions use the revision 1.0 silicon from TI. Revision 2.0 silicon was not made available outside of TI. Revision 2.1 silicon is just now becoming available, I believe with a lead time, so we do not have product based on it.</p>
<p>We will be supporting 1GHz. You may have noticed, as Mike pointed out, that TI is not going to produce the new speed grade for all variants of the AM335x, for example, it may not be produced for the AM3359, but will be available on the AM3354 and AM3352, for example.</p>
<p>Let us know how we can help you further, for example, how soon might you require 1GHz?</p>
<p>Thanks,<br />tom</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: SPI NOR Flash memory maphttp://support.criticallink.com/redmine/boards/10/topics/25012013-03-12T08:13:11ZThomas Catalinotom.catalino@criticallink.com
<p>(posted for a customer)</p>
<p>We are looking at using the SPI flash and/or NOR flash for storing our software on the L138 SOM. We are currently using uBoot and the exisiting boot code on the board so we do not want to overwrite these.</p>
<p>Could you provide a map of your use of NOR and NAND flash as initially occupied on a delivered board?</p>
<p>Also, could you provide the RAM address space used by uBoot? (Approximately).</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: SYSBIOS & Starterwarehttp://support.criticallink.com/redmine/boards/10/topics/2179?r=2209#message-22092012-12-26T15:55:39ZThomas Catalinotom.catalino@criticallink.com
<p>Hi Jean-Baptiste -</p>
<p>It would be my understanding that if you are going to use SYS/BIOS that you should start with a sys/bios project. Likely sys/bios needs to be initialized, etc. So, simply starting with starterware and adding a sys/bios task is probably not a valid use case.</p>
<p>Having said this, your best bet is to seek assistance from the TI wiki's and e2e forums as we do not (currently) provide SYS/BIOS example or sample for our L138 platform, though there should be no problems using SYS/BIOS on our platform.</p>
<p>Please let us know if we can help you with any further questions. <br />Thanks,<br />Tom</p> MityDSP-L138 (ARM9 Based Platforms) - FPGA Development: RE: Pinout on L138-FG-225-RChttp://support.criticallink.com/redmine/boards/12/topics/2118?r=2119#message-21192012-12-02T14:24:18ZThomas Catalinotom.catalino@criticallink.com
<p>Michele -</p>
<p>Can I ask for a reminder of what that issue is or a pointer to a forum post? I'm unable to locate it at the moment.</p>
<p>Thanks,<br />Tom</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: FPGA Pinouts ... documentation error??http://support.criticallink.com/redmine/boards/11/topics/19732012-10-19T18:05:20ZThomas Catalinotom.catalino@criticallink.com
<p>(posted for a customer)</p>
<p>I have purchased one of your MityDsp Development kits to use as a reference platform for a base board design. Things are moving along really nice, at least until I started trying to reconcile Xilinx documentation for the XC6SLX45 FGGA and the carrier board design guide for the MityDSP-L138F...</p>
<p>When I try to compare the listing of the pins on the interface connector with the xilinx pinout for the part (in the Spartan-6 FPGA packaging and Pinouts document) , I get stumped.</p>
<p>For example: pin 191 lists (in the carrier board design guide for MityDsp-L138F ) as B0_1P.C7 . But when I look up IO_L1P on the xilinx pinout for the CSG324 package, I find that it is connected to pin D4 (and pin C7 is connected to IO_L10P_0). No matter how I try, I can't make that add up...</p>
<p>I am sure I am missing something totally vital here, but cannot figure out what that is (and I am pretty sure that my VHDL is not going to be working if I can't connect stuff to the right pins on the FPGA :).</p>
<p>Can you please let me know what I am missing.</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: kernel buildhttp://support.criticallink.com/redmine/boards/10/topics/1813?r=1814#message-18142012-09-06T17:59:02ZThomas Catalinotom.catalino@criticallink.com
<p>Scott may have found the issue ... he is going to verify and re-post ...</p> MitySOM-335x (ARM Cortex-A8 Based Products) - Software Development: Booting StarterWare on MityAR...http://support.criticallink.com/redmine/boards/28/topics/17822012-08-29T10:48:11ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>We would like to use a simple TI StarterWare based design possibly with SYSBIOS. I believe you mentioned you don’t have the StarterWare boot ported to this platform yet. I’m wondering if I can use the existing Linux SPL bootloader (MLO file) and use mkimage to take our binary image and transform it into a “u-boot.img” file with the appropriate header information. Do you think this is feasible?</p>
<p>In order for this to work, I have a few questions about the SPL boot. <br />Does the SPL boot initialize the SOM for full performance operation (i.e. PMIC & Arm Core for full power operation, PLLs for 720MHz, DDR for max performance, etc.)?<br />When the SPL is done with its initialization, does it search for a file called “u-boot.img”, load it and branch to the entry point?</p> MitySOM-335x (ARM Cortex-A8 Based Products) - Software Development: Boot from NAND?http://support.criticallink.com/redmine/boards/28/topics/17672012-08-28T10:19:47ZThomas Catalinotom.catalino@criticallink.com
<p>(posted for a customer)</p>
<p>Can the MityARM-3359 boot from NAND?</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: Debugging DSP in VirtualBox? http://support.criticallink.com/redmine/boards/10/topics/17322012-08-22T17:03:12ZThomas Catalinotom.catalino@criticallink.com
<p>Can JTAG debugging be performed from within CCS running in a VirtualBox?</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: Vision Development Kit - What toolcha...http://support.criticallink.com/redmine/boards/10/topics/17312012-08-22T17:00:43ZThomas Catalinotom.catalino@criticallink.com
<p>What GCC toolchain is used to build the VDK Linux application? DSP?</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: L138 - DSP Timer interrupt question ... http://support.criticallink.com/redmine/boards/10/topics/17082012-08-14T14:28:15ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>We are running on the board on the C674x side and have some success with our periodic timer interrupt. However, it seems we are not setting up the interrupt controller properly since we sometimes get periodic interrupts and sometimes we do not. It feels like it depends on the previous execution of code on the C674x after power-up. We are basically trying to get Tim12 to generate a periodic interrupt and Tim34 to be a separate, free running counter. We also are setup to field the Tim12 interrupt on the cpu interrupt 4. Below are the values we are putting in the timer registers, but we have no clue what to put in the interrupt controller registers 0x0180000 through 0x01800188. If you have any clues or a good contact at TI, that would be great!</p>
<p>Thanks,<br />Bill</p>
<pre>
TIM12_ADDR .set 0 x01f0c010 ; Timer12 Counter Register
TIM12_VAL .set 0 ; Timer12 Value
TIM34_ADDR .set 0 x01f0c014 ; Timer34 Counter Register
TIM34_VAL .set 0 ; Timer34 Value
PRD12_ADDR .set 0 x01f0c018 ; Timer12 Period Register
PRD12_VAL .set 20000000 ; Timer12 Period Value - 10ms default
PRD34_ADDR .set 0 x01f0c01c ; Timer34 Period Register
PRD34_VAL .set 0 xffffffff ; Timer34 Period Value
TCR_ADDR .set 0 x01f0c020 ; Timer Control Register
TCR_VAL .set 0 x00800080 ; ENAMODE34 = 2h, ENAMODE12 = 2h, timer is enabled continuously
TGCR_ADDR .set 0 x01f0c024 ; Timer Global Control Register
TGCR_VAL .set 0 x00000007 ; TIMMODE = 1h, timer is in dual 32-bit timer unchained mode, TIM34RS/TIM12RS = 1, not in rest
REL12_ADDR .set 0 x01f0c034 ; Timer12 Reload Register
REL12_VAL .set 0 ; Timer12 Reload Value
REL34_ADDR .set 0 x01f0c038 ; Timer34 Reload Register
REL34_VAL .set 0 ; Timer34 Reload Value
INTCTLSTAT_ADDR .set 0 x01f0c044 ; Timer Interrupt Control and Status Register
INTCTLSTAT_VAL .set 0 x00020003 ; Enable Timer12 interrupt
EMUMGT_ADDR .set 0 x01f0c004 ; Emulation Management Register
EMUMGT_VAL .set 1 ; Emulation Management Value, don't use stop bit
</pre> MitySOM-335x (ARM Cortex-A8 Based Products) - PCB Development: RE: schematic of MityARM-3359http://support.criticallink.com/redmine/boards/29/topics/1315?r=1680#message-16802012-08-05T20:27:33ZThomas Catalinotom.catalino@criticallink.com
<p>Thank you, Jason. I sent you an e-mail. Tom</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: FPGA bandwidth available on development kithttp://support.criticallink.com/redmine/boards/11/topics/16582012-07-27T21:49:14ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>I have a question about the FPGA I/O bandwidth coming off expansion headers 2 & 3 on the development kit. I would like to interface the FPGA to data converters and need to know the sampling rate limitations imposed by the Molex 79109-1224 connectors to the FPGA on the MityDSP-L138F module. I found min/max limit of 20/68MHz in the data sheet for the Profibus development kit. This was for the MDK-8 Digital I/O interface and I didn't know if this is the same as the FPGA I/O. Can you please tell me the recommended maximum single-ended and/or differential signal rates for the FPGA I/O to the expansion headers?</p> MitySOM-335x (ARM Cortex-A8 Based Products) - PCB Development: RE: schematic of MityARM-3359http://support.criticallink.com/redmine/boards/29/topics/1315?r=1572#message-15722012-07-12T22:45:42ZThomas Catalinotom.catalino@criticallink.com
<p>Hello Diego -</p>
<p>I have also sent the schematics and Altium design files to your e-mail.</p>
<p>Currently our policy on the module schematics has not been modified. We would, however, like to know if there is any information missing from our base board design guide that is required to design a base board or software on our module. If there is we would be happy to update it with the missing information so that not having the schematics does not hinder your progress.</p>
<p>Thank you again for using our products!<br />Tom</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: RE: MityDSP-L138F Mounting Holes (Posted o...http://support.criticallink.com/redmine/boards/11/topics/1558?r=1561#message-15612012-07-09T16:02:56ZThomas Catalinotom.catalino@criticallink.com
<p>I've attached the requested drawing, does this address your needs?</p>
<p>Tom</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: KSZ8995MA Ethernet Switch Supporthttp://support.criticallink.com/redmine/boards/10/topics/1428?r=1539#message-15392012-06-26T10:29:16ZThomas Catalinotom.catalino@criticallink.com
<p>Charlie -</p>
<p>Thanks for the update, great news!</p>
<p>Tom</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: Building new openembedded-core based ...http://support.criticallink.com/redmine/boards/10/topics/15282012-06-19T20:39:46ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>I would like to build a dev environment from scratch if possible and am following the beta instructions for building the new openembedded-core based system</p>
<p>The build is failing because of a reference to a base URI of a subversion repository svn://wanda/svn/mityomap/mityomapl138 in file sources/meta-mitydsp/include/mitydsp-preferred-revs.inc</p>
<p>It looks like an internal repository on your "wanda" machine. Is there an equivalent external URI I could use to access this repository?</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: RE: The schematic of MityDSP-L138 Developm...http://support.criticallink.com/redmine/boards/11/topics/1504?r=1513#message-15132012-06-13T12:44:13ZThomas Catalinotom.catalino@criticallink.com
<p>Hello Yilin -</p>
<p>I will e-mail you a link to download the design files for the MityDSP-L138 base board.</p>
<p>Thank you for using our product.</p>
<p>Tom</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: Voltagelevel for EMA (PowerGroup B - DVDD3...http://support.criticallink.com/redmine/boards/11/topics/15122012-06-13T11:55:25ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>which voltage level your EMIFA-Pins are configured? Is it 1,8V or 3,3V?</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: RTC 3V BATT Connection when not using RTC?http://support.criticallink.com/redmine/boards/11/topics/14932012-06-08T15:25:03ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>Quick question: hopefully an easy one to answer. If I don’t want to use a battery backed up RTC on the MityDSP-L138F what should I connect the 3V RTC BATT (pin 35) line to? Should it be connected to system power (3.3V), floating, or ground?</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: Non-FPGA module NAND Timings http://support.criticallink.com/redmine/boards/10/topics/14812012-06-01T09:08:19ZThomas Catalinotom.catalino@criticallink.com
<p>(Posted on behalf of a customer)</p>
<p>In the wiki it says that without a FPGA the NAND access changes: "... on the Industrial I/O host board, by adding additional wait states to the default NAND timings (contact critical link for details). "</p>
<p>I guess this must be a driver change in Linux and uBoot. Can you supply this information?</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: MACHINE type for the MDK ...http://support.criticallink.com/redmine/boards/10/topics/14292012-05-16T13:31:57ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>The Linux which I installed is the latest available with MDK-2-12, version Angstrom v2012.03-core - Kernel 3.2.0. I am currently downloading and installing the version for a different board to get to know how to use it, but it is set up to a particular MACHINE. For what MACHINE was the version supplied with the MDK created?</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: KSZ8995MA Ethernet Switch Supporthttp://support.criticallink.com/redmine/boards/10/topics/14282012-05-16T13:30:40ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>Have you, or do you know of anyone who has got a KSZ8995MA Ethernet Switch chip to work with the MityDSP-L138? The chip works fine as a switch but I want to get the Linux to recognise it. I will presumably have to modify the kernel setup to achieve this.</p> MitySOM-335x (ARM Cortex-A8 Based Products) - Software Development: RE: Connecting JTAG to Mityar...http://support.criticallink.com/redmine/boards/28/topics/1422?r=1427#message-14272012-05-16T13:21:09ZThomas Catalinotom.catalino@criticallink.com
<p>Hi Raja -</p>
<p>Sorry for the delay in getting back to you on this. We are working this now and will have an answer for you as soon as we can.</p>
<p>Thanks,<br />Tom</p> MitySOM-335x (ARM Cortex-A8 Based Products) - Software Development: Is there a linux driver for R...http://support.criticallink.com/redmine/boards/28/topics/13622012-04-19T15:24:11ZThomas Catalinotom.catalino@criticallink.com
<p>Is there a linux driver for RMII or just RGMII?</p> MitySOM-335x (ARM Cortex-A8 Based Products) - Software Development: Is RMII possible with the Mit...http://support.criticallink.com/redmine/boards/28/topics/13612012-04-19T15:22:42ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>Is RMII possible with the MityARM-3359? I didn’t see some on the alternate functions listed in Critical Links documentation but it exist in TI’s.</p>
<p>(whoops, posted to the wrong forum, can't seem to move it!)</p> MitySOM-335x (ARM Cortex-A8 Based Products) - PCB Development: Is a separate I2C EEPROM needed to...http://support.criticallink.com/redmine/boards/29/topics/13532012-04-17T22:04:36ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>All the other AM3359 boards have this (ULCD, TI EVM, BeagleBone, etc.) and it looks like the EEPROM ID triggers companion code in the kernel. The EEPROM basically tells the kernel what hardware is connected and what pinmux settings are needed for that hardware (and possibly other things based on EEPROM ID). The TI SDK works with the MistDSP out of the box. Does this might mean that the MityDSP has its own EEPROM ID that the TI Kernel can detect and autoconfigure? Or are expected to set up our pinmux table with a custom ID and the TI kernel will take care of setting everything up right.</p> MitySOM-335x (ARM Cortex-A8 Based Products) - PCB Development: SPI1 pin conflict:http://support.criticallink.com/redmine/boards/29/topics/13522012-04-17T22:01:58ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>MityDSP has dedicated pins 193, 195 and 197 to SPI1 because they connected it to an SPI NOR flash, however using either pins 195 or 197 Data with the 193 clock for SPI1 results in “IO Set violation” warnings in the Pinmux utility. Is the TI Pinmux utility overly restrictive or is the MityDSP documentation wrong?</p>
<p>From your doc: “Note that the SPI1 chip select 0, however, is reserved in order to support booting from the on-board NOR flash. After bootloading, access to the NOR flash is typically not required, and the SPI port may be used with other chip selects if required.” Are we OK to use the SPI1 pins as documented?</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: SODIMM Pin 53 ... http://support.criticallink.com/redmine/boards/11/topics/13232012-04-07T21:33:16ZThomas Catalinotom.catalino@criticallink.com
<p>(Posted on behalf of a customer)</p>
<p>The datasheet for the MITYDSP-L138F shows Pin 53 as reserved, however the Industrial IO board uses it for SPI1_SCS0. Why does the datasheet show it as reserved?</p> MityDSP (TI TMS320C6xxx Based Products) - Software Development: RE: emulator initialization from ...http://support.criticallink.com/redmine/boards/8/topics/1280?r=1319#message-13192012-04-05T20:04:37ZThomas Catalinotom.catalino@criticallink.com
<p>Glad to hear that you're moving forward, let us know if you need any additional support.</p>
<p>Tom</p> MitySOM-335x (ARM Cortex-A8 Based Products) - PCB Development: RE: schematic of MityARM-3359http://support.criticallink.com/redmine/boards/29/topics/1315?r=1318#message-13182012-04-05T20:01:47ZThomas Catalinotom.catalino@criticallink.com
<p>Hello Amin -</p>
<p>Critical Link does not provide the schematic diagram for our MityDSP modules. However, we do understand that detailed information is needed by developers using our modules to develop base boards and software for them so we provide the following design guides that should provide any information needed to develop with our modules.</p>
<p>You can find the design guides here: <a class="external" href="http://www.mitydsp.com/products-services/cpu-engines/design-guides/">http://www.mitydsp.com/products-services/cpu-engines/design-guides/</a></p>
<p>In addition, for technical questions not addressed by the design guides please feel free to post here.</p>
<p>We do, however provide as much information for the development kit base board as you would like, Amin, I will e-mail you the schematics and Altium format design files for the development kit base board. We hope they will help you be successful with your design.</p>
<p>Tom</p> MitySOM-335x (ARM Cortex-A8 Based Products) - Software Development: Virtual Box abortshttp://support.criticallink.com/redmine/boards/28/topics/13062012-04-04T09:02:32ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>I have installed the “mityarm-335x_SDK.ovf” on to the Linux machine with the help of VM Virtual box software and started running the same.</p>
<p>While trying to compile the kernel located at “Home/projects/linux-mityarm-335x”, connection to Virtual box is getting aborted and in turn the compilation process. Even simple tar command to compress kernel also creating the same problem.<br />I have changed the settings to avoid screen saver and display turn off in case it has an effect.</p>
<p>Could you please let me know any further settings need to be done?</p> MitySOM-335x (ARM Cortex-A8 Based Products) - PCB Development: 48V Power Supply Suggestion ... http://support.criticallink.com/redmine/boards/29/topics/12982012-04-02T13:26:01ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>As per our product specification, we need to use 48 V input power supply, so we are planning to use 0ne 48V to 12 v POWER SUPPLY. CAN YOU SUGGEST ANY SUITABLE POWER SUPPLY FOR THE SAME .</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: Dead board http://support.criticallink.com/redmine/boards/10/topics/12752012-03-27T07:34:32ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>- I tried to flash a new application to my module. Therefor I performed: sfh_OMAP-L138.exe –flash –v –p COM1 UPL_SPI_MEM.ais myApp.out.</p>
<p>- After a reset, the serial connection remained silent.</p>
<p>- I re-flashed with the u-boot image: sfh_OMAP-L138.exe –flash –v –p COM1 UPL_SPI_MEM.ais u-boot.bin<br />à Operation completed successfully.</p>
<p>- But the serial connection remains still silent.</p>
<p>I’m able to connect to the target with JTAG and run my application from the Shared Memory Section. But it is not possible to load the program into DDR<br />è ARM9_0: Trouble Setting Breakpoint with the Action "Continue or Finish Stepping" at 0xfffd5684: Error 0x00000008/-1066 Error during: Break Point, Cannot set/verify breakpoint at 0xFFFD5684 <br />ARM9_0: File Loader: Data verification failed at address 0xC1080000 Please verify target memory and memory map.</p>
<p>- ARM9_0: GEL: File: D:\Program Files\Texas Instruments\OMAPL138_StarterWare_1_10_01_01\build\armv5\cgt_ccs\omapl138\evmOMAPL138\uart\Debug\uartEcho.out: a data verification error occurred, file load failed.</p> MitySOM-335x (ARM Cortex-A8 Based Products) - PCB Development: Power supply requirementshttp://support.criticallink.com/redmine/boards/29/topics/12682012-03-23T15:49:57ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>In design guide (for the MityARM-335x) page 12 section 3.1 power supply requirements are given but no indicative current. Can you give me ball park on this.</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: StarterWare question ... http://support.criticallink.com/redmine/boards/10/topics/1235?r=1260#message-12602012-03-21T20:01:35ZThomas Catalinotom.catalino@criticallink.com
<p>Hi Stephane -</p>
<p>Unfortunately we believe you are executing the low level initialization code for the TI EVM which is different than what needs to execute for our module. We believe this is why you are having difficulty.</p>
<p>We need to address for you how we are going to get StarterWare support functional for you (and other customers) on our boards. We will work to address this as quickly as possible.</p>
<p>Thank you - <br />Tom</p> MityDSP (TI TMS320C6xxx Based Products) - Software Development: Loading code to on-board 6455 SRAM http://support.criticallink.com/redmine/boards/8/topics/12432012-03-14T09:41:48ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer using MityDSP-Pro)</p>
<p>I have so far only loaded & run via CCSv5, but soon I will want to run via boot from a hex file stored in FLASH. However, I see an ominous note under "IRAM" on pg 28 of your Day-1 PM Training slides: "Note: Current bootloader doesn’t support loading code to IRAM from FLASH." I think I saw that elsewhere in the training slides. Is that still the case? If so, can the bootloaded load into L1P? How do I make this work? I need to put code & data into L1P, L1D, & L2, since there is not enough room in L1P & L1D, and DDR2 is way too slow.</p> MityDSP (TI TMS320C6xxx Based Products) - Software Development: Placing code into onboard 6455 SRAMhttp://support.criticallink.com/redmine/boards/8/topics/12422012-03-14T09:40:22ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer who is using the MityDSP-Pro)</p>
<p>I've been trying to put an interrupt service routine (ISR) and the data it touches into L1P & L1D on the c6455 (MityDSP-Pro). Using L2 for code & data works fine, but I can't get things to work if I put the ISR code in L1P. I have been loading & running via CCS (a related bootloader question at the end of this email).</p>
<p>I've tried a very simple ISR put in L2 with one L1D variable getting incremented, and that works fine. If I then try to put the ISR into L1P, the ISR doesn't get called. When I try to pause the DSP to look variables in CCS, this error window pops up:</p>
<pre>Trouble Halting Target CPU:
Error 0x00000024/-1060
Error during: Register, Execution,
An unknown error prevented the emulator from accessing the processor
in a timely fashion.
It is recommended to RESET EMULATOR. This will disconnect each
target from the emulator. The targets should then be power cycled
or hard reset followed by an emureset and reconnect to each target.
</pre>
<p>I am using DSP/BIOS 5.41 and I'm using the ISR Dispatcher in the HWI ISR manager. Under Scheduling->HWI in the DSP/BIOS config tool, I am using a "RESET vector address" of 0x00800000 (the start of L2). Would that need to change to an L1 address? As I recall, your examples use L2. Do you have any examples using L1 or other suggestions?</p>
<p>I can provide more details of how I have things set up, but I thought I'd pass the general issue by you in case you are aware of some limitations on what I'm trying to do.</p>
<p>I am presently looking into L1 memory protection settings, since tests are showing the program stopping when I try to call a function I put in L1P. Maybe the bootstrapper/loader disables L1P (or leaves it disabled) and my DSP code needs to turn it back on? If that rings a bell, please let me know.</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: StarterWare question ... http://support.criticallink.com/redmine/boards/10/topics/12352012-03-06T14:56:23ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>For the starterware non-os method, I have built some of the starterware examples using code composer. I have converted those to bin files with the out2rprc executable. I am at the point that I need to send the file to uboot I guess. Is there a way that I can do that from the uboot prompt? Or do I need to do the flashing method with sfh_OMAP-L138.exe? If so, I see the sfh executable needs an AIS file and I see that the linux disk I received has an AIS in the images folder (UBL_SPI_MEM.ais). Is that the AIS file I should be using?</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: Critical Link Package locations?http://support.criticallink.com/redmine/boards/10/topics/12332012-03-06T10:12:00ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>What are the updated feed addresses for the critical link packages?</p>
<p>(these are the errors I get from opkg update)</p>
<p>Downloading <a class="external" href="http://www.angstrom-distribution.org/feeds/unstable/ipk/glibc/armv5te/machine/mityomapl138/Packages.gz">http://www.angstrom-distribution.org/feeds/unstable/ipk/glibc/armv5te/machine/mityomapl138/Packages.gz</a>.<br />wget: server returned error: HTTP/1.1 404 Not Found</p>
<ul>
<li>opkg_download: Failed to download <a class="external" href="http://www.angstrom-distribution.org/feeds/unstable/ipk/glibc/armv5te/machine/mityomapl138/Packages.gz">http://www.angstrom-distribution.org/feeds/unstable/ipk/glibc/armv5te/machine/mityomapl138/Packages.gz</a>, wget returned 1.</li>
</ul> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: FPGA no-connects for 45 size FPGA on MityD...http://support.criticallink.com/redmine/boards/11/topics/12282012-02-28T08:47:31ZThomas Catalinotom.catalino@criticallink.com
<p>(Posted on behalf of a customer)</p>
<p>We have done a design using the MityDSP-L138F SOM. I tried avoiding using the pins on the FPGA that are not connected in the larger variant, but I was not succesfull, meaning I accidently used two of the pins, namely 170 + 172 (FPGA pins E7 + E8); which is fine for the -16 variant of the FPGA.</p>
<p>For our prototypes we would like to be able to use the -45 variant of the FPGA and hence my question:<br />How are SOM pins 170 + 172 on the -45 (L138-xI-225-Rx) connected?</p>
<p>If they are floating I can do a "hack" on the SOM, which would provide the most "elegant" fix to my bug.</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: MityDSP-L138F Footprint Question http://support.criticallink.com/redmine/boards/11/topics/12242012-02-16T20:03:03ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>For the MityDSP-l138F, I noticed the drill hole for the standoff in the Altium file (for the Industrial IO board) is acutally about 1780mils from the center of the DIMM Connector. As oppose to 2in - .2 shown in the diagram (in the carrier board design guide). Is the 20mil difference done to make sure that the L138F makes a good contact with the DIMM connector?</p> MityDSP-L138 (ARM9 Based Platforms) - FPGA Development: AXI Compatibility? http://support.criticallink.com/redmine/boards/12/topics/12112012-02-06T20:17:57ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer for the MityARM-1808F module)</p>
<p>Any advice on how to connect your EMIF interface to an AXI bus (a Xilinx FPGA core standard) in the FPGA would be appreciated.</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: RTC Battery Drainhttp://support.criticallink.com/redmine/boards/11/topics/12022012-02-01T11:13:27ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>A quick question for you, or perhaps someone else on your team, regarding<br />the RTC on the L138 modules and the profibus development kit battery:</p>
<p>We have noticed that the RTC batteries have been running low quickly. For<br />example, we installed two batteries last night that were reading around 3.5<br />V. We checked them this morning and they are now around 2.7 V.</p>
<p>We might have bad/old batteries. However, all of our profibus development<br />boards have a low RTC battery on them, so we are curious if there is some<br />other root cause.</p>
<p>I noticed today that the linux driver we were using was clearing a "split<br />power supply" bit in the RTC control register on boot, which might account<br />for an increase in the leakage current and thus low battery life (see page<br />24 of <a class="external" href="http://www.ti.com/lit/ug/sprufm3c/sprufm3c.pdf">http://www.ti.com/lit/ug/sprufm3c/sprufm3c.pdf</a>, the SPLITPOWER bit of<br />the RTC control reg). I hope that will fix the issue -- time will tell.</p>
<p>So, I am simply curious -- have you seen the RTC battery running low before?<br />Any recommendations? Perhaps even a part number/supplier of "known good" <br />batteries? Any advice or suggestions would be greatly appreciated!</p> MityDSP (TI TMS320C6xxx Based Products) - Software Development: FPGA Interrupts on MityDSP-Prohttp://support.criticallink.com/redmine/boards/8/topics/11332012-01-09T21:49:41ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>I am trying to get some documentation on the FPGA/DSP interrupts for the MityDSP-Pro. In the MityDSP-Pro data sheet "MityDSP-PRO Data Sheet" at <a class="external" href="http://www.mitydsp.com/images/upload/File/MityDSPProSpec(1).pdf">http://www.mitydsp.com/images/upload/File/MityDSPProSpec(1).pdf</a>, Figure 1 on page 2 shows an "IRQ" arrow going from the FPGA to the DSP. Also, the last sentence at the bottom of page 3 of the same document says "The MityDSP-Pro also includes lines between the FPGA and the MityDSP for the purposes of generating interrupt signals." The problem is that I can't find any documentation on these interrupts such as pins on the FPGA and matching interrupts lines (gpio or other?) on the DSP side. Actually, I can't find any documentation in general (interrupts or other) on the FPGA/DSP interface. Am I missing some documentation or something? This is crucial for my team's development efforts on the FPGA and DSP.</p> MityDSP (TI TMS320C6xxx Based Products) - Software Development: Builds and SYS/BIOS questions ...http://support.criticallink.com/redmine/boards/8/topics/11322012-01-06T14:43:26ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>I had some early errors regarding -mv64+. I was not aware that the c6455 is a "C64x+" device, so some compile errors occurred until I specified "Generic C64x+ Device" in the "Main" tab under the "General" project settings, and specified "64+" under the compiler Basic Options (for target processor).</p>
<p>I specified "rts64plus.lib" for runtime support to go with the "64+".</p>
<p>I also used DSP/BIOS version 5.41.11.38 since I read that the "SYS/BIOS" (version 6.x??) does not support the c6455. Is that true?</p>
<p>In the BIOS->System->Global Settings, I changed the target name to "c6455" (probably not necessary?), board clock to 50000 kHz (information only), and DSP Speed to 1200 MHz (it was 600 MHz).</p>
<p>Any comments or issues with the above?</p> MityDSP (TI TMS320C6xxx Based Products) - Software Development: SYS/BIOS Version 6.x on the MityD...http://support.criticallink.com/redmine/boards/8/topics/11312012-01-06T14:42:30ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>Can I use the new "SYS/BIOS" (version 6.x??) with the c6455? I would like to start with the latest stuff to slow my obsolescence. If I can use it, do I use the same template file I used for SYS/BIOS? I tried going that route, but I didn't see the same kind of "import" support as with DSP/BIOS pulling in your tci file. Any wisdom on this?</p> MityDSP (TI TMS320C6xxx Based Products) - PCB Development: RE: FPGA/DSP Interface Details & exter...http://support.criticallink.com/redmine/boards/9/topics/1114?r=1115#message-11152011-12-28T08:20:07ZThomas Catalinotom.catalino@criticallink.com
<p>Doug -</p>
<p>I will let the technical team answer the question about the external interrupts. However, we will add information in our design guide detailing the interface between the FPGA and DSP, we will get this done as soon as possible.</p>
<p>Thanks,<br />tom</p> MityDSP (TI TMS320C6xxx Based Products) - PCB Development: FPGA/DSP Interface Details & external ...http://support.criticallink.com/redmine/boards/9/topics/11142011-12-28T08:16:55ZThomas Catalinotom.catalino@criticallink.com
<p>(Posted on behalf of a customer)</p>
<p>I am working on designing the carrier interface board for the MityDSP Pro module. I have the carrier design guideline document but I would like to get more details on the DSP board itself. Specifically the interface connection from the DSP to the FPGA. One issue I am having is I would like to have an external interrupt go to the DSP from the carrier card and it doesn’t appear that there is easy access to the DSP external interrupts other than the PCI interface.</p>
<p>Any documentation or suggestions would be appreciated.</p>
<p>Hope you have a great Holiday….</p>
<p>Thanks,<br />Doug</p> MityDSP (TI TMS320C6xxx Based Products) - PCB Development: RE: MityDSP-Pro FPGA questions ... http://support.criticallink.com/redmine/boards/9/topics/1073?r=1108#message-11082011-12-22T11:53:09ZThomas Catalinotom.catalino@criticallink.com
<p>(from Anthony)</p>
<p>Michael,</p>
<p>Thanks for the response. From what you describe it seems that the signals I intend to use are fine the way they are connected up in our schematics, which just leaves us needing to make sure we have the bootloader come up in a way that utilizes the DSP EMAC in 10/100 mode…Knowing what the bootloader does is a huge explanation, is there somewhere that I missed reading the actual boot up process in detail because from the schematic I was totally confused based on what I was seeing in the demo.</p>
<p>My previous assumption was that the evaluation board most likely came with an FPGA image that does far more than what we will initially be needing it to do outside of whatever logic the DSP might need to access the boot flash and other stuff. This is understandable but we now need to take it back down to a more basic level with minimal function in the hopes of being able to better understand how we need to implement our designs.</p>
<p>I’m going to think out loud here for a minute and you can correct me. In researching the MityDSP directory install I noticed that there is a section for hardware that has both a ‘development’ directory called “C:\MityDSP\2.10\hardware\FPGA” and another called “C:\MityDSP\2.10\hardware\FPGA_boot”.</p>
<p>In the directory labeled “C:\MityDSP\2.10\hardware\FPGA_boot” I see several sub directories that appear to have pre-compiled FPGA bitstreams for various sized FPGA’s of which I am very familiar with having designed with Xilinx for over 15 years. More specific, in the sub directory XC3S4000_Pro is what I assume to be a more base or simpler FPGA image?</p>
<p>I also notice in the VHDL directory various files of which 2 standout relating to the DSP_Pro, at least that’s my thinking. “MityDSP_eth.vhd” and “MityDSP-Pro.vhd” are the 2 files which I have actually called up as designs, created projects and managed to compile to bit stream generation successfully. However, being that the majority of our work has never needed the largest FPGAs, we have managed to do all our work with the free WebPack ISE that Xilinx offers. In any case, I did manage to target the largest device in the WebPack which is the XC3S1500. The Critical Link MityDSP plug-in uses the XC3S4000 but again, the largest device supported in the free WebPack ISE is the 1500, however, using the constraints file provided I did not receive any errors that prevented the tools from compiling the design into the XC3S1500. This was all in an effort to make sure I could recompile the designs and call up the correct cores properly. In fact I was missing 2 core generator files and created my own based on the errors and investigating the VHDL files, it worked. Eventually Tom sent me the missing files and I reran the designs with those and was successful again.</p>
<p>In looking at the VHDL code itself, it would seem to me that ‘MityDSP-Pro.vhd’ has the basic RS232 function in addition to the LED signals called FPGA_RSV1 & FPGA_RSV2 on the SO-DIMM connector that I would need to drive activity and link for the 10/100 function of the TI DSP? Here is the section of code I am referring to:</p>
<p>This is taken from MityDSP-Pro.vhd file…</p>
<p>-- I/O pins for RS232 interface<br />i_rs232_rcv : in std_logic;<br />o_rs232_xmit : out std_logic;<br />i_rs232_cts : in std_logic;<br />o_rs232_rts : out std_logic;</p>
<p>-- I/O pins for USB interface<br />-- i_usb_rcv : in std_logic;<br />-- o_usb_xmit : out std_logic;<br />-- i_usb_cts : in std_logic;<br />-- o_usb_rts : out std_logic;</p>
<p>o_sba_data : out std_logic;<br />o_sba_clk : out std_logic;</p>
<p>o_led0_n : out std_logic; (Are these the 2 lines that drive FPGA_RSV1 & FPGA_RSV2?)<br />o_led1_n : out std_logic; ( )</p>
<p>i_config : in std_logic_vector(2 downto 0) (Is this used on board the plug-in module transparent to the user?)<br /> );<br />end MityDSP_Pro;</p>
<p>Is the bitstream that is located in XC3S4000_Pro sub directory in fact that VHDL design (MityDSP-Pro.vhd)? If so, by reprogramming “MityDSP-Pro_boot_4k.mcs” into the current plug-in module would that ensure that the DSP EMAC comes up in 10/100 mode as well as having the FPGA_RSV1 & RSV2 signals become active for activity and link on the RJ-45 connector?</p>
<p>I believe I am understanding the whole setup better now that some pieces of the puzzle have been filled in. If the file I mention above does not do what I think it does, can you generate an XC3S4000 bit stream with the basic functions we would need to boot as well as have RS232 and the LED signals driven?</p>
<p>Thanks,</p>
<p>Anthony</p> MityDSP (TI TMS320C6xxx Based Products) - PCB Development: RE: MityDSP-Pro FPGA questions ... http://support.criticallink.com/redmine/boards/9/topics/1073?r=1102#message-11022011-12-21T13:01:41ZThomas Catalinotom.catalino@criticallink.com
<p><cite>From the schematics it appears that the evaluation board is connected to both RJ-45 connectors, one goes to the 10/100 signals on the plug-in module DSP EMAC and the other to what appears to be a Gigabit PHY which uses a GEMAC running out of the FPGA, is that correct</cite>?</p>
<p>Almost correct. The DSP MAC is the 10/100/1000 and the FPGA MAC is 10/100. I will ask one of the guys here to help you through getting the demo functional.</p>
<p>Thanks,<br />Tom</p> MityDSP (TI TMS320C6xxx Based Products) - PCB Development: MityDSP-Pro FPGA questions ... http://support.criticallink.com/redmine/boards/9/topics/10732011-12-14T18:13:11ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>RS232_TXD SO-DIMM pin 14<br />RS232_RXD SO-DIMM pin 16</p>
<p>FPGA_RSV1 SO-DIMM pin 21<br />FPGA_RSV2 SO-DIMM pin 23</p>
<p>Since we are not using anything out of the FPGA by our design, I am assuming (hoping) that the FPGA image provided on your DVD install in the following directory:</p>
<p>“C:\MityDSP\2.10\hardware\FPGA_boot\xc3s4000_Pro\MityDSP-Pro_boot_4k.mcs”</p>
<p>Does the following:</p>
<p>Has basic RS232 communication & drives the RSV pins to allow us to determine Ethernet activity since we are simply using the 10/100 as is off the SO-DIMM connector.</p>
<p>Can you let me know if that assumption is correct? If not then we will need to figure out how to display Ethernet activity so that we know everything is at least trying to communicate. The MityDSP-Pro plug-in module, is that what is programmed, the above mcs file?</p> MityDSP (TI TMS320C6xxx Based Products) - Software Development: RE: MityDSP-Pro with Pro Motherbo...http://support.criticallink.com/redmine/boards/8/topics/1032?r=1033#message-10332011-11-29T11:50:35ZThomas Catalinotom.catalino@criticallink.com
<p>Customer indicates these issues have been resolved.</p> MityDSP (TI TMS320C6xxx Based Products) - Software Development: MityDSP-Pro with Pro Motherboard ...http://support.criticallink.com/redmine/boards/8/topics/10322011-11-29T11:41:04ZThomas Catalinotom.catalino@criticallink.com
<p>(on behalf of a customer, customer is using CCS 4)</p>
<p>So a few items I see so far is that the USB is not loading up the driver, can’t find it and I can’t seem to find any drivers on the DVD or MityDSP directory, are drivers supposed to be included? I let the auto install search everywhere including online but can’t find any, so that’s a problem.</p>
<p>The TI debugger is also looking for a driver (hardware management via Windows), can’t find one either…</p>
<p>So from what I’m seeing so far, there are 2 items, the debugger and basic USB driver not installing correctly as the drivers can’t be found, not sure what to do about that.</p>
<p>We are using Windows XP-Pro with service pack 3 installed so no reason Windows shouldn’t be able to find drivers. There is nothing else that came with our eval kit regarding drivers or software, was there supposed to be?</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: Loading UBL and U-Boothttp://support.criticallink.com/redmine/boards/10/topics/1027?r=1031#message-10312011-11-29T09:26:58ZThomas Catalinotom.catalino@criticallink.com
<p>Gregory -</p>
<p>In the development kit there is both a small cable that adapts the dual-row header to DB9 and also a DB9 to DB9 serial cable, they both must be used together as the DB9 to DB9 is a null modem configuration. Perhaps you are only using the small dual-row to DB9 cable?</p>
<p>Tom</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: Loading UBL and U-Boothttp://support.criticallink.com/redmine/boards/10/topics/10272011-11-28T15:00:47ZThomas Catalinotom.catalino@criticallink.com
<p>(Posted on behalf of a customer)</p>
<p>I received the MityDSP-L138F Development Kit (80-000268RI-2A) today. I am unable to recevive "BOOT ME" via UART for loading UBL and U-BOOT on it.</p>
<p>I use the following command line : >mono sfh_OMAP-L138.exe -erase -p /dev/ttyUSB0.</p>
<p>I received the error message in holding the button Boot on the board : (Serial Port): Read error! .... Do this board haven't the UBL, UBBOT and Linux Kernel installed ? Do I must load its on this board myself ?</p>
<p>I spend several hours to understand the inferface between OMAP and FPGA devices using the kernel modules (fpga_i2c.ko, fpga_pwm.ko, fpga_gpio.ko etc) Please explain me about its with block diagram. Why you use these modules ?</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: Kernel Hanghttp://support.criticallink.com/redmine/boards/10/topics/984?r=986#message-9862011-11-10T09:58:57ZThomas Catalinotom.catalino@criticallink.com
<p>Mike -</p>
<p>Andrew provided this information to me prior to posting on the forum:</p>
<p>I built a kernel, following the instructions at <a class="external" href="http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Installing_Open_Embedded">http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Installing_Open_Embedded</a></p>
<p>With the following commands:</p>
<pre>
git clone git://support.criticallink.com/home/git/linux-davinci.git linux-davinci
cd linux-davinci/
git checkout -b devel origin/devel
. /usr/local/angstrom/arm/environment-setup
unset CPATH
make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabi- distclean
make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabi- mityomapl138_defconfig
make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabi- uImage
</pre>
<p>Tom</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: Kernel Hang Anomalyhttp://support.criticallink.com/redmine/boards/10/topics/967?r=969#message-9692011-11-01T20:51:42ZThomas Catalinotom.catalino@criticallink.com
<p>Hi David -</p>
<p>I'll let the technical team address the hang. But just wanted to let you know that modules are shipped without a kernel or file system installed. This is a customer configuration step since our customers run a variety of operating systems and configurations. Sorry if this has caused any confusion.</p>
<p>Thanks,<br />Tom</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: RE: PROFIBUS Dev Kit RS485 on J504http://support.criticallink.com/redmine/boards/11/topics/919?r=930#message-9302011-10-26T10:24:11ZThomas Catalinotom.catalino@criticallink.com
<p>Hi Mike -</p>
<p>You are correct, thank you for pointing this out. The table in the data sheet is from an older revision to the board before we moved the line drivers to an external, panel mounted (and currently customer supplied).</p>
<p>We will get the datasheet updated, I apologize for the confusion.</p>
<p>Thanks,<br />Tom</p> MityDSP-L138 (ARM9 Based Platforms) - PCB Development: RE: PROFIBUS Dev Kit RS485 on J504http://support.criticallink.com/redmine/boards/11/topics/919?r=920#message-9202011-10-25T14:10:10ZThomas Catalinotom.catalino@criticallink.com
<p>Hi Mike -</p>
<p>They are TTL and meant to ribbon cable to a small driver board that can be panel mounted to minimize stub length for PROFIBUS applications.</p>
<p>We may not have made that clear enough in the documentation and will take an action to clear that up.</p>
<p>Tom</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: uPP receive problemhttp://support.criticallink.com/redmine/boards/10/topics/884?r=890#message-8902011-10-20T13:23:28ZThomas Catalinotom.catalino@criticallink.com
<p>Hi Scott -</p>
<p>Thanks for posting.</p>
<p>I talked to the guys about this problem that you're having. It sounds like any number of issues in the handshake between the FPGA and the uPP peripheral could be causing your issue. They mentioned Data Ready, Data Valid, etc, all needing to be dealt with / provided by the FPGA properly. In order to really assist they would probably need to dig into your design and roll up their sleeves with source code and timing diagrams, etc. If you'd like us to do that we can talk about setting up a vehicle to do that.</p>
<p>We've used this peripheral in numerous designs (5 to 10) running at speeds ranging from 27Mhz to the full 75Mhz speed with no issues, so we do not believe it to be a board design issue, but more than likely something in the handshake code in the FPGA.</p>
<p>I know this doesn't really help you at the moment. Feel free to give me a call if you'd like to talk it through further.</p>
<p>Thanks,<br />Tom</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: no serial data when first using d...http://support.criticallink.com/redmine/boards/10/topics/748?r=751#message-7512011-09-08T16:29:39ZThomas Catalinotom.catalino@criticallink.com
<p>Mike -</p>
<p>Glad you are up and running. Good point about the out of box experience.</p>
<p>Thanks,<br />Tom</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: MityDSP GUIhttp://support.criticallink.com/redmine/boards/10/topics/696?r=697#message-6972011-08-15T17:02:36ZThomas Catalinotom.catalino@criticallink.com
<p>Hi Thomas -</p>
<p>The MityDSP GUI is used only with our 6711 and 6455 based product. I believe you have an OMAPL138 or AM1808 based product, is this correct?</p>
<p>Thank you - <br />Tom</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: Mapping code to IRAMhttp://support.criticallink.com/redmine/boards/10/topics/648?r=649#message-6492011-07-26T17:14:54ZThomas Catalinotom.catalino@criticallink.com
<p>Hi Marc -</p>
<p>I'm not sure we will have the answer to this question as it's really a TI question. While we're waiting for a response from my team you may also wish to post it on the TI e2e forums.</p>
<p>Tom</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: Industrial board USB mini-B conne...http://support.criticallink.com/redmine/boards/10/topics/548?r=549#message-5492011-06-30T17:34:18ZThomas Catalinotom.catalino@criticallink.com
<p>Hi Zoltan -</p>
<p>You are correct. Thank you for pointing this out!</p>
<p>This fix will go into the next build of boards. I apologize for any inconvenience.</p>
<p>Thanks,<br />Tom</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: How Do I Get SD Memory Working fo...http://support.criticallink.com/redmine/boards/10/topics/313?r=371#message-3712011-03-05T09:19:50ZThomas Catalinotom.catalino@criticallink.com
<p>Hi David,</p>
<p>What throughput do you need or expect to get? I don't think the SD card is ever going to be as fast as a RAM based file system. I'm not sure what performance you are trying to get to.</p>
<p>Thanks,<br />Tom</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: I2C Board Support Packagehttp://support.criticallink.com/redmine/boards/10/topics/236?r=254#message-2542010-11-16T07:44:15ZThomas Catalinotom.catalino@criticallink.com
<p>Hi Simon -</p>
<p>The latest version of our kernel is included in the tarball on the BSP wiki page located here:</p>
<p><a class="external" href="http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Board_Support_Package">http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Board_Support_Package</a></p>
<p>Tom</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: I2C Board Support Packagehttp://support.criticallink.com/redmine/boards/10/topics/236?r=238#message-2382010-11-05T11:26:42ZThomas Catalinotom.catalino@criticallink.com
<p>Hi John -</p>
<p>I believe you are looking at using the I2C driver we provide under the FPGA directory. This driver is indeed used for an FPGA based I2C core and not the I2C provided on the OMAP itself.</p>
<p>See Mike's post about how to get to the I2C driver for the onboard OMAP I2C driver ...</p>
<p>Tom</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: Timers and interrupthttp://support.criticallink.com/redmine/boards/10/topics/202?r=211#message-2112010-11-01T10:39:51ZThomas Catalinotom.catalino@criticallink.com
<p>Hi Simon -</p>
<p>I realize you are trying to use an AM1808 module, but using an OMAP-L138 and using the DSP for this quick turnaround might be an easier, and possibly more reliable, solution.</p>
<p>Is there a particular reason for focusing on the ARM only module?</p>
<p>Thanks,<br />Tom</p> MityDSP-L138 (ARM9 Based Platforms) - FPGA Development: RE: POWER DOWN Memory Corruptionhttp://support.criticallink.com/redmine/boards/12/topics/87?r=90#message-902010-08-24T21:11:18ZThomas Catalinotom.catalino@criticallink.com
<p>If your application will not be writing to the NAND flash then you should not need hold-up circuit from the motherboard. However, if you plan to mount a user filesystem rw, and plan to write to it during normal operation, then you may want to consider it, or other means to insure the filesystem will not be corrupt. For example, always having a backup of your data file (and a way to validate it's integrity) may be a reasonable way to deal with this issue. There may be other techniques as well that I'm not immediately aware of.</p>
<p>Tom Catalino</p> MityDSP-L138 (ARM9 Based Platforms) - FPGA Development: RE: POWER DOWN Memory Corruptionhttp://support.criticallink.com/redmine/boards/12/topics/87?r=88#message-882010-08-24T20:58:00ZThomas Catalinotom.catalino@criticallink.com
<p>John -</p>
<p>We are indeed aware of this and are working on a solution. We plan to allow for the root file system to be mounted as a read-only file system (currently it's mounted read-write). Mounting the root file system read only will allow power to be removed at any time without impacting the integrity of the root file system, and therefore, the system's ability to boot. Once we have this capability we will make it available to all customers.</p>
<p>Having said this, we recognize that customers will want to use the NAND flash to also mount a user file system read-write in order to record data or logging information. As with writing to any flash in an embedded system, care must be taken in the application to deal with a power failure during a write operation.</p>
<p>Tom Catalino</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: Downloadhttp://support.criticallink.com/redmine/boards/10/topics/7?r=9#message-92010-07-08T20:25:14ZThomas Catalinotom.catalino@criticallink.com
<p>Dennis -</p>
<p>Just like to add that if all you need to do is download an application to the filesystem in NAND flash, and Linux is already up (on the target), there are a number of other options. These would include standard FTP (would have to make sure the FTP server is installed on the target and running), NFS copy, or the scp command from your host system.</p>
<p>Tom</p> MityDSP-L138 (ARM9 Based Platforms) - Software Development: RE: MityDSP GUIhttp://support.criticallink.com/redmine/boards/10/topics/1?r=2#message-22010-07-06T12:15:57ZThomas Catalinotom.catalino@criticallink.com
<p>Hi Uffe -</p>
<p>Thank you for your question.</p>
<p>The MityDSP GUI is compatible with the 6711 and 645x platforms from Critical Link.</p>
<p>The OMAP-L138 and AM1808 platforms should indeed be compatible with the SFH utility from TI. We are currently working on validating this and will provide information on running the SFH utility with our platforms once the validation is complete.</p>
<p>However, the SFH utility is primarily for loading the NOR flash on a board / system that is either not programmed, or has become corrupt. All systems we ship have the NOR flash pre-programmed. So, you may not need it.</p>
<p>Thanks,<br />Tom Catalino</p>