From 5e54c59f95b80ff860fe605c56e99b1ff2ba706e Mon Sep 17 00:00:00 2001 From: dan Date: Thu, 24 Oct 2013 10:27:44 -0600 Subject: [PATCH] sent to criticallink for review --- arch/arm/mach-omap2/baseboard-mityarm335x-devkit.c | 867 +++++---- arch/arm/mach-omap2/board-mityarm335x.c | 624 +++--- arch/arm/mach-omap2/devices.c | 1943 +++++++++--------- arch/arm/mach-omap2/mux33xx.c | 1170 +++++------ drivers/net/cpsw.c | 2056 ++++++++++---------- 5 files changed, 3356 insertions(+), 3304 deletions(-) diff --git a/arch/arm/mach-omap2/baseboard-mityarm335x-devkit.c b/arch/arm/mach-omap2/baseboard-mityarm335x-devkit.c index 059fdaf..4d88a21 100644 --- a/arch/arm/mach-omap2/baseboard-mityarm335x-devkit.c +++ b/arch/arm/mach-omap2/baseboard-mityarm335x-devkit.c @@ -42,34 +42,34 @@ /* Vitesse 8601 register defs we need... */ #define VSC8601_PHY_ID (0x00070420) #define VSC8601_PHY_MASK (0xFFFFFFFC) -#define MII_EXTPAGE (0x1F) -#define RGMII_SKEW (0x1C) +#define MII_EXTPAGE (0x1F) +#define RGMII_SKEW (0x1C) #define MITY335X_DK_SPIBUS_TS (1) /* TODO - refactor all the pinmux stuff for all board files to use */ #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) -#define MITY335X_DK_GPIO_TS_IRQ_N GPIO_TO_PIN(0,20) -#define MITY335X_DK_GPIO_BACKLIGHT GPIO_TO_PIN(3,14) +#define MITY335X_DK_GPIO_TS_IRQ_N GPIO_TO_PIN(0,20) +#define MITY335X_DK_GPIO_BACKLIGHT GPIO_TO_PIN(3,14) #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ - defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) + defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) #define TS_USE_SPI 0 /*1 -- currently not supported*/ #else #define TS_USE_SPI 0 #endif struct pinmux_config { - const char *muxname; - int val; + const char *muxname; + int val; }; #define setup_pin_mux(pin_mux) \ { \ - int i = 0; \ - for (; pin_mux[i].muxname != NULL; i++) \ - omap_mux_init_signal(pin_mux[i].muxname, pin_mux[i].val); \ + int i = 0; \ + for (; pin_mux[i].muxname != NULL; i++) \ + omap_mux_init_signal(pin_mux[i].muxname, pin_mux[i].val); \ } /****************************************************************************** @@ -80,466 +80,493 @@ struct pinmux_config { * *****************************************************************************/ +static struct pinmux_config rmii2_pin_mux[] = { + {"gpmc_csn3.rmii2_crs_dv", AM33XX_PIN_INPUT_PULLUP}, +// {"gpmc_wait0.rmii2_crs_dv", AM33XX_PIN_INPUT_PULLUP}, + {"gpmc_a0.rmii2_txen", AM33XX_PIN_OUTPUT}, // -- + {"gpmc_a5.rmii2_txd0", AM33XX_PIN_OUTPUT}, // -- + {"gpmc_a4.rmii2_txd1", AM33XX_PIN_OUTPUT}, // --- + {"gpmc_a11.rmii2_rxd0", AM33XX_PIN_INPUT_PULLDOWN}, // -- + {"gpmc_a10.rmii2_rxd1", AM33XX_PIN_INPUT_PULLDOWN}, // -- + {"mii1_col.rmii2_refclk", AM33XX_PIN_INPUT_PULLDOWN}, // -- + {"mdio_data.mdio_data", AM33XX_PIN_INPUT_PULLUP}, + {"mdio_clk.mdio_clk", AM33XX_PIN_OUTPUT_PULLUP}, + {NULL, 0} +}; static struct pinmux_config rgmii2_pin_mux[] = { - {"gpmc_a0.rgmii2_tctl", AM33XX_PIN_OUTPUT}, - {"gpmc_a1.rgmii2_rctl", AM33XX_PIN_INPUT_PULLDOWN}, - {"gpmc_a2.rgmii2_td3", AM33XX_PIN_OUTPUT}, - {"gpmc_a3.rgmii2_td2", AM33XX_PIN_OUTPUT}, - {"gpmc_a4.rgmii2_td1", AM33XX_PIN_OUTPUT}, - {"gpmc_a5.rgmii2_td0", AM33XX_PIN_OUTPUT}, - {"gpmc_a6.rgmii2_tclk", AM33XX_PIN_OUTPUT}, - {"gpmc_a7.rgmii2_rclk", AM33XX_PIN_INPUT_PULLDOWN}, - {"gpmc_a8.rgmii2_rd3", AM33XX_PIN_INPUT_PULLDOWN}, - {"gpmc_a9.rgmii2_rd2", AM33XX_PIN_INPUT_PULLDOWN}, - {"gpmc_a10.rgmii2_rd1", AM33XX_PIN_INPUT_PULLDOWN}, - {"gpmc_a11.rgmii2_rd0", AM33XX_PIN_INPUT_PULLDOWN}, - {"mdio_data.mdio_data", AM33XX_PIN_INPUT_PULLUP}, - {"mdio_clk.mdio_clk", AM33XX_PIN_OUTPUT_PULLUP}, - {NULL, 0} + {"gpmc_a0.rgmii2_tctl", AM33XX_PIN_OUTPUT}, + {"gpmc_a1.rgmii2_rctl", AM33XX_PIN_INPUT_PULLDOWN}, + {"gpmc_a2.rgmii2_td3", AM33XX_PIN_OUTPUT}, + {"gpmc_a3.rgmii2_td2", AM33XX_PIN_OUTPUT}, + {"gpmc_a4.rgmii2_td1", AM33XX_PIN_OUTPUT}, + {"gpmc_a5.rgmii2_td0", AM33XX_PIN_OUTPUT}, + {"gpmc_a6.rgmii2_tclk", AM33XX_PIN_OUTPUT}, + {"gpmc_a7.rgmii2_rclk", AM33XX_PIN_INPUT_PULLDOWN}, + {"gpmc_a8.rgmii2_rd3", AM33XX_PIN_INPUT_PULLDOWN}, + {"gpmc_a9.rgmii2_rd2", AM33XX_PIN_INPUT_PULLDOWN}, + {"gpmc_a10.rgmii2_rd1", AM33XX_PIN_INPUT_PULLDOWN}, + {"gpmc_a11.rgmii2_rd0", AM33XX_PIN_INPUT_PULLDOWN}, + {"mdio_data.mdio_data", AM33XX_PIN_INPUT_PULLUP}, + {"mdio_clk.mdio_clk", AM33XX_PIN_OUTPUT_PULLUP}, + {NULL, 0} }; static struct pinmux_config lcdc_pin_mux[] = { - {"lcd_data0.lcd_data0", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, - {"lcd_data1.lcd_data1", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, - {"lcd_data2.lcd_data2", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, - {"lcd_data3.lcd_data3", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, - {"lcd_data4.lcd_data4", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, - {"lcd_data5.lcd_data5", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, - {"lcd_data6.lcd_data6", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, - {"lcd_data7.lcd_data7", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, - {"lcd_data8.lcd_data8", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, - {"lcd_data9.lcd_data9", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, - {"lcd_data10.lcd_data10", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, - {"lcd_data11.lcd_data11", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, - {"lcd_data12.lcd_data12", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, - {"lcd_data13.lcd_data13", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, - {"lcd_data14.lcd_data14", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, - {"lcd_data15.lcd_data15", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, - {"lcd_vsync.lcd_vsync", AM33XX_PIN_OUTPUT}, - {"lcd_hsync.lcd_hsync", AM33XX_PIN_OUTPUT}, - {"lcd_pclk.lcd_pclk", AM33XX_PIN_OUTPUT}, - {"lcd_ac_bias_en.lcd_ac_bias_en", AM33XX_PIN_OUTPUT}, - /* GPIO for the backlight */ - { "mcasp0_aclkx.gpio3_14", AM33XX_PIN_OUTPUT}, - {NULL, 0} + #if 0 //danm + {"lcd_data0.lcd_data0", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, + {"lcd_data1.lcd_data1", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, + {"lcd_data2.lcd_data2", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, + {"lcd_data3.lcd_data3", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, + {"lcd_data4.lcd_data4", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, + {"lcd_data5.lcd_data5", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, + {"lcd_data6.lcd_data6", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, + {"lcd_data7.lcd_data7", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, + {"lcd_data8.lcd_data8", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, + {"lcd_data9.lcd_data9", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, + {"lcd_data10.lcd_data10", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, + {"lcd_data11.lcd_data11", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, + {"lcd_data12.lcd_data12", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, + {"lcd_data13.lcd_data13", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, + {"lcd_data14.lcd_data14", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, + {"lcd_data15.lcd_data15", AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, + {"lcd_vsync.lcd_vsync", AM33XX_PIN_OUTPUT}, + {"lcd_hsync.lcd_hsync", AM33XX_PIN_OUTPUT}, + {"lcd_pclk.lcd_pclk", AM33XX_PIN_OUTPUT}, + {"lcd_ac_bias_en.lcd_ac_bias_en", AM33XX_PIN_OUTPUT}, + /* GPIO for the backlight */ + { "mcasp0_aclkx.gpio3_14", AM33XX_PIN_OUTPUT}, + #endif + {NULL, 0} }; static struct pinmux_config mmc0_pin_mux[] = { - {"mmc0_dat3.mmc0_dat3", AM33XX_PIN_INPUT_PULLUP}, - {"mmc0_dat2.mmc0_dat2", AM33XX_PIN_INPUT_PULLUP}, - {"mmc0_dat1.mmc0_dat1", AM33XX_PIN_INPUT_PULLUP}, - {"mmc0_dat0.mmc0_dat0", AM33XX_PIN_INPUT_PULLUP}, - {"mmc0_clk.mmc0_clk", AM33XX_PIN_INPUT_PULLUP}, - {"mmc0_cmd.mmc0_cmd", AM33XX_PIN_INPUT_PULLUP}, - {"mii1_txen.gpio3_3", AM33XX_PIN_INPUT_PULLUP}, /* SD Card Detect */ - {"mii1_col.gpio3_0", AM33XX_PIN_INPUT_PULLUP}, /* SD Write Protect */ - {NULL, 0} + {"mmc0_dat3.mmc0_dat3", AM33XX_PIN_INPUT_PULLUP}, + {"mmc0_dat2.mmc0_dat2", AM33XX_PIN_INPUT_PULLUP}, + {"mmc0_dat1.mmc0_dat1", AM33XX_PIN_INPUT_PULLUP}, + {"mmc0_dat0.mmc0_dat0", AM33XX_PIN_INPUT_PULLUP}, + {"mmc0_clk.mmc0_clk", AM33XX_PIN_INPUT_PULLUP}, + {"mmc0_cmd.mmc0_cmd", AM33XX_PIN_INPUT_PULLUP}, + // danm {"mii1_txen.gpio3_3", AM33XX_PIN_INPUT_PULLUP}, /* SD Card Detect */ +// {"mii1_col.gpio3_0", AM33XX_PIN_INPUT_PULLUP}, /* SD Write Protect */ + {NULL, 0} }; /** * Expansion connector pins for SDIO - * Pin WifiJ1 DevJ700 335X PIN/Function - * 1 SDIO_D3 GPMC_AD15 GPMC_AD15/MMC2_DAT3 - * 3 SDIO_D2 GPMC_AD14 GPMC_AD14/MMC2_DAT2 - * 5 SDIO_D1 GPMC_AD13 GPMC_AD13/MMC2_DAT1 - * 7 SDIO_D0 GPMC_AD12 GPMC_AD12/MMC2_DAT0 - * 9 RESET GPMC_AD11 GPMC_AD11/GPIO2_27 - * 22 SDIO_CMD GPMC_CS3_N GPMC_CSN3/MMC2_CMD - * 30 SDIO_CLK GPMC_CLK GPMC_CLK/MMC2_CLK + * Pin WifiJ1 DevJ700 335X PIN/Function + * 1 SDIO_D3 GPMC_AD15 GPMC_AD15/MMC2_DAT3 + * 3 SDIO_D2 GPMC_AD14 GPMC_AD14/MMC2_DAT2 + * 5 SDIO_D1 GPMC_AD13 GPMC_AD13/MMC2_DAT1 + * 7 SDIO_D0 GPMC_AD12 GPMC_AD12/MMC2_DAT0 + * 9 RESET GPMC_AD11 GPMC_AD11/GPIO2_27 + * 22 SDIO_CMD GPMC_CS3_N GPMC_CSN3/MMC2_CMD + * 30 SDIO_CLK GPMC_CLK GPMC_CLK/MMC2_CLK */ static struct pinmux_config mmc2_pin_mux[] = { - {"gpmc_ad15.mmc2_dat3", AM33XX_PIN_INPUT_PULLUP}, - {"gpmc_ad14.mmc2_dat2", AM33XX_PIN_INPUT_PULLUP}, - {"gpmc_ad13.mmc2_dat1", AM33XX_PIN_INPUT_PULLUP}, - {"gpmc_ad12.mmc2_dat0", AM33XX_PIN_INPUT_PULLUP}, - {"gpmc_clk.mmc2_clk", AM33XX_PIN_INPUT_PULLUP}, - {"gpmc_csn3.mmc2_cmd", AM33XX_PIN_INPUT_PULLUP}, - {NULL, 0} + {"gpmc_ad15.mmc2_dat3", AM33XX_PIN_INPUT_PULLUP}, + {"gpmc_ad14.mmc2_dat2", AM33XX_PIN_INPUT_PULLUP}, + {"gpmc_ad13.mmc2_dat1", AM33XX_PIN_INPUT_PULLUP}, + {"gpmc_ad12.mmc2_dat0", AM33XX_PIN_INPUT_PULLUP}, + {"gpmc_clk.mmc2_clk", AM33XX_PIN_INPUT_PULLUP}, + {"gpmc_csn3.mmc2_cmd", AM33XX_PIN_INPUT_PULLUP}, + {NULL, 0} }; static struct pinmux_config can_pin_mux[] = { - {"uart1_rxd.d_can1_tx", AM33XX_PULL_ENBL}, - {"uart1_txd.d_can1_rx", AM33XX_PIN_INPUT_PULLUP}, - {"mii1_txd3.d_can0_tx", AM33XX_PULL_ENBL}, - {"mii1_txd2.d_can0_rx", AM33XX_PIN_INPUT_PULLUP}, - {NULL, 0} + {"uart1_rxd.d_can1_tx", AM33XX_PULL_ENBL}, + {"uart1_txd.d_can1_rx", AM33XX_PIN_INPUT_PULLUP}, + {"mii1_txd3.d_can0_tx", AM33XX_PULL_ENBL}, + {"mii1_txd2.d_can0_rx", AM33XX_PIN_INPUT_PULLUP}, + {NULL, 0} }; static struct pinmux_config expansion_pin_mux[] = { - {"uart0_ctsn.uart4_rxd", AM33XX_PIN_INPUT_PULLUP},/* Exp0 RX */ - {"uart0_rtsn.uart4_txd", AM33XX_PULL_ENBL}, /* Exp0 TX */ - {"mii1_rxd3.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},/* Exp1 RX */ - {"mii1_rxd2.uart3_txd", AM33XX_PULL_ENBL}, /* Exp1 TX */ - {"mii1_rxd1.gpio2_20", AM33XX_PULL_ENBL}, /* Exp1 TX EN */ - {"mii1_txclk.gpio3_9", AM33XX_PULL_ENBL}, /* Exp0 TX EN */ - {NULL, 0} + {"uart1_rxd.uart1_rxd", AM33XX_PIN_INPUT_PULLUP},/* Exp0 RX */ + {"uart1_txd.uart1_txd", AM33XX_PULL_ENBL}, /* Exp0 TX */ + {"mii1_rxd3.uart1_dtrn", AM33XX_PULL_ENBL}, /* uart 1 modem */ + {"mii1_rxclk..uart1_dsrn", AM33XX_PULL_ENBL}, /* */ + {"mii1_txclk.uart1_dcdn", AM33XX_PULL_ENBL}, /* */ + + {"spi0_sclk.uart2_rxd", AM33XX_PIN_INPUT_PULLUP},/* Exp0 RX */ + {"spi0_d0.uart2_txd", AM33XX_PULL_ENBL}, /* Exp0 TX */ + + {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},/*- Exp0 RX */ + {"mii1_rxd2.uart3_txd", AM33XX_PULL_ENBL}, /* - Exp0 TX */ + + {"mii1_txd3.uart4_rxd", AM33XX_PIN_INPUT_PULLUP},/* - Exp0 RX */ + {"mii1_txd2.uart4_txd", AM33XX_PULL_ENBL}, /* Exp0 TX */ + + {"lcd_data9.uart5_rxd", AM33XX_PIN_INPUT_PULLUP},/*- Exp0 RX */ + {"lcd_data8.uart5_txd", AM33XX_PULL_ENBL}, /*- Exp0 TX */ + {NULL, 0} }; + static struct pinmux_config usb_pin_mux[] = { - {"usb0_drvvbus.usb0_drvvbus", AM33XX_PIN_OUTPUT}, - {"usb1_drvvbus.usb1_drvvbus", AM33XX_PIN_OUTPUT}, - {NULL, 0} + {"usb0_drvvbus.usb0_drvvbus", AM33XX_PIN_OUTPUT}, + {"usb1_drvvbus.usb1_drvvbus", AM33XX_PIN_OUTPUT}, + {NULL, 0} }; #if (TS_USE_SPI) static struct pinmux_config ts_pin_mux[] = { - /* SPI0 CS0 taken care of by SPI pinmux setup */ - {"xdma_event_intr1.gpio0_20", AM33XX_PIN_INPUT}, /* Pen down */ - {"xdma_event_intr0.gpio0_19", AM33XX_PIN_INPUT}, /* 7843 busy (not used)*/ - {NULL, 0} + /* SPI0 CS0 taken care of by SPI pinmux setup */ + {"xdma_event_intr1.gpio0_20", AM33XX_PIN_INPUT}, /* Pen down */ + {"xdma_event_intr0.gpio0_19", AM33XX_PIN_INPUT}, /* 7843 busy (not used)*/ + {NULL, 0} }; #endif /* Module pin mux for mcasp1 */ static struct pinmux_config mcasp1_pin_mux[] = { - {"mcasp0_aclkr.mcasp1_aclkx", AM33XX_PIN_INPUT_PULLDOWN}, - {"mcasp0_fsr.mcasp1_fsx", AM33XX_PIN_INPUT_PULLDOWN}, - {"mcasp0_axr1.mcasp1_axr0", AM33XX_PIN_OUTPUT}, - {"mcasp0_ahclkx.mcasp1_axr1", AM33XX_PIN_INPUT_PULLDOWN}, - {"mii1_rxd0.mcasp1_ahclkr", AM33XX_PIN_INPUT_PULLDOWN}, - {"rmii1_refclk.mcasp1_ahclkx", AM33XX_PIN_INPUT_PULLDOWN}, - {NULL, 0}, + {"mcasp0_aclkr.mcasp1_aclkx", AM33XX_PIN_INPUT_PULLDOWN}, + {"mcasp0_fsr.mcasp1_fsx", AM33XX_PIN_INPUT_PULLDOWN}, + {"mcasp0_axr1.mcasp1_axr0", AM33XX_PIN_OUTPUT}, + {"mcasp0_ahclkx.mcasp1_axr1", AM33XX_PIN_INPUT_PULLDOWN}, + {"mii1_rxd0.mcasp1_ahclkr", AM33XX_PIN_INPUT_PULLDOWN}, + {"rmii1_refclk.mcasp1_ahclkx", AM33XX_PIN_INPUT_PULLDOWN}, + {NULL, 0}, }; static struct pinmux_config i2c0_pin_mux[] = { - {"i2c0_sda.i2c0_sda", AM33XX_SLEWCTRL_SLOW | AM33XX_PULL_ENBL | - AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT}, - {"i2c0_scl.i2c0_scl", AM33XX_SLEWCTRL_SLOW | AM33XX_PULL_ENBL | - AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT}, - {NULL, 0}, + {"i2c0_sda.i2c0_sda", AM33XX_SLEWCTRL_SLOW | AM33XX_PULL_ENBL | + AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT}, + {"i2c0_scl.i2c0_scl", AM33XX_SLEWCTRL_SLOW | AM33XX_PULL_ENBL | + AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT}, + {NULL, 0}, }; static struct pinmux_config spi0_pin_mux[] = { - {"spi0_cs0.spi0_cs0", AM33XX_PIN_OUTPUT_PULLUP}, - {"spi0_cs1.spi0_cs1", AM33XX_PIN_OUTPUT_PULLUP}, - {"spi0_sclk.spi0_sclk", AM33XX_PIN_OUTPUT_PULLUP}, - {"spi0_d0.spi0_d0", AM33XX_PIN_OUTPUT}, - {"spi0_d1.spi0_d1", AM33XX_PULL_ENBL | AM33XX_INPUT_EN}, - {NULL, 0}, + {"spi0_cs0.spi0_cs0", AM33XX_PIN_OUTPUT_PULLUP}, + {"spi0_cs1.spi0_cs1", AM33XX_PIN_OUTPUT_PULLUP}, + {"spi0_sclk.spi0_sclk", AM33XX_PIN_OUTPUT_PULLUP}, + {"spi0_d0.spi0_d0", AM33XX_PIN_OUTPUT}, + {"spi0_d1.spi0_d1", AM33XX_PULL_ENBL | AM33XX_INPUT_EN}, + {NULL, 0}, }; static struct pinmux_config tsc_pin_mux[] = { - {"ain0.ain0", AM33XX_INPUT_EN}, - {"ain1.ain1", AM33XX_INPUT_EN}, - {"ain2.ain2", AM33XX_INPUT_EN}, - {"ain3.ain3", AM33XX_INPUT_EN}, - {"vrefp.vrefp", AM33XX_INPUT_EN}, - {"vrefn.vrefn", AM33XX_INPUT_EN}, - {NULL, 0}, + {"ain0.ain0", AM33XX_INPUT_EN}, + {"ain1.ain1", AM33XX_INPUT_EN}, + {"ain2.ain2", AM33XX_INPUT_EN}, + {"ain3.ain3", AM33XX_INPUT_EN}, + {"vrefp.vrefp", AM33XX_INPUT_EN}, + {"vrefn.vrefn", AM33XX_INPUT_EN}, + {NULL, 0}, }; static struct pinmux_config wl12xx_pin_mux[] = { - {"gpmc_ad10.gpio0_26", AM33XX_PIN_INPUT}, /* WL WL IRQ */ - {"gpmc_ad11.gpio0_27", AM33XX_PIN_INPUT}, /* WL SPI I/O RST */ - {"gpmc_csn1.gpio1_30", AM33XX_PIN_INPUT_PULLUP}, /* WL IRQ */ - {"gpmc_csn2.gpio1_31", AM33XX_PIN_OUTPUT}, /* BT RST ?*/ - {NULL, 0}, + {"gpmc_ad10.gpio0_26", AM33XX_PIN_INPUT}, /* WL WL IRQ */ + {"gpmc_ad11.gpio0_27", AM33XX_PIN_INPUT}, /* WL SPI I/O RST */ + {"gpmc_csn1.gpio1_30", AM33XX_PIN_INPUT_PULLUP}, /* WL IRQ */ + {"gpmc_csn2.gpio1_31", AM33XX_PIN_OUTPUT}, /* BT RST ?*/ + {NULL, 0}, }; -#define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(0, 26) +#define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(0, 26) struct wl12xx_platform_data am335x_wlan_data = { - .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO), - .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */ + .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO), + .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */ }; static struct omap2_hsmmc_info mmc_info[] __initdata = { - { - .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA, - .gpio_cd = GPIO_TO_PIN(3, 3), - .gpio_wp = GPIO_TO_PIN(3, 0), - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - }, - { - .mmc = 0, /* will be set at runtime */ - }, - { - .mmc = 0, /* will be set at runtime */ - }, - {} /* Terminator */ - }; + { + .mmc = 1, + .caps = MMC_CAP_4_BIT_DATA, + .gpio_cd = -EINVAL, // GPIO_TO_PIN(3, 3), + .gpio_wp = -EINVAL, //GPIO_TO_PIN(3, 0), + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + }, + { + .mmc = 0, /* will be set at runtime */ + }, + { + .mmc = 0, /* will be set at runtime */ + }, + {} /* Terminator */ + }; static __init void baseboard_setup_expansion(void) { - setup_pin_mux(expansion_pin_mux); + setup_pin_mux(expansion_pin_mux); } static __init void baseboard_setup_can(void) { - setup_pin_mux(can_pin_mux); + setup_pin_mux(can_pin_mux); - am33xx_d_can_init(0); - am33xx_d_can_init(1); + am33xx_d_can_init(0); + am33xx_d_can_init(1); } static struct omap_musb_board_data board_data = { - .interface_type = MUSB_INTERFACE_ULPI, - .mode = MUSB_OTG, - .power = 500, - .instances = 1, + .interface_type = MUSB_INTERFACE_ULPI, + .mode = MUSB_OTG, + .power = 500, + .instances = 1, }; static __init void baseboard_setup_usb(void) { - setup_pin_mux(usb_pin_mux); - usb_musb_init(&board_data); + setup_pin_mux(usb_pin_mux); + usb_musb_init(&board_data); } static __init void baseboard_setup_mmc(void) { - /* pin mux */ - setup_pin_mux(mmc0_pin_mux); + /* pin mux */ + setup_pin_mux(mmc0_pin_mux); - /* configure mmc */ - omap2_hsmmc_init(mmc_info); + /* configure mmc */ + omap2_hsmmc_init(mmc_info); } static const struct display_panel disp_panel = { - WVGA, /* panel_type */ - 32, /* max_bpp */ - 16, /* min_bpp */ - COLOR_ACTIVE, /* panel_shade */ + WVGA, /* panel_type */ + 32, /* max_bpp */ + 16, /* min_bpp */ + COLOR_ACTIVE, /* panel_shade */ }; static struct lcd_ctrl_config dvi_cfg = { - .p_disp_panel = &disp_panel, - .ac_bias = 255, - .ac_bias_intrpt = 0, - .dma_burst_sz = 16, - .bpp = 16, - .fdd = 0x80, - .tft_alt_mode = 0, - .stn_565_mode = 0, - .mono_8bit_mode = 0, - .invert_line_clock = 1, - .invert_frm_clock = 1, - .sync_edge = 0, - .sync_ctrl = 1, - .raster_order = 0, + .p_disp_panel = &disp_panel, + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 16, + .fdd = 0x80, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, }; /* TODO - should really update driver to support VESA mode timings... */ struct da8xx_lcdc_platform_data dvi_pdata = { - .manu_name = "VESA", - .controller_data = &dvi_cfg, - .type = "800x600", + .manu_name = "VESA", + .controller_data = &dvi_cfg, + .type = "800x600", }; #ifdef CONFIG_BACKLIGHT_TPS6116X static struct platform_device tps6116x_device = { - .name = "tps6116x", - .id = -1, - .dev = { - .platform_data = (void*)MITY335X_DK_GPIO_BACKLIGHT, - }, + .name = "tps6116x", + .id = -1, + .dev = { + .platform_data = (void*)MITY335X_DK_GPIO_BACKLIGHT, + }, }; #endif /* CONFIG_BACKLIGHT_TPS6116X */ #if (TS_USE_SPI) static struct ads7846_platform_data ads7846_config = { - .model = 7843, - .vref_mv = 3300, - .x_max = 0x0fff, - .y_max = 0x0fff, - .x_plate_ohms = 180, - .pressure_max = 255, - .debounce_max = 0, //200, - .debounce_tol = 5, - .debounce_rep = 10, - .gpio_pendown = MITY335X_DK_GPIO_TS_IRQ_N, - .keep_vref_on = 1, - .irq_flags = IRQF_TRIGGER_FALLING, - .vref_delay_usecs = 100, - .settle_delay_usecs = 200, - .penirq_recheck_delay_usecs = 1000, - .filter_init = 0, - .filter = 0, - .filter_cleanup = 0, - .gpio_pendown = MITY335X_DK_GPIO_TS_IRQ_N, + .model = 7843, + .vref_mv = 3300, + .x_max = 0x0fff, + .y_max = 0x0fff, + .x_plate_ohms = 180, + .pressure_max = 255, + .debounce_max = 0, //200, + .debounce_tol = 5, + .debounce_rep = 10, + .gpio_pendown = MITY335X_DK_GPIO_TS_IRQ_N, + .keep_vref_on = 1, + .irq_flags = IRQF_TRIGGER_FALLING, + .vref_delay_usecs = 100, + .settle_delay_usecs = 200, + .penirq_recheck_delay_usecs = 1000, + .filter_init = 0, + .filter = 0, + .filter_cleanup = 0, + .gpio_pendown = MITY335X_DK_GPIO_TS_IRQ_N, }; static __init void baseboard_setup_ts(void) { - setup_pin_mux(ts_pin_mux); - /* SPI hookup already done by baseboard_setup_spi0() */ + setup_pin_mux(ts_pin_mux); + /* SPI hookup already done by baseboard_setup_spi0() */ } #else static struct resource tsc_resources[] = { - [0] = { - .start = AM33XX_TSC_BASE, - .end = AM33XX_TSC_BASE + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AM33XX_IRQ_ADC_GEN, - .end = AM33XX_IRQ_ADC_GEN, - .flags = IORESOURCE_IRQ, - }, + [0] = { + .start = AM33XX_TSC_BASE, + .end = AM33XX_TSC_BASE + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AM33XX_IRQ_ADC_GEN, + .end = AM33XX_IRQ_ADC_GEN, + .flags = IORESOURCE_IRQ, + }, }; static struct tsc_data am335x_touchscreen_data = { - .wires = 4, - .analog_input = 1, - .x_plate_resistance = 200, + .wires = 4, + .analog_input = 1, + .x_plate_resistance = 200, }; static struct platform_device tsc_device = { - .name = "tsc", - .id = -1, - .dev = { - .platform_data = &am335x_touchscreen_data, - }, - .num_resources = ARRAY_SIZE(tsc_resources), - .resource = tsc_resources, + .name = "tsc", + .id = -1, + .dev = { + .platform_data = &am335x_touchscreen_data, + }, + .num_resources = ARRAY_SIZE(tsc_resources), + .resource = tsc_resources, }; static __init void baseboard_setup_ts(void) { - int err; + int err; - setup_pin_mux(tsc_pin_mux); - err = platform_device_register(&tsc_device); - if (err) - pr_err("failed to register touchscreen device\n"); + setup_pin_mux(tsc_pin_mux); + err = platform_device_register(&tsc_device); + if (err) + pr_err("failed to register touchscreen device\n"); } #endif /* CONFIG_TOUCHSCREEN_ADS7846 */ static __init void baseboard_setup_dvi(void) { - struct clk *disp_pll; + struct clk *disp_pll; - /* pinmux */ - setup_pin_mux(lcdc_pin_mux); + /* pinmux */ + setup_pin_mux(lcdc_pin_mux); - /* add I2C1 device entry */ + /* add I2C1 device entry */ - /* TODO - really need to modify da8xx driver to support mating to the - * TFP410 and tweaking settings at the driver level... need to stew on - * this.. - */ + /* TODO - really need to modify da8xx driver to support mating to the + * TFP410 and tweaking settings at the driver level... need to stew on + * this.. + */ - /* configure / enable LCDC */ - disp_pll = clk_get(NULL, "dpll_disp_ck"); - if (IS_ERR(disp_pll)) { - pr_err("Connect get disp_pll\n"); - return; - } + /* configure / enable LCDC */ + disp_pll = clk_get(NULL, "dpll_disp_ck"); + if (IS_ERR(disp_pll)) { + pr_err("Connect get disp_pll\n"); + return; + } - if (clk_set_rate(disp_pll, 300000000)) { - pr_warning("%s: Unable to initialize display PLL.\n", - __func__); - goto out; - } + if (clk_set_rate(disp_pll, 300000000)) { + pr_warning("%s: Unable to initialize display PLL.\n", + __func__); + goto out; + } - if (am33xx_register_lcdc(&dvi_pdata)) - pr_warning("%s: Unable to register LCDC device.\n", - __func__); + if (am33xx_register_lcdc(&dvi_pdata)) + pr_warning("%s: Unable to register LCDC device.\n", + __func__); #ifdef CONFIG_BACKLIGHT_TPS6116X - if (platform_device_register(&tps6116x_device)) - pr_err("failed to register backlight device\n"); + if (platform_device_register(&tps6116x_device)) + pr_err("failed to register backlight device\n"); #else - /* backlight */ - /* TEMPORARY until driver is ready... just jam it on! */ - if(0 != gpio_request(MITY335X_DK_GPIO_BACKLIGHT, "backlight control")) { - pr_warning("Unable to request GPIO %d\n",MITY335X_DK_GPIO_BACKLIGHT); - goto out; - } - if(0 != gpio_direction_output(MITY335X_DK_GPIO_BACKLIGHT, 1) ){ - pr_warning("Unable to set backlight GPIO %d ON\n", - MITY335X_DK_GPIO_BACKLIGHT); - goto out; - } else { - pr_info("Backlight GPIO = %d\n", MITY335X_DK_GPIO_BACKLIGHT); - } + /* backlight */ + /* TEMPORARY until driver is ready... just jam it on! */ + if(0 != gpio_request(MITY335X_DK_GPIO_BACKLIGHT, "backlight control")) { + pr_warning("Unable to request GPIO %d\n",MITY335X_DK_GPIO_BACKLIGHT); + goto out; + } + if(0 != gpio_direction_output(MITY335X_DK_GPIO_BACKLIGHT, 1) ){ + pr_warning("Unable to set backlight GPIO %d ON\n", + MITY335X_DK_GPIO_BACKLIGHT); + goto out; + } else { + pr_info("Backlight GPIO = %d\n", MITY335X_DK_GPIO_BACKLIGHT); + } #endif // CONFIG_BACKLIGHT_TPS6116X out: - clk_put(disp_pll); + clk_put(disp_pll); } static u8 am335x_iis_serializer_direction[] = { - TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE, - INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, - INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, - INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, }; static struct snd_platform_data baseboard_snd_data = { - .tx_dma_offset = 0x46400000, /* McASP1 */ - .rx_dma_offset = 0x46400000, - .op_mode = DAVINCI_MCASP_IIS_MODE, - .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction), - .tdm_slots = 2, - .serial_dir = am335x_iis_serializer_direction, - .asp_chan_q = EVENTQ_2, - .version = MCASP_VERSION_3, - .txnumevt = 1, - .rxnumevt = 1, + .tx_dma_offset = 0x46400000, /* McASP1 */ + .rx_dma_offset = 0x46400000, + .op_mode = DAVINCI_MCASP_IIS_MODE, + .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction), + .tdm_slots = 2, + .serial_dir = am335x_iis_serializer_direction, + .asp_chan_q = EVENTQ_2, + .version = MCASP_VERSION_3, + .txnumevt = 1, + .rxnumevt = 1, }; static struct omap2_mcspi_device_config spi0_ctlr_data = { - .turbo_mode = 0, /* diable "turbo" mode */ - .single_channel = 1, /* 0: slave, 1: master */ - .d0_is_mosi = 1, /* D0 is output from 3335X */ + .turbo_mode = 0, /* diable "turbo" mode */ + .single_channel = 1, /* 0: slave, 1: master */ + .d0_is_mosi = 1, /* D0 is output from 3335X */ }; static struct spi_board_info baseboard_spi0_slave_info[] = { - { - .modalias = "tlv320aic26-codec", - .controller_data = &spi0_ctlr_data, - .irq = -1, - .max_speed_hz = 2000000, - .bus_num = 1, - .chip_select = 1, - .mode = SPI_MODE_1, - }, + { + .modalias = "tlv320aic26-codec", + .controller_data = &spi0_ctlr_data, + .irq = -1, + .max_speed_hz = 2000000, + .bus_num = 1, + .chip_select = 1, + .mode = SPI_MODE_1, + }, #if (TS_USE_SPI) - { - .modalias = "ads7846", - .bus_num = MITY335X_DK_SPIBUS_TS, - .chip_select = 0, - .max_speed_hz = 1500000, - .controller_data = &spi0_ctlr_data, - .irq = OMAP_GPIO_IRQ(MITY335X_DK_GPIO_TS_IRQ_N), - .platform_data = &ads7846_config, - } + { + .modalias = "ads7846", + .bus_num = MITY335X_DK_SPIBUS_TS, + .chip_select = 0, + .max_speed_hz = 1500000, + .controller_data = &spi0_ctlr_data, + .irq = OMAP_GPIO_IRQ(MITY335X_DK_GPIO_TS_IRQ_N), + .platform_data = &ads7846_config, + } #endif /* TS_USE_SPI */ }; static __init void baseboard_setup_audio(void) { - pr_info("Configuring audio...\n"); - setup_pin_mux(mcasp1_pin_mux); - am335x_register_mcasp1(&baseboard_snd_data); + pr_info("Configuring audio...\n"); + setup_pin_mux(mcasp1_pin_mux); + am335x_register_mcasp1(&baseboard_snd_data); } static __init void baseboard_setup_spi0_devices(void) { - setup_pin_mux(spi0_pin_mux); - spi_register_board_info(baseboard_spi0_slave_info, - ARRAY_SIZE(baseboard_spi0_slave_info)); + setup_pin_mux(spi0_pin_mux); + spi_register_board_info(baseboard_spi0_slave_info, + ARRAY_SIZE(baseboard_spi0_slave_info)); - baseboard_setup_audio(); - baseboard_setup_ts(); + baseboard_setup_audio(); + baseboard_setup_ts(); } static void __init baseboard_i2c0_init(void) { - setup_pin_mux(i2c0_pin_mux); - omap_register_i2c_bus(1, 100, NULL, 0); + setup_pin_mux(i2c0_pin_mux); + omap_register_i2c_bus(1, 100, NULL, 0); } /* fixup for the Vitesse 8601 PHY on the MityARM335x dev kit. @@ -547,47 +574,47 @@ static void __init baseboard_i2c0_init(void) */ static int am335x_vsc8601_phy_fixup(struct phy_device *phydev) { - unsigned int val; - - pr_info("am335x_vsc8601_phy_fixup %x here addr = %d\n", - phydev->phy_id, phydev->addr); - - /* skew control is in extended register set */ - if (phy_write(phydev, MII_EXTPAGE, 1) < 0) { - pr_err("Error enabling extended PHY regs\n"); - return 1; - } - /* read the skew */ - val = phy_read(phydev, RGMII_SKEW); - if (val < 0) { - pr_err("Error reading RGMII skew reg\n"); - return val; - } - val &= 0x0FFF; /* clear skew values */ - val |= 0x3000; /* 0 Tx skew, 2.0ns Rx skew */ - if (phy_write(phydev, RGMII_SKEW, val) < 0) { - pr_err("failed to write RGMII_SKEW\n"); - return 1; - } - /* disable the extended page access */ - if (phy_write(phydev, MII_EXTPAGE, 0) < 0) { - pr_err("Error disabling extended PHY regs\n"); - return 1; - } - return 0; + unsigned int val; + + pr_info("am335x_vsc8601_phy_fixup %x here addr = %d\n", + phydev->phy_id, phydev->addr); + + /* skew control is in extended register set */ + if (phy_write(phydev, MII_EXTPAGE, 1) < 0) { + pr_err("Error enabling extended PHY regs\n"); + return 1; + } + /* read the skew */ + val = phy_read(phydev, RGMII_SKEW); + if (val < 0) { + pr_err("Error reading RGMII skew reg\n"); + return val; + } + val &= 0x0FFF; /* clear skew values */ + val |= 0x3000; /* 0 Tx skew, 2.0ns Rx skew */ + if (phy_write(phydev, RGMII_SKEW, val) < 0) { + pr_err("failed to write RGMII_SKEW\n"); + return 1; + } + /* disable the extended page access */ + if (phy_write(phydev, MII_EXTPAGE, 0) < 0) { + pr_err("Error disabling extended PHY regs\n"); + return 1; + } + return 0; } static __init void baseboard_setup_enet(void) { - /* pinmux */ - setup_pin_mux(rgmii2_pin_mux); - - /* network configuration done in SOM code */ - /* PHY address setup? */ - /* Register PHY fixup to adjust rx clock skew */ - phy_register_fixup_for_uid(VSC8601_PHY_ID, - VSC8601_PHY_MASK, - am335x_vsc8601_phy_fixup); + /* pinmux */ + setup_pin_mux(rmii2_pin_mux); + + /* network configuration done in SOM code */ + /* PHY address setup? */ + /* Register PHY fixup to adjust rx clock skew */ + phy_register_fixup_for_uid(VSC8601_PHY_ID, + VSC8601_PHY_MASK, + am335x_vsc8601_phy_fixup); } @@ -596,126 +623,126 @@ static __init void baseboard_setup_enet(void) static void mmc2_wl12xx_init(void) { - setup_pin_mux(mmc2_pin_mux); - - mmc_info[1].mmc = 3; - mmc_info[1].name = "wl1271"; - mmc_info[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD - | MMC_PM_KEEP_POWER; - mmc_info[1].nonremovable = true; - mmc_info[1].gpio_cd = -EINVAL; - mmc_info[1].gpio_wp = -EINVAL; - mmc_info[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */ - - /* mmc will be initialized when mmc0_init is called */ - return; + setup_pin_mux(mmc2_pin_mux); + + mmc_info[1].mmc = 3; + mmc_info[1].name = "wl1271"; + mmc_info[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD + | MMC_PM_KEEP_POWER; + mmc_info[1].nonremovable = true; + mmc_info[1].gpio_cd = -EINVAL; + mmc_info[1].gpio_wp = -EINVAL; + mmc_info[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */ + + /* mmc will be initialized when mmc0_init is called */ + return; } static void wl12xx_bluetooth_enable(void) { #if 0 - int status = gpio_request(am335x_wlan_data.bt_enable_gpio, - "bt_en\n"); - if (status < 0) - pr_err("Failed to request gpio for bt_enable"); + int status = gpio_request(am335x_wlan_data.bt_enable_gpio, + "bt_en\n"); + if (status < 0) + pr_err("Failed to request gpio for bt_enable"); - pr_info("Configure Bluetooth Enable pin...\n"); - gpio_direction_output(am335x_wlan_data.bt_enable_gpio, 0); + pr_info("Configure Bluetooth Enable pin...\n"); + gpio_direction_output(am335x_wlan_data.bt_enable_gpio, 0); #else - pr_info("Bluetooth not Enabled!\n"); + pr_info("Bluetooth not Enabled!\n"); #endif } static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd) { -#if 1 /* TJI - 5/24/12 WL enable not connected yet.. always on */ - if (on) { - gpio_set_value(am335x_wlan_data.wlan_enable_gpio, 1); - mdelay(70); - } - else - gpio_set_value(am335x_wlan_data.wlan_enable_gpio, 0); +#if 1 /* TJI - 5/24/12 WL enable not connected yet.. always on */ + if (on) { + gpio_set_value(am335x_wlan_data.wlan_enable_gpio, 1); + mdelay(70); + } + else + gpio_set_value(am335x_wlan_data.wlan_enable_gpio, 0); #endif - return 0; + return 0; } static void baseboard_setup_wlan(void) { - struct device *dev; - struct omap_mmc_platform_data *pdata; - int ret; + struct device *dev; + struct omap_mmc_platform_data *pdata; + int ret; - /* Register WLAN and BT enable pins based on the evm board revision */ - am335x_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(3,4); - am335x_wlan_data.bt_enable_gpio = -EINVAL; + /* Register WLAN and BT enable pins based on the evm board revision */ + am335x_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(3,4); + am335x_wlan_data.bt_enable_gpio = -EINVAL; pr_info("WLAN GPIO Info.. IRQ = %3d WL_EN = %3d BT_EN = %3d\n", - am335x_wlan_data.irq, - am335x_wlan_data.wlan_enable_gpio, - am335x_wlan_data.bt_enable_gpio); + am335x_wlan_data.irq, + am335x_wlan_data.wlan_enable_gpio, + am335x_wlan_data.bt_enable_gpio); - wl12xx_bluetooth_enable(); - - if (wl12xx_set_platform_data(&am335x_wlan_data)) - pr_err("error setting wl12xx data\n"); - - dev = mmc_info[1].dev; - if (!dev) { - pr_err("wl12xx mmc device initialization failed\n"); - goto out; - } - - pdata = dev->platform_data; - if (!pdata) { - pr_err("Platfrom data of wl12xx device not set\n"); - goto out; - } + wl12xx_bluetooth_enable(); + + if (wl12xx_set_platform_data(&am335x_wlan_data)) + pr_err("error setting wl12xx data\n"); + + dev = mmc_info[1].dev; + if (!dev) { + pr_err("wl12xx mmc device initialization failed\n"); + goto out; + } + + pdata = dev->platform_data; + if (!pdata) { + pr_err("Platfrom data of wl12xx device not set\n"); + goto out; + } #if 1 - ret = gpio_request_one(am335x_wlan_data.wlan_enable_gpio, - GPIOF_OUT_INIT_LOW, "wlan_en"); - if (ret) { - pr_err("Error requesting wlan enable gpio: %d\n", ret); - goto out; - } + ret = gpio_request_one(am335x_wlan_data.wlan_enable_gpio, + GPIOF_OUT_INIT_LOW, "wlan_en"); + if (ret) { + pr_err("Error requesting wlan enable gpio: %d\n", ret); + goto out; + } #endif - setup_pin_mux(wl12xx_pin_mux); + setup_pin_mux(wl12xx_pin_mux); - pdata->slots[0].set_power = wl12xx_set_power; - pr_info("baseboard_setup_wlan: finished\n"); + pdata->slots[0].set_power = wl12xx_set_power; + pr_info("baseboard_setup_wlan: finished\n"); out: - return; + return; } static __init int baseboard_init(void) { - pr_info("%s [%s]...\n", __func__, BASEBOARD_NAME); + pr_info("%s [%s]...\n", __func__, BASEBOARD_NAME); - baseboard_setup_enet(); + baseboard_setup_enet(); - mmc2_wl12xx_init(); + mmc2_wl12xx_init(); - baseboard_setup_mmc(); + baseboard_setup_mmc(); - baseboard_setup_usb(); + baseboard_setup_usb(); - baseboard_setup_dvi(); + baseboard_setup_dvi(); - baseboard_setup_can(); + baseboard_setup_can(); - baseboard_setup_spi0_devices(); + baseboard_setup_spi0_devices(); - baseboard_i2c0_init(); + baseboard_i2c0_init(); - baseboard_setup_wlan(); + baseboard_setup_wlan(); - baseboard_setup_expansion(); + baseboard_setup_expansion(); - return 0; + return 0; } arch_initcall_sync(baseboard_init); diff --git a/arch/arm/mach-omap2/board-mityarm335x.c b/arch/arm/mach-omap2/board-mityarm335x.c index 17f4609..e298e5d 100644 --- a/arch/arm/mach-omap2/board-mityarm335x.c +++ b/arch/arm/mach-omap2/board-mityarm335x.c @@ -61,60 +61,60 @@ /* module pin mux structure */ struct pinmux_config { - const char *string_name; /* signal name format */ - int val; /* Options for the mux register value */ + const char *string_name; /* signal name format */ + int val; /* Options for the mux register value */ }; static struct omap_board_config_kernel mityarm335x_config[] __initdata = { }; -#define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */ -#define EEPROM_NO_OF_MAC_ADDR 3 +#define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */ +#define EEPROM_NO_OF_MAC_ADDR 3 #define FACTORY_CONFIG_MAGIC 0x012C0138 #define FACTORY_CONFIG_VERSION 0x00010001 struct factory_config { - u32 magic; - u32 version; - u8 mac[6]; - u32 reserved; - u32 spare; - u32 serialnumber; - char partnum[32]; + u32 magic; + u32 version; + u8 mac[6]; + u32 reserved; + u32 spare; + u32 serialnumber; + char partnum[32]; }; static struct factory_config factory_config; /* Pin mux for on board nand flash */ static struct pinmux_config nand_pin_mux[] = { - {"gpmc_ad0.gpmc_ad0", AM33XX_PIN_INPUT_PULLUP}, - {"gpmc_ad1.gpmc_ad1", AM33XX_PIN_INPUT_PULLUP}, - {"gpmc_ad2.gpmc_ad2", AM33XX_PIN_INPUT_PULLUP}, - {"gpmc_ad3.gpmc_ad3", AM33XX_PIN_INPUT_PULLUP}, - {"gpmc_ad4.gpmc_ad4", AM33XX_PIN_INPUT_PULLUP}, - {"gpmc_ad5.gpmc_ad5", AM33XX_PIN_INPUT_PULLUP}, - {"gpmc_ad6.gpmc_ad6", AM33XX_PIN_INPUT_PULLUP}, - {"gpmc_ad7.gpmc_ad7", AM33XX_PIN_INPUT_PULLUP}, - {"gpmc_wait0.gpmc_wait0", AM33XX_PIN_INPUT_PULLUP}, - {"gpmc_wpn.gpmc_wpn", AM33XX_PIN_INPUT_PULLUP}, - {"gpmc_csn0.gpmc_csn0", AM33XX_PULL_DISA}, - {"gpmc_advn_ale.gpmc_advn_ale", AM33XX_PULL_DISA}, - {"gpmc_oen_ren.gpmc_oen_ren", AM33XX_PULL_DISA}, - {"gpmc_wen.gpmc_wen", AM33XX_PULL_DISA}, - {"gpmc_ben0_cle.gpmc_ben0_cle", AM33XX_PULL_DISA}, - {NULL, 0}, + {"gpmc_ad0.gpmc_ad0", AM33XX_PIN_INPUT_PULLUP}, + {"gpmc_ad1.gpmc_ad1", AM33XX_PIN_INPUT_PULLUP}, + {"gpmc_ad2.gpmc_ad2", AM33XX_PIN_INPUT_PULLUP}, + {"gpmc_ad3.gpmc_ad3", AM33XX_PIN_INPUT_PULLUP}, + {"gpmc_ad4.gpmc_ad4", AM33XX_PIN_INPUT_PULLUP}, + {"gpmc_ad5.gpmc_ad5", AM33XX_PIN_INPUT_PULLUP}, + {"gpmc_ad6.gpmc_ad6", AM33XX_PIN_INPUT_PULLUP}, + {"gpmc_ad7.gpmc_ad7", AM33XX_PIN_INPUT_PULLUP}, + {"gpmc_wait0.gpmc_wait0", AM33XX_PIN_INPUT_PULLUP}, + {"gpmc_wpn.gpmc_wpn", AM33XX_PIN_INPUT_PULLUP}, + {"gpmc_csn0.gpmc_csn0", AM33XX_PULL_DISA}, + {"gpmc_advn_ale.gpmc_advn_ale", AM33XX_PULL_DISA}, + {"gpmc_oen_ren.gpmc_oen_ren", AM33XX_PULL_DISA}, + {"gpmc_wen.gpmc_wen", AM33XX_PULL_DISA}, + {"gpmc_ben0_cle.gpmc_ben0_cle", AM33XX_PULL_DISA}, + {NULL, 0}, }; /* Module pin mux for SPI fash */ static struct pinmux_config spi1_pin_mux[] = { - {"ecap0_in_pwm0_out.spi1_sclk", AM33XX_PULL_ENBL | AM33XX_INPUT_EN }, - {"mcasp0_fsx.spi1_d0", AM33XX_PULL_ENBL | AM33XX_PULL_UP | - AM33XX_INPUT_EN }, - {"mcasp0_axr0.spi1_d1", AM33XX_PULL_ENBL | AM33XX_INPUT_EN }, - {"mcasp0_ahclkr.spi1_cs0", AM33XX_PULL_ENBL | AM33XX_PULL_UP | - AM33XX_INPUT_EN }, - {NULL, 0}, + {"ecap0_in_pwm0_out.spi1_sclk", AM33XX_PULL_ENBL | AM33XX_INPUT_EN }, + {"mcasp0_fsx.spi1_d0", AM33XX_PULL_ENBL | AM33XX_PULL_UP | + AM33XX_INPUT_EN }, + {"mcasp0_axr0.spi1_d1", AM33XX_PULL_ENBL | AM33XX_INPUT_EN }, + {"mcasp0_ahclkr.spi1_cs0", AM33XX_PULL_ENBL | AM33XX_PULL_UP | + AM33XX_INPUT_EN }, + {NULL, 0}, }; /* @@ -122,11 +122,11 @@ static struct pinmux_config spi1_pin_mux[] = { * SDASR_EN2 (pins 11/10, ID0) of TPS65910. Also goes to edge connector. */ static struct pinmux_config i2c1_pin_mux[] = { - {"mii1_crs.i2c1_sda", AM33XX_SLEWCTRL_SLOW | AM33XX_PULL_ENBL | - AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT}, - {"mii1_rxerr.i2c1_scl", AM33XX_SLEWCTRL_SLOW | AM33XX_PULL_ENBL | - AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT}, - {NULL, 0}, + {"mii1_crs.i2c1_sda", AM33XX_SLEWCTRL_SLOW | AM33XX_PULL_ENBL | + AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT}, + {"mii1_rxerr.i2c1_scl", AM33XX_SLEWCTRL_SLOW | AM33XX_PULL_ENBL | + AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT}, + {NULL, 0}, }; /* @@ -134,361 +134,361 @@ static struct pinmux_config i2c1_pin_mux[] = { * of TPS65910. Does not leave module. */ static struct pinmux_config i2c2_pin_mux[] = { - {"uart1_ctsn.i2c2_sda", AM33XX_SLEWCTRL_SLOW | AM33XX_PULL_ENBL | - AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT}, - {"uart1_rtsn.i2c2_scl", AM33XX_SLEWCTRL_SLOW | AM33XX_PULL_ENBL | - AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT}, - {NULL, 0}, + {"uart1_ctsn.i2c2_sda", AM33XX_SLEWCTRL_SLOW | AM33XX_PULL_ENBL | + AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT}, + {"uart1_rtsn.i2c2_scl", AM33XX_SLEWCTRL_SLOW | AM33XX_PULL_ENBL | + AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT}, + {NULL, 0}, }; /* * @pin_mux - single module pin-mux structure which defines pin-mux -* details for all its pins. +* details for all its pins. */ static void setup_pin_mux(struct pinmux_config *pin_mux) { - int i; + int i; - for (i = 0; pin_mux->string_name != NULL; pin_mux++) - omap_mux_init_signal(pin_mux->string_name, pin_mux->val); + for (i = 0; pin_mux->string_name != NULL; pin_mux++) + omap_mux_init_signal(pin_mux->string_name, pin_mux->val); } /* NAND partition information */ static struct mtd_partition mityarm335x_nand_partitions[] = { /* All the partition sizes are listed in terms of NAND block size */ - { - .name = "SPL", - .offset = 0, /* Offset = 0x0 */ - .size = SZ_128K, - }, - { - .name = "SPL.backup1", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */ - .size = SZ_128K, - }, - { - .name = "SPL.backup2", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x40000 */ - .size = SZ_128K, - }, - { - .name = "SPL.backup3", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */ - .size = SZ_128K, - }, - { - .name = "U-Boot", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ - .size = 15 * SZ_128K, - }, - { - .name = "U-Boot Env", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */ - .size = 1 * SZ_128K, - }, - { - .name = "Kernel", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ - .size = 40 * SZ_128K, - }, - { - .name = "File System", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */ - .size = MTDPART_SIZ_FULL, - }, + { + .name = "SPL", + .offset = 0, /* Offset = 0x0 */ + .size = SZ_128K, + }, + { + .name = "SPL.backup1", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */ + .size = SZ_128K, + }, + { + .name = "SPL.backup2", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x40000 */ + .size = SZ_128K, + }, + { + .name = "SPL.backup3", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */ + .size = SZ_128K, + }, + { + .name = "U-Boot", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ + .size = 15 * SZ_128K, + }, + { + .name = "U-Boot Env", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */ + .size = 1 * SZ_128K, + }, + { + .name = "Kernel", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ + .size = 40 * SZ_128K, + }, + { + .name = "File System", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */ + .size = MTDPART_SIZ_FULL, + }, }; static void mityarm335x_nand_init(void) { - setup_pin_mux(nand_pin_mux); - board_nand_init(mityarm335x_nand_partitions, - ARRAY_SIZE(mityarm335x_nand_partitions), 0, 0); + setup_pin_mux(nand_pin_mux); + board_nand_init(mityarm335x_nand_partitions, + ARRAY_SIZE(mityarm335x_nand_partitions), 0, 0); } /* SPI flash information (reserved for user applications) */ static struct mtd_partition mityarm335x_spi_partitions[] = { - { - .name = "NOR User Defined", - .offset = 0, - .size = MTDPART_SIZ_FULL, - } + { + .name = "NOR User Defined", + .offset = 0, + .size = MTDPART_SIZ_FULL, + } }; static const struct flash_platform_data mityarm335x_spi_flash = { - .name = "spi_flash", - .parts = mityarm335x_spi_partitions, - .nr_parts = ARRAY_SIZE(mityarm335x_spi_partitions), - .type = "m25p64-nonjedec", + .name = "spi_flash", + .parts = mityarm335x_spi_partitions, + .nr_parts = ARRAY_SIZE(mityarm335x_spi_partitions), + .type = "m25p64-nonjedec", }; static const struct omap2_mcspi_device_config spi1_ctlr_data = { - .turbo_mode = 0, - .single_channel = 0, - .d0_is_mosi = 1, + .turbo_mode = 0, + .single_channel = 0, + .d0_is_mosi = 1, }; /* * On board SPI NOR FLASH */ static struct spi_board_info mityarm335x_spi1_slave_info[] = { - { - .modalias = "m25p80", - .platform_data = &mityarm335x_spi_flash, - .controller_data = (void*)&spi1_ctlr_data, - .irq = -1, - .max_speed_hz = 30000000, - .bus_num = 2, - .chip_select = 0, - .mode = SPI_MODE_3, - }, + { + .modalias = "m25p80", + .platform_data = &mityarm335x_spi_flash, + .controller_data = (void*)&spi1_ctlr_data, + .irq = -1, + .max_speed_hz = 30000000, + .bus_num = 2, + .chip_select = 0, + .mode = SPI_MODE_3, + }, }; /* setup spi1 */ static void spi1_init(void) { - setup_pin_mux(spi1_pin_mux); - spi_register_board_info(mityarm335x_spi1_slave_info, - ARRAY_SIZE(mityarm335x_spi1_slave_info)); - return; + setup_pin_mux(spi1_pin_mux); + spi_register_board_info(mityarm335x_spi1_slave_info, + ARRAY_SIZE(mityarm335x_spi1_slave_info)); + return; } static struct regulator_init_data am335x_dummy; static struct regulator_consumer_supply am335x_vdd1_supply[] = { - REGULATOR_SUPPLY("mpu", "mpu.0"), + REGULATOR_SUPPLY("mpu", "mpu.0"), }; static struct regulator_init_data am335x_vdd1 = { - .constraints = { - .min_uV = 600000, - .max_uV = 1500000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .always_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(am335x_vdd1_supply), - .consumer_supplies = am335x_vdd1_supply, + .constraints = { + .min_uV = 600000, + .max_uV = 1500000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(am335x_vdd1_supply), + .consumer_supplies = am335x_vdd1_supply, }; static struct tps65910_board mityarm335x_tps65910_info = { - .tps65910_pmic_init_data[TPS65910_REG_VRTC] = &am335x_dummy, - .tps65910_pmic_init_data[TPS65910_REG_VIO] = &am335x_dummy, - .tps65910_pmic_init_data[TPS65910_REG_VDD1] = &am335x_vdd1, - .tps65910_pmic_init_data[TPS65910_REG_VDD2] = &am335x_dummy, - .tps65910_pmic_init_data[TPS65910_REG_VDD3] = &am335x_dummy, - .tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &am335x_dummy, - .tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &am335x_dummy, - .tps65910_pmic_init_data[TPS65910_REG_VPLL] = &am335x_dummy, - .tps65910_pmic_init_data[TPS65910_REG_VDAC] = &am335x_dummy, - .tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &am335x_dummy, - .tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &am335x_dummy, - .tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &am335x_dummy, - .tps65910_pmic_init_data[TPS65910_REG_VMMC] = &am335x_dummy, + .tps65910_pmic_init_data[TPS65910_REG_VRTC] = &am335x_dummy, + .tps65910_pmic_init_data[TPS65910_REG_VIO] = &am335x_dummy, + .tps65910_pmic_init_data[TPS65910_REG_VDD1] = &am335x_vdd1, + .tps65910_pmic_init_data[TPS65910_REG_VDD2] = &am335x_dummy, + .tps65910_pmic_init_data[TPS65910_REG_VDD3] = &am335x_dummy, + .tps65910_pmic_init_data[TPS65910_REG_VDIG1] = &am335x_dummy, + .tps65910_pmic_init_data[TPS65910_REG_VDIG2] = &am335x_dummy, + .tps65910_pmic_init_data[TPS65910_REG_VPLL] = &am335x_dummy, + .tps65910_pmic_init_data[TPS65910_REG_VDAC] = &am335x_dummy, + .tps65910_pmic_init_data[TPS65910_REG_VAUX1] = &am335x_dummy, + .tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &am335x_dummy, + .tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &am335x_dummy, + .tps65910_pmic_init_data[TPS65910_REG_VMMC] = &am335x_dummy, }; static struct i2c_board_info __initdata mityarm335x_i2c2_boardinfo[] = { - { - I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1), - .platform_data = &mityarm335x_tps65910_info, - }, + { + I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1), + .platform_data = &mityarm335x_tps65910_info, + }, }; static void read_factory_config(struct memory_accessor *a, void* context) { - int ret; - const char *partnum = NULL; - - ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config)); - if (ret != sizeof(struct factory_config)) { - pr_warning("MityARM-335x: Read Factory Config Failed: %d\n", - ret); - goto bad_config; - } - - if (factory_config.magic != FACTORY_CONFIG_MAGIC) { - pr_warning("MityARM-335x: Factory Config Magic Wrong (%X)\n", - factory_config.magic); - goto bad_config; - } - - if (factory_config.version != FACTORY_CONFIG_VERSION) { - pr_warning("MityARM-335x: Factory Config Version Wrong (%X)\n", - factory_config.version); - goto bad_config; - } - - partnum = factory_config.partnum; - pr_info("MityARM-335x: Part Number = %s\n", partnum); + int ret; + const char *partnum = NULL; + + ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config)); + if (ret != sizeof(struct factory_config)) { + pr_warning("MityARM-335x: Read Factory Config Failed: %d\n", + ret); + goto bad_config; + } + + if (factory_config.magic != FACTORY_CONFIG_MAGIC) { + pr_warning("MityARM-335x: Factory Config Magic Wrong (%X)\n", + factory_config.magic); + goto bad_config; + } + + if (factory_config.version != FACTORY_CONFIG_VERSION) { + pr_warning("MityARM-335x: Factory Config Version Wrong (%X)\n", + factory_config.version); + goto bad_config; + } + + partnum = factory_config.partnum; + pr_info("MityARM-335x: Part Number = %s\n", partnum); bad_config: - return; + return; } static struct at24_platform_data mityarm335x_fd_info = { - .byte_len = 256, - .page_size = 8, - .flags = AT24_FLAG_READONLY | AT24_FLAG_IRUGO, - .setup = read_factory_config, - .context = NULL, + .byte_len = 256, + .page_size = 8, + .flags = AT24_FLAG_READONLY | AT24_FLAG_IRUGO, + .setup = read_factory_config, + .context = NULL, }; static struct i2c_board_info __initdata mityarm335x_i2c1_boardinfo[] = { - { - I2C_BOARD_INFO("24c02", 0x50), - .platform_data = &mityarm335x_fd_info, - }, + { + I2C_BOARD_INFO("24c02", 0x50), + .platform_data = &mityarm335x_fd_info, + }, }; static void __init mityarm335x_i2c_init(void) { - setup_pin_mux(i2c2_pin_mux); - omap_register_i2c_bus(3, 100, mityarm335x_i2c2_boardinfo, - ARRAY_SIZE(mityarm335x_i2c2_boardinfo)); - setup_pin_mux(i2c1_pin_mux); - omap_register_i2c_bus(2, 100, mityarm335x_i2c1_boardinfo, - ARRAY_SIZE(mityarm335x_i2c1_boardinfo)); + setup_pin_mux(i2c2_pin_mux); + omap_register_i2c_bus(3, 100, mityarm335x_i2c2_boardinfo, + ARRAY_SIZE(mityarm335x_i2c2_boardinfo)); + setup_pin_mux(i2c1_pin_mux); + omap_register_i2c_bus(2, 100, mityarm335x_i2c1_boardinfo, + ARRAY_SIZE(mityarm335x_i2c1_boardinfo)); } static struct resource am335x_rtc_resources[] = { - { - .start = AM33XX_RTC_BASE, - .end = AM33XX_RTC_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { /* timer irq */ - .start = AM33XX_IRQ_RTC_TIMER, - .end = AM33XX_IRQ_RTC_TIMER, - .flags = IORESOURCE_IRQ, - }, - { /* alarm irq */ - .start = AM33XX_IRQ_RTC_ALARM, - .end = AM33XX_IRQ_RTC_ALARM, - .flags = IORESOURCE_IRQ, - }, + { + .start = AM33XX_RTC_BASE, + .end = AM33XX_RTC_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { /* timer irq */ + .start = AM33XX_IRQ_RTC_TIMER, + .end = AM33XX_IRQ_RTC_TIMER, + .flags = IORESOURCE_IRQ, + }, + { /* alarm irq */ + .start = AM33XX_IRQ_RTC_ALARM, + .end = AM33XX_IRQ_RTC_ALARM, + .flags = IORESOURCE_IRQ, + }, }; static struct platform_device am335x_rtc_device = { - .name = "omap_rtc", - .id = -1, - .num_resources = ARRAY_SIZE(am335x_rtc_resources), - .resource = am335x_rtc_resources, + .name = "omap_rtc", + .id = -1, + .num_resources = ARRAY_SIZE(am335x_rtc_resources), + .resource = am335x_rtc_resources, }; static int am335x_rtc_init(void) { - void __iomem *base; - struct clk *clk; + void __iomem *base; + struct clk *clk; - clk = clk_get(NULL, "rtc_fck"); - if (IS_ERR(clk)) { - pr_err("rtc : Failed to get RTC clock\n"); - return -1; - } + clk = clk_get(NULL, "rtc_fck"); + if (IS_ERR(clk)) { + pr_err("rtc : Failed to get RTC clock\n"); + return -1; + } - if (clk_enable(clk)) { - pr_err("rtc: Clock Enable Failed\n"); - return -1; - } + if (clk_enable(clk)) { + pr_err("rtc: Clock Enable Failed\n"); + return -1; + } - base = ioremap(AM33XX_RTC_BASE, SZ_4K); + base = ioremap(AM33XX_RTC_BASE, SZ_4K); - if (WARN_ON(!base)) - return -ENOMEM; + if (WARN_ON(!base)) + return -ENOMEM; - /* Unlock the rtc's registers */ - __raw_writel(0x83e70b13, base + 0x6c); - __raw_writel(0x95a4f1e0, base + 0x70); + /* Unlock the rtc's registers */ + __raw_writel(0x83e70b13, base + 0x6c); + __raw_writel(0x95a4f1e0, base + 0x70); - /* - * Enable the 32K OSc - * TODO: Need a better way to handle this - * Since we want the clock to be running before mmc init - * we need to do it before the rtc probe happens - */ - __raw_writel(0x48, base + 0x54); + /* + * Enable the 32K OSc + * TODO: Need a better way to handle this + * Since we want the clock to be running before mmc init + * we need to do it before the rtc probe happens + */ + __raw_writel(0x48, base + 0x54); - iounmap(base); + iounmap(base); - return platform_device_register(&am335x_rtc_device); + return platform_device_register(&am335x_rtc_device); } extern void __iomem * __init am33xx_get_mem_ctlr(void); static struct resource am33xx_cpuidle_resources[] = { - { - .start = AM33XX_EMIF0_BASE, - .end = AM33XX_EMIF0_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, + { + .start = AM33XX_EMIF0_BASE, + .end = AM33XX_EMIF0_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, }; /* AM33XX devices support DDR2 power down */ static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = { - .ddr2_pdown = 1, + .ddr2_pdown = 1, }; static struct platform_device am33xx_cpuidle_device = { - .name = "cpuidle-am33xx", - .num_resources = ARRAY_SIZE(am33xx_cpuidle_resources), - .resource = am33xx_cpuidle_resources, - .dev = { - .platform_data = &am33xx_cpuidle_pdata, - }, + .name = "cpuidle-am33xx", + .num_resources = ARRAY_SIZE(am33xx_cpuidle_resources), + .resource = am33xx_cpuidle_resources, + .dev = { + .platform_data = &am33xx_cpuidle_pdata, + }, }; static void __init am33xx_cpuidle_init(void) { - int ret; + int ret; - am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr(); + am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr(); - ret = platform_device_register(&am33xx_cpuidle_device); + ret = platform_device_register(&am33xx_cpuidle_device); - if (ret) - pr_warning("AM33XX cpuidle registration failed\n"); + if (ret) + pr_warning("AM33XX cpuidle registration failed\n"); } static int mityarm335x_dbg_som_show(struct seq_file *s, void *unused) { - const char *partnum = NULL; - if (factory_config.magic != FACTORY_CONFIG_MAGIC) { - pr_err("MityARM-335x: Factory Config Magic Wrong (%X)\n", - factory_config.magic); - return -EFAULT; - } - - if (factory_config.version != FACTORY_CONFIG_VERSION) { - pr_err("MityARM-335x: Factory Config Version Wrong (%X)\n", - factory_config.version); - return -EFAULT; - } - - partnum = factory_config.partnum; - seq_printf(s, "MityARM-335x: Part Number = %s\n", partnum); - seq_printf(s, " : Serial Num = %d\n", factory_config.serialnumber); - seq_printf(s, " : Found MAC = %pM\n", factory_config.mac); - - return 0; + const char *partnum = NULL; + if (factory_config.magic != FACTORY_CONFIG_MAGIC) { + pr_err("MityARM-335x: Factory Config Magic Wrong (%X)\n", + factory_config.magic); + return -EFAULT; + } + + if (factory_config.version != FACTORY_CONFIG_VERSION) { + pr_err("MityARM-335x: Factory Config Version Wrong (%X)\n", + factory_config.version); + return -EFAULT; + } + + partnum = factory_config.partnum; + seq_printf(s, "MityARM-335x: Part Number = %s\n", partnum); + seq_printf(s, " : Serial Num = %d\n", factory_config.serialnumber); + seq_printf(s, " : Found MAC = %pM\n", factory_config.mac); + + return 0; } static ssize_t mityarm335x_dbg_som_write(struct file *file, - const char __user *user_buf, - size_t count, loff_t *ppos) + const char __user *user_buf, + size_t count, loff_t *ppos) { - return 0; + return 0; } static int mityarm335x_dbg_som_open(struct inode *inode, struct file *file) { - return single_open(file, mityarm335x_dbg_som_show, inode->i_private); + return single_open(file, mityarm335x_dbg_som_show, inode->i_private); } static const struct file_operations mityarm335x_dbg_som_fops = { - .open = mityarm335x_dbg_som_open, - .read = seq_read, - .write = mityarm335x_dbg_som_write, - .llseek = seq_lseek, - .release = single_release, + .open = mityarm335x_dbg_som_open, + .read = seq_read, + .write = mityarm335x_dbg_som_write, + .llseek = seq_lseek, + .release = single_release, }; /* NOT static, so baseboard can see it... */ @@ -496,58 +496,58 @@ struct dentry *mityarm335x_dbg_dir=NULL; static void __init mityarm335x_dbg_init(void) { - static struct dentry *mityarm335x_dbg_board_dir; + static struct dentry *mityarm335x_dbg_board_dir; - mityarm335x_dbg_dir = debugfs_create_dir("mityarm335x", NULL); - if (!mityarm335x_dbg_dir) - return; - mityarm335x_dbg_board_dir = debugfs_create_dir("module", mityarm335x_dbg_dir); - if (!mityarm335x_dbg_board_dir) - return; + mityarm335x_dbg_dir = debugfs_create_dir("mityarm335x", NULL); + if (!mityarm335x_dbg_dir) + return; + mityarm335x_dbg_board_dir = debugfs_create_dir("module", mityarm335x_dbg_dir); + if (!mityarm335x_dbg_board_dir) + return; - (void)debugfs_create_file("config", S_IRUGO, - mityarm335x_dbg_board_dir, NULL, - &mityarm335x_dbg_som_fops); + (void)debugfs_create_file("config", S_IRUGO, + mityarm335x_dbg_board_dir, NULL, + &mityarm335x_dbg_som_fops); } static void __init mityarm335x_init(void) { - am33xx_cpuidle_init(); - am33xx_mux_init(NULL); - omap_serial_init(); - am335x_rtc_init(); - am33xx_cpsw_init(1); /* 1 == enable gigabit */ - mityarm335x_i2c_init(); - omap_sdrc_init(NULL, NULL); - spi1_init(); - mityarm335x_nand_init(); - omap_board_config = mityarm335x_config; - omap_board_config_size = ARRAY_SIZE(mityarm335x_config); - /* Create an alias for icss clock */ - if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL)) - pr_err("failed to create an alias: icss_uart_gclk --> pruss\n"); - /* Create an alias for gfx/sgx clock */ - if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL)) - pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n"); - - mityarm335x_dbg_init(); + am33xx_cpuidle_init(); + am33xx_mux_init(NULL); + omap_serial_init(); + am335x_rtc_init(); + am33xx_cpsw_init(0); /* 1 == enable gigabit */ + mityarm335x_i2c_init(); + omap_sdrc_init(NULL, NULL); + spi1_init(); + mityarm335x_nand_init(); + omap_board_config = mityarm335x_config; + omap_board_config_size = ARRAY_SIZE(mityarm335x_config); + /* Create an alias for icss clock */ + if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL)) + pr_err("failed to create an alias: icss_uart_gclk --> pruss\n"); + /* Create an alias for gfx/sgx clock */ + if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL)) + pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n"); + + mityarm335x_dbg_init(); } static void __init mityarm335x_map_io(void) { - omap2_set_globals_am33xx(); - omapam33xx_map_common_io(); + omap2_set_globals_am33xx(); + omapam33xx_map_common_io(); } MACHINE_START(MITYARM335X, "mityarm335x") - /* Maintainer: Critical Link, LLC */ - .atag_offset = 0x100, - .map_io = mityarm335x_map_io, - .init_irq = ti816x_init_irq, - .init_early = am335x_init_early, - .timer = &omap3_am33xx_timer, - .init_machine = mityarm335x_init, + /* Maintainer: Critical Link, LLC */ + .atag_offset = 0x100, + .map_io = mityarm335x_map_io, + .init_irq = ti816x_init_irq, + .init_early = am335x_init_early, + .timer = &omap3_am33xx_timer, + .init_machine = mityarm335x_init, MACHINE_END diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 2a2a9c1..e70d02c 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -31,7 +31,7 @@ #include #include -#ifdef CONFIG_OMAP3_EDMA +#ifdef CONFIG_OMAP3_EDMA #include #endif @@ -59,178 +59,178 @@ static int __init omap3_l3_init(void) { - int l; - struct omap_hwmod *oh; - struct platform_device *pdev; - char oh_name[L3_MODULES_MAX_LEN]; + int l; + struct omap_hwmod *oh; + struct platform_device *pdev; + char oh_name[L3_MODULES_MAX_LEN]; - /* - * To avoid code running on other OMAPs in - * multi-omap builds - */ - if (!(cpu_is_omap34xx())) - return -ENODEV; + /* + * To avoid code running on other OMAPs in + * multi-omap builds + */ + if (!(cpu_is_omap34xx())) + return -ENODEV; - l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main"); + l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main"); - oh = omap_hwmod_lookup(oh_name); + oh = omap_hwmod_lookup(oh_name); - if (!oh) - pr_err("could not look up %s\n", oh_name); + if (!oh) + pr_err("could not look up %s\n", oh_name); - pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0, - NULL, 0, 0); + pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0, + NULL, 0, 0); - WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); + WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); - return IS_ERR(pdev) ? PTR_ERR(pdev) : 0; + return IS_ERR(pdev) ? PTR_ERR(pdev) : 0; } postcore_initcall(omap3_l3_init); static int __init omap4_l3_init(void) { - int l, i; - struct omap_hwmod *oh[3]; - struct platform_device *pdev; - char oh_name[L3_MODULES_MAX_LEN]; + int l, i; + struct omap_hwmod *oh[3]; + struct platform_device *pdev; + char oh_name[L3_MODULES_MAX_LEN]; - /* If dtb is there, the devices will be created dynamically */ - if (of_have_populated_dt()) - return -ENODEV; + /* If dtb is there, the devices will be created dynamically */ + if (of_have_populated_dt()) + return -ENODEV; - /* - * To avoid code running on other OMAPs in - * multi-omap builds - */ - if (!(cpu_is_omap44xx())) - return -ENODEV; + /* + * To avoid code running on other OMAPs in + * multi-omap builds + */ + if (!(cpu_is_omap44xx())) + return -ENODEV; - for (i = 0; i < L3_MODULES; i++) { - l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1); + for (i = 0; i < L3_MODULES; i++) { + l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1); - oh[i] = omap_hwmod_lookup(oh_name); - if (!(oh[i])) - pr_err("could not look up %s\n", oh_name); - } + oh[i] = omap_hwmod_lookup(oh_name); + if (!(oh[i])) + pr_err("could not look up %s\n", oh_name); + } - pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL, - 0, NULL, 0, 0); + pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL, + 0, NULL, 0, 0); - WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); + WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); - return IS_ERR(pdev) ? PTR_ERR(pdev) : 0; + return IS_ERR(pdev) ? PTR_ERR(pdev) : 0; } postcore_initcall(omap4_l3_init); #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) static struct resource omap2cam_resources[] = { - { - .start = OMAP24XX_CAMERA_BASE, - .end = OMAP24XX_CAMERA_BASE + 0xfff, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_24XX_CAM_IRQ, - .flags = IORESOURCE_IRQ, - } + { + .start = OMAP24XX_CAMERA_BASE, + .end = OMAP24XX_CAMERA_BASE + 0xfff, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_24XX_CAM_IRQ, + .flags = IORESOURCE_IRQ, + } }; static struct platform_device omap2cam_device = { - .name = "omap24xxcam", - .id = -1, - .num_resources = ARRAY_SIZE(omap2cam_resources), - .resource = omap2cam_resources, + .name = "omap24xxcam", + .id = -1, + .num_resources = ARRAY_SIZE(omap2cam_resources), + .resource = omap2cam_resources, }; #endif #define L4_PER_LCDC_PHYS 0x4830E000 static struct resource am33xx_lcdc_resources[] = { - [0] = { /* registers */ - .start = L4_PER_LCDC_PHYS, - .end = L4_PER_LCDC_PHYS + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { /* interrupt */ - .start = AM33XX_IRQ_LCD, - .end = AM33XX_IRQ_LCD, - .flags = IORESOURCE_IRQ, - }, + [0] = { /* registers */ + .start = L4_PER_LCDC_PHYS, + .end = L4_PER_LCDC_PHYS + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { /* interrupt */ + .start = AM33XX_IRQ_LCD, + .end = AM33XX_IRQ_LCD, + .flags = IORESOURCE_IRQ, + }, }; static struct platform_device am33xx_lcdc_device = { - .name = "da8xx_lcdc", - .id = 0, - .num_resources = ARRAY_SIZE(am33xx_lcdc_resources), - .resource = am33xx_lcdc_resources, + .name = "da8xx_lcdc", + .id = 0, + .num_resources = ARRAY_SIZE(am33xx_lcdc_resources), + .resource = am33xx_lcdc_resources, }; void __init am33xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata) { - int ret; + int ret; - am33xx_lcdc_device.dev.platform_data = pdata; + am33xx_lcdc_device.dev.platform_data = pdata; - ret = platform_device_register(&am33xx_lcdc_device); - if (ret) - pr_warning("am33xx_register_lcdc: lcdc registration failed: %d\n", - ret); + ret = platform_device_register(&am33xx_lcdc_device); + if (ret) + pr_warning("am33xx_register_lcdc: lcdc registration failed: %d\n", + ret); } -#if defined(CONFIG_SND_AM335X_SOC_EVM) || \ - defined(CONFIG_SND_AM335X_SOC_EVM_MODULE) || \ - defined(CONFIG_SND_MITYARM335X_SOC_DEVKIT) +#if defined(CONFIG_SND_AM335X_SOC_EVM) || \ + defined(CONFIG_SND_AM335X_SOC_EVM_MODULE) || \ + defined(CONFIG_SND_MITYARM335X_SOC_DEVKIT) static struct resource am335x_mcasp1_resource[] = { - { - .name = "mcasp1", - .start = AM33XX_ASP1_BASE, - .end = AM33XX_ASP1_BASE + (SZ_1K * 12) - 1, - .flags = IORESOURCE_MEM, - }, - /* TX event */ - { - .start = AM33XX_DMA_MCASP1_X, - .end = AM33XX_DMA_MCASP1_X, - .flags = IORESOURCE_DMA, - }, - /* RX event */ - { - .start = AM33XX_DMA_MCASP1_R, - .end = AM33XX_DMA_MCASP1_R, - .flags = IORESOURCE_DMA, - }, + { + .name = "mcasp1", + .start = AM33XX_ASP1_BASE, + .end = AM33XX_ASP1_BASE + (SZ_1K * 12) - 1, + .flags = IORESOURCE_MEM, + }, + /* TX event */ + { + .start = AM33XX_DMA_MCASP1_X, + .end = AM33XX_DMA_MCASP1_X, + .flags = IORESOURCE_DMA, + }, + /* RX event */ + { + .start = AM33XX_DMA_MCASP1_R, + .end = AM33XX_DMA_MCASP1_R, + .flags = IORESOURCE_DMA, + }, }; static struct platform_device am335x_mcasp1_device = { - .name = "davinci-mcasp", - .id = 1, - .num_resources = ARRAY_SIZE(am335x_mcasp1_resource), - .resource = am335x_mcasp1_resource, + .name = "davinci-mcasp", + .id = 1, + .num_resources = ARRAY_SIZE(am335x_mcasp1_resource), + .resource = am335x_mcasp1_resource, }; void __init am335x_register_mcasp1(struct snd_platform_data *pdata) { - pr_info("Registering mcasp1\n"); - am335x_mcasp1_device.dev.platform_data = pdata; - platform_device_register(&am335x_mcasp1_device); + pr_info("Registering mcasp1\n"); + am335x_mcasp1_device.dev.platform_data = pdata; + platform_device_register(&am335x_mcasp1_device); } #else void __init am335x_register_mcasp1(struct snd_platform_data *pdata) {} #endif -#if defined(CONFIG_SND_AM335X_SOC) || \ - defined(CONFIG_SND_AM335X_SOC_SOC_MODULE) || \ - defined(CONFIG_SND_MITYARM335X_SOC_DEVKIT) +#if defined(CONFIG_SND_AM335X_SOC) || \ + defined(CONFIG_SND_AM335X_SOC_SOC_MODULE) || \ + defined(CONFIG_SND_MITYARM335X_SOC_DEVKIT) struct platform_device am33xx_pcm_device = { - .name = "davinci-pcm-audio", - .id = -1, + .name = "davinci-pcm-audio", + .id = -1, }; static void am33xx_init_pcm(void) { - platform_device_register(&am33xx_pcm_device); + platform_device_register(&am33xx_pcm_device); } #else @@ -238,149 +238,149 @@ static inline void am33xx_init_pcm(void) {} #endif static struct resource omap3isp_resources[] = { - { - .start = OMAP3430_ISP_BASE, - .end = OMAP3430_ISP_END, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP3430_ISP_CCP2_BASE, - .end = OMAP3430_ISP_CCP2_END, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP3430_ISP_CCDC_BASE, - .end = OMAP3430_ISP_CCDC_END, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP3430_ISP_HIST_BASE, - .end = OMAP3430_ISP_HIST_END, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP3430_ISP_H3A_BASE, - .end = OMAP3430_ISP_H3A_END, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP3430_ISP_PREV_BASE, - .end = OMAP3430_ISP_PREV_END, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP3430_ISP_RESZ_BASE, - .end = OMAP3430_ISP_RESZ_END, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP3430_ISP_SBL_BASE, - .end = OMAP3430_ISP_SBL_END, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP3430_ISP_CSI2A_REGS1_BASE, - .end = OMAP3430_ISP_CSI2A_REGS1_END, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP3430_ISP_CSIPHY2_BASE, - .end = OMAP3430_ISP_CSIPHY2_END, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP3630_ISP_CSI2A_REGS2_BASE, - .end = OMAP3630_ISP_CSI2A_REGS2_END, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP3630_ISP_CSI2C_REGS1_BASE, - .end = OMAP3630_ISP_CSI2C_REGS1_END, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP3630_ISP_CSIPHY1_BASE, - .end = OMAP3630_ISP_CSIPHY1_END, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP3630_ISP_CSI2C_REGS2_BASE, - .end = OMAP3630_ISP_CSI2C_REGS2_END, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_34XX_CAM_IRQ, - .flags = IORESOURCE_IRQ, - } + { + .start = OMAP3430_ISP_BASE, + .end = OMAP3430_ISP_END, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP3430_ISP_CCP2_BASE, + .end = OMAP3430_ISP_CCP2_END, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP3430_ISP_CCDC_BASE, + .end = OMAP3430_ISP_CCDC_END, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP3430_ISP_HIST_BASE, + .end = OMAP3430_ISP_HIST_END, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP3430_ISP_H3A_BASE, + .end = OMAP3430_ISP_H3A_END, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP3430_ISP_PREV_BASE, + .end = OMAP3430_ISP_PREV_END, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP3430_ISP_RESZ_BASE, + .end = OMAP3430_ISP_RESZ_END, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP3430_ISP_SBL_BASE, + .end = OMAP3430_ISP_SBL_END, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP3430_ISP_CSI2A_REGS1_BASE, + .end = OMAP3430_ISP_CSI2A_REGS1_END, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP3430_ISP_CSIPHY2_BASE, + .end = OMAP3430_ISP_CSIPHY2_END, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP3630_ISP_CSI2A_REGS2_BASE, + .end = OMAP3630_ISP_CSI2A_REGS2_END, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP3630_ISP_CSI2C_REGS1_BASE, + .end = OMAP3630_ISP_CSI2C_REGS1_END, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP3630_ISP_CSIPHY1_BASE, + .end = OMAP3630_ISP_CSIPHY1_END, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP3630_ISP_CSI2C_REGS2_BASE, + .end = OMAP3630_ISP_CSI2C_REGS2_END, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_34XX_CAM_IRQ, + .flags = IORESOURCE_IRQ, + } }; static struct platform_device omap3isp_device = { - .name = "omap3isp", - .id = -1, - .num_resources = ARRAY_SIZE(omap3isp_resources), - .resource = omap3isp_resources, + .name = "omap3isp", + .id = -1, + .num_resources = ARRAY_SIZE(omap3isp_resources), + .resource = omap3isp_resources, }; int omap3_init_camera(struct isp_platform_data *pdata) { - omap3isp_device.dev.platform_data = pdata; - return platform_device_register(&omap3isp_device); + omap3isp_device.dev.platform_data = pdata; + return platform_device_register(&omap3isp_device); } static inline void omap_init_camera(void) { #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) - if (cpu_is_omap24xx()) - platform_device_register(&omap2cam_device); + if (cpu_is_omap24xx()) + platform_device_register(&omap2cam_device); #endif } int __init omap4_keyboard_init(struct omap4_keypad_platform_data - *sdp4430_keypad_data, struct omap_board_data *bdata) + *sdp4430_keypad_data, struct omap_board_data *bdata) { - struct platform_device *pdev; - struct omap_hwmod *oh; - struct omap4_keypad_platform_data *keypad_data; - unsigned int id = -1; - char *oh_name = "kbd"; - char *name = "omap4-keypad"; - - oh = omap_hwmod_lookup(oh_name); - if (!oh) { - pr_err("Could not look up %s\n", oh_name); - return -ENODEV; - } - - keypad_data = sdp4430_keypad_data; - - pdev = omap_device_build(name, id, oh, keypad_data, - sizeof(struct omap4_keypad_platform_data), NULL, 0, 0); - - if (IS_ERR(pdev)) { - WARN(1, "Can't build omap_device for %s:%s.\n", - name, oh->name); - return PTR_ERR(pdev); - } - oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt); - - return 0; + struct platform_device *pdev; + struct omap_hwmod *oh; + struct omap4_keypad_platform_data *keypad_data; + unsigned int id = -1; + char *oh_name = "kbd"; + char *name = "omap4-keypad"; + + oh = omap_hwmod_lookup(oh_name); + if (!oh) { + pr_err("Could not look up %s\n", oh_name); + return -ENODEV; + } + + keypad_data = sdp4430_keypad_data; + + pdev = omap_device_build(name, id, oh, keypad_data, + sizeof(struct omap4_keypad_platform_data), NULL, 0, 0); + + if (IS_ERR(pdev)) { + WARN(1, "Can't build omap_device for %s:%s.\n", + name, oh->name); + return PTR_ERR(pdev); + } + oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt); + + return 0; } #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) static inline void omap_init_mbox(void) { - struct omap_hwmod *oh; - struct platform_device *pdev; - - oh = omap_hwmod_lookup("mailbox"); - if (!oh) { - pr_err("%s: unable to find hwmod\n", __func__); - return; - } - - pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0); - WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n", - __func__, PTR_ERR(pdev)); + struct omap_hwmod *oh; + struct platform_device *pdev; + + oh = omap_hwmod_lookup("mailbox"); + if (!oh) { + pr_err("%s: unable to find hwmod\n", __func__); + return; + } + + pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0); + WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n", + __func__, PTR_ERR(pdev)); } #else static inline void omap_init_mbox(void) { } @@ -391,8 +391,8 @@ static inline void omap_init_sti(void) {} #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE) static struct platform_device omap_pcm = { - .name = "omap-pcm-audio", - .id = -1, + .name = "omap-pcm-audio", + .id = -1, }; /* @@ -409,16 +409,16 @@ OMAP_MCBSP_PLATFORM_DEVICE(5); static void omap_init_audio(void) { - platform_device_register(&omap_mcbsp1); - platform_device_register(&omap_mcbsp2); - if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) { - platform_device_register(&omap_mcbsp3); - platform_device_register(&omap_mcbsp4); - } - if (cpu_is_omap243x() || cpu_is_omap34xx()) - platform_device_register(&omap_mcbsp5); - - platform_device_register(&omap_pcm); + platform_device_register(&omap_mcbsp1); + platform_device_register(&omap_mcbsp2); + if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) { + platform_device_register(&omap_mcbsp3); + platform_device_register(&omap_mcbsp4); + } + if (cpu_is_omap243x() || cpu_is_omap34xx()) + platform_device_register(&omap_mcbsp5); + + platform_device_register(&omap_pcm); } #else @@ -431,45 +431,45 @@ static inline void omap_init_audio(void) {} static int omap_mcspi_init(struct omap_hwmod *oh, void *unused) { - struct platform_device *pdev; - char *name = "omap2_mcspi"; - struct omap2_mcspi_platform_config *pdata; - static int spi_num; - struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr; - - pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); - if (!pdata) { - pr_err("Memory allocation for McSPI device failed\n"); - return -ENOMEM; - } - - pdata->num_cs = mcspi_attrib->num_chipselect; - switch (oh->class->rev) { - case OMAP2_MCSPI_REV: - case OMAP3_MCSPI_REV: - pdata->regs_offset = 0; - break; - case OMAP4_MCSPI_REV: - pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET; - break; - default: - pr_err("Invalid McSPI Revision value\n"); - return -EINVAL; - } - - spi_num++; - pr_info("Registering mcspi %d [%d]\n", spi_num, pdata->num_cs); - pdev = omap_device_build(name, spi_num, oh, pdata, - sizeof(*pdata), NULL, 0, 0); - WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n", - name, oh->name); - kfree(pdata); - return 0; + struct platform_device *pdev; + char *name = "omap2_mcspi"; + struct omap2_mcspi_platform_config *pdata; + static int spi_num; + struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr; + + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + if (!pdata) { + pr_err("Memory allocation for McSPI device failed\n"); + return -ENOMEM; + } + + pdata->num_cs = mcspi_attrib->num_chipselect; + switch (oh->class->rev) { + case OMAP2_MCSPI_REV: + case OMAP3_MCSPI_REV: + pdata->regs_offset = 0; + break; + case OMAP4_MCSPI_REV: + pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET; + break; + default: + pr_err("Invalid McSPI Revision value\n"); + return -EINVAL; + } + + spi_num++; + pr_info("Registering mcspi %d [%d]\n", spi_num, pdata->num_cs); + pdev = omap_device_build(name, spi_num, oh, pdata, + sizeof(*pdata), NULL, 0, 0); + WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n", + name, oh->name); + kfree(pdata); + return 0; } static void omap_init_mcspi(void) { - omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL); + omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL); } #else @@ -480,22 +480,22 @@ static inline void omap_init_mcspi(void) {} static int omap_elm_init(struct omap_hwmod *oh, void *unused) { - struct platform_device *pdev; - char *name = "omap2_elm"; - static int elm_num; + struct platform_device *pdev; + char *name = "omap2_elm"; + static int elm_num; - elm_num++; - pdev = omap_device_build(name, elm_num, oh, NULL, - 0, NULL, - 0, 0); - return 0; + elm_num++; + pdev = omap_device_build(name, elm_num, oh, NULL, + 0, NULL, + 0, 0); + return 0; } static void omap_init_elm(void) { - omap_hwmod_for_each_by_class("elm", omap_elm_init, NULL); + omap_hwmod_for_each_by_class("elm", omap_elm_init, NULL); } #else @@ -504,33 +504,33 @@ static void omap_init_elm(void) {} static struct resource omap2_pmu_resource = { - .start = 3, - .end = 3, - .flags = IORESOURCE_IRQ, + .start = 3, + .end = 3, + .flags = IORESOURCE_IRQ, }; static struct resource omap3_pmu_resource = { - .start = INT_34XX_BENCH_MPU_EMUL, - .end = INT_34XX_BENCH_MPU_EMUL, - .flags = IORESOURCE_IRQ, + .start = INT_34XX_BENCH_MPU_EMUL, + .end = INT_34XX_BENCH_MPU_EMUL, + .flags = IORESOURCE_IRQ, }; static struct platform_device omap_pmu_device = { - .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, - .num_resources = 1, + .name = "arm-pmu", + .id = ARM_PMU_DEVICE_CPU, + .num_resources = 1, }; static void omap_init_pmu(void) { - if (cpu_is_omap24xx()) - omap_pmu_device.resource = &omap2_pmu_resource; - else if (cpu_is_omap34xx()) - omap_pmu_device.resource = &omap3_pmu_resource; - else - return; - - platform_device_register(&omap_pmu_device); + if (cpu_is_omap24xx()) + omap_pmu_device.resource = &omap2_pmu_resource; + else if (cpu_is_omap34xx()) + omap_pmu_device.resource = &omap3_pmu_resource; + else + return; + + platform_device_register(&omap_pmu_device); } @@ -538,62 +538,62 @@ static void omap_init_pmu(void) #ifdef CONFIG_ARCH_OMAP2 static struct resource omap2_sham_resources[] = { - { - .start = OMAP24XX_SEC_SHA1MD5_BASE, - .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_24XX_SHA1MD5, - .flags = IORESOURCE_IRQ, - } + { + .start = OMAP24XX_SEC_SHA1MD5_BASE, + .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_24XX_SHA1MD5, + .flags = IORESOURCE_IRQ, + } }; static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources); #else -#define omap2_sham_resources NULL -#define omap2_sham_resources_sz 0 +#define omap2_sham_resources NULL +#define omap2_sham_resources_sz 0 #endif #ifdef CONFIG_ARCH_OMAP3 static struct resource omap3_sham_resources[] = { - { - .start = OMAP34XX_SEC_SHA1MD5_BASE, - .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_34XX_SHA1MD52_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .start = OMAP34XX_DMA_SHA1MD5_RX, - .flags = IORESOURCE_DMA, - } + { + .start = OMAP34XX_SEC_SHA1MD5_BASE, + .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_34XX_SHA1MD52_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .start = OMAP34XX_DMA_SHA1MD5_RX, + .flags = IORESOURCE_DMA, + } }; static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources); #else -#define omap3_sham_resources NULL -#define omap3_sham_resources_sz 0 +#define omap3_sham_resources NULL +#define omap3_sham_resources_sz 0 #endif static struct platform_device sham_device = { - .name = "omap-sham", - .id = -1, + .name = "omap-sham", + .id = -1, }; static void omap_init_sham(void) { - if (cpu_is_omap24xx()) { - sham_device.resource = omap2_sham_resources; - sham_device.num_resources = omap2_sham_resources_sz; - } else if (cpu_is_omap34xx()) { - sham_device.resource = omap3_sham_resources; - sham_device.num_resources = omap3_sham_resources_sz; - } else { - pr_err("%s: platform not supported\n", __func__); - return; - } - platform_device_register(&sham_device); + if (cpu_is_omap24xx()) { + sham_device.resource = omap2_sham_resources; + sham_device.num_resources = omap2_sham_resources_sz; + } else if (cpu_is_omap34xx()) { + sham_device.resource = omap3_sham_resources; + sham_device.num_resources = omap3_sham_resources_sz; + } else { + pr_err("%s: platform not supported\n", __func__); + return; + } + platform_device_register(&sham_device); } #else static inline void omap_init_sham(void) { } @@ -603,66 +603,66 @@ static inline void omap_init_sham(void) { } #ifdef CONFIG_ARCH_OMAP2 static struct resource omap2_aes_resources[] = { - { - .start = OMAP24XX_SEC_AES_BASE, - .end = OMAP24XX_SEC_AES_BASE + 0x4C, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP24XX_DMA_AES_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = OMAP24XX_DMA_AES_RX, - .flags = IORESOURCE_DMA, - } + { + .start = OMAP24XX_SEC_AES_BASE, + .end = OMAP24XX_SEC_AES_BASE + 0x4C, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP24XX_DMA_AES_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = OMAP24XX_DMA_AES_RX, + .flags = IORESOURCE_DMA, + } }; static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources); #else -#define omap2_aes_resources NULL -#define omap2_aes_resources_sz 0 +#define omap2_aes_resources NULL +#define omap2_aes_resources_sz 0 #endif #ifdef CONFIG_ARCH_OMAP3 static struct resource omap3_aes_resources[] = { - { - .start = OMAP34XX_SEC_AES_BASE, - .end = OMAP34XX_SEC_AES_BASE + 0x4C, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP34XX_DMA_AES2_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = OMAP34XX_DMA_AES2_RX, - .flags = IORESOURCE_DMA, - } + { + .start = OMAP34XX_SEC_AES_BASE, + .end = OMAP34XX_SEC_AES_BASE + 0x4C, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP34XX_DMA_AES2_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = OMAP34XX_DMA_AES2_RX, + .flags = IORESOURCE_DMA, + } }; static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources); #else -#define omap3_aes_resources NULL -#define omap3_aes_resources_sz 0 +#define omap3_aes_resources NULL +#define omap3_aes_resources_sz 0 #endif static struct platform_device aes_device = { - .name = "omap-aes", - .id = -1, + .name = "omap-aes", + .id = -1, }; static void omap_init_aes(void) { - if (cpu_is_omap24xx()) { - aes_device.resource = omap2_aes_resources; - aes_device.num_resources = omap2_aes_resources_sz; - } else if (cpu_is_omap34xx()) { - aes_device.resource = omap3_aes_resources; - aes_device.num_resources = omap3_aes_resources_sz; - } else { - pr_err("%s: platform not supported\n", __func__); - return; - } - platform_device_register(&aes_device); + if (cpu_is_omap24xx()) { + aes_device.resource = omap2_aes_resources; + aes_device.num_resources = omap2_aes_resources_sz; + } else if (cpu_is_omap34xx()) { + aes_device.resource = omap3_aes_resources; + aes_device.num_resources = omap3_aes_resources_sz; + } else { + pr_err("%s: platform not supported\n", __func__); + return; + } + platform_device_register(&aes_device); } #else @@ -674,55 +674,55 @@ static inline void omap_init_aes(void) { } #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) static inline void omap242x_mmc_mux(struct omap_mmc_platform_data - *mmc_controller) + *mmc_controller) { - if ((mmc_controller->slots[0].switch_pin > 0) && \ - (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) - omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, - OMAP_PIN_INPUT_PULLUP); - if ((mmc_controller->slots[0].gpio_wp > 0) && \ - (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) - omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, - OMAP_PIN_INPUT_PULLUP); - - omap_mux_init_signal("sdmmc_cmd", 0); - omap_mux_init_signal("sdmmc_clki", 0); - omap_mux_init_signal("sdmmc_clko", 0); - omap_mux_init_signal("sdmmc_dat0", 0); - omap_mux_init_signal("sdmmc_dat_dir0", 0); - omap_mux_init_signal("sdmmc_cmd_dir", 0); - if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { - omap_mux_init_signal("sdmmc_dat1", 0); - omap_mux_init_signal("sdmmc_dat2", 0); - omap_mux_init_signal("sdmmc_dat3", 0); - omap_mux_init_signal("sdmmc_dat_dir1", 0); - omap_mux_init_signal("sdmmc_dat_dir2", 0); - omap_mux_init_signal("sdmmc_dat_dir3", 0); - } - - /* - * Use internal loop-back in MMC/SDIO Module Input Clock - * selection - */ - if (mmc_controller->slots[0].internal_clock) { - u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); - v |= (1 << 24); - omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); - } + if ((mmc_controller->slots[0].switch_pin > 0) && \ + (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) + omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, + OMAP_PIN_INPUT_PULLUP); + if ((mmc_controller->slots[0].gpio_wp > 0) && \ + (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) + omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, + OMAP_PIN_INPUT_PULLUP); + + omap_mux_init_signal("sdmmc_cmd", 0); + omap_mux_init_signal("sdmmc_clki", 0); + omap_mux_init_signal("sdmmc_clko", 0); + omap_mux_init_signal("sdmmc_dat0", 0); + omap_mux_init_signal("sdmmc_dat_dir0", 0); + omap_mux_init_signal("sdmmc_cmd_dir", 0); + if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { + omap_mux_init_signal("sdmmc_dat1", 0); + omap_mux_init_signal("sdmmc_dat2", 0); + omap_mux_init_signal("sdmmc_dat3", 0); + omap_mux_init_signal("sdmmc_dat_dir1", 0); + omap_mux_init_signal("sdmmc_dat_dir2", 0); + omap_mux_init_signal("sdmmc_dat_dir3", 0); + } + + /* + * Use internal loop-back in MMC/SDIO Module Input Clock + * selection + */ + if (mmc_controller->slots[0].internal_clock) { + u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + v |= (1 << 24); + omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); + } } void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) { - char *name = "mmci-omap"; + char *name = "mmci-omap"; - if (!mmc_data[0]) { - pr_err("%s fails: Incomplete platform data\n", __func__); - return; - } + if (!mmc_data[0]) { + pr_err("%s fails: Incomplete platform data\n", __func__); + return; + } - omap242x_mmc_mux(mmc_data[0]); - omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE, - INT_24XX_MMC_IRQ, mmc_data[0]); + omap242x_mmc_mux(mmc_data[0]); + omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE, + INT_24XX_MMC_IRQ, mmc_data[0]); } #endif @@ -731,31 +731,31 @@ void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE) #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) -#define OMAP_HDQ_BASE 0x480B2000 +#define OMAP_HDQ_BASE 0x480B2000 #endif static struct resource omap_hdq_resources[] = { - { - .start = OMAP_HDQ_BASE, - .end = OMAP_HDQ_BASE + 0x1C, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_24XX_HDQ_IRQ, - .flags = IORESOURCE_IRQ, - }, + { + .start = OMAP_HDQ_BASE, + .end = OMAP_HDQ_BASE + 0x1C, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_24XX_HDQ_IRQ, + .flags = IORESOURCE_IRQ, + }, }; static struct platform_device omap_hdq_dev = { - .name = "omap_hdq", - .id = 0, - .dev = { - .platform_data = NULL, - }, - .num_resources = ARRAY_SIZE(omap_hdq_resources), - .resource = omap_hdq_resources, + .name = "omap_hdq", + .id = 0, + .dev = { + .platform_data = NULL, + }, + .num_resources = ARRAY_SIZE(omap_hdq_resources), + .resource = omap_hdq_resources, }; static inline void omap_hdq_init(void) { - (void) platform_device_register(&omap_hdq_dev); + (void) platform_device_register(&omap_hdq_dev); } #else static inline void omap_hdq_init(void) {} @@ -764,7 +764,7 @@ static inline void omap_hdq_init(void) {} /*---------------------------------------------------------------------------*/ #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \ - defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE) + defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE) #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = { }; @@ -774,15 +774,15 @@ static struct resource omap_vout_resource[2] = { #endif static struct platform_device omap_vout_device = { - .name = "omap_vout", - .num_resources = ARRAY_SIZE(omap_vout_resource), - .resource = &omap_vout_resource[0], - .id = -1, + .name = "omap_vout", + .num_resources = ARRAY_SIZE(omap_vout_resource), + .resource = &omap_vout_resource[0], + .id = -1, }; static void omap_init_vout(void) { - if (platform_device_register(&omap_vout_device) < 0) - printk(KERN_ERR "Unable to register OMAP-VOUT device\n"); + if (platform_device_register(&omap_vout_device) < 0) + printk(KERN_ERR "Unable to register OMAP-VOUT device\n"); } #else static inline void omap_init_vout(void) {} @@ -790,122 +790,122 @@ static inline void omap_init_vout(void) {} #if defined(CONFIG_SOC_OMAPAM33XX) && defined(CONFIG_OMAP3_EDMA) -#define AM33XX_TPCC_BASE 0x49000000 -#define AM33XX_TPTC0_BASE 0x49800000 -#define AM33XX_TPTC1_BASE 0x49900000 -#define AM33XX_TPTC2_BASE 0x49a00000 +#define AM33XX_TPCC_BASE 0x49000000 +#define AM33XX_TPTC0_BASE 0x49800000 +#define AM33XX_TPTC1_BASE 0x49900000 +#define AM33XX_TPTC2_BASE 0x49a00000 -#define AM33XX_SCM_BASE_EDMA 0x00000f90 +#define AM33XX_SCM_BASE_EDMA 0x00000f90 static struct resource am33xx_edma_resources[] = { - { - .name = "edma_cc0", - .start = AM33XX_TPCC_BASE, - .end = AM33XX_TPCC_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma_tc0", - .start = AM33XX_TPTC0_BASE, - .end = AM33XX_TPTC0_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma_tc1", - .start = AM33XX_TPTC1_BASE, - .end = AM33XX_TPTC1_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma_tc2", - .start = AM33XX_TPTC2_BASE, - .end = AM33XX_TPTC2_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma0", - .start = AM33XX_IRQ_TPCC0_INT_PO0, - .flags = IORESOURCE_IRQ, - }, - { - .name = "edma0_err", - .start = AM33XX_IRQ_TPCC0_ERRINT_PO, - .flags = IORESOURCE_IRQ, - }, + { + .name = "edma_cc0", + .start = AM33XX_TPCC_BASE, + .end = AM33XX_TPCC_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc0", + .start = AM33XX_TPTC0_BASE, + .end = AM33XX_TPTC0_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc1", + .start = AM33XX_TPTC1_BASE, + .end = AM33XX_TPTC1_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc2", + .start = AM33XX_TPTC2_BASE, + .end = AM33XX_TPTC2_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma0", + .start = AM33XX_IRQ_TPCC0_INT_PO0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "edma0_err", + .start = AM33XX_IRQ_TPCC0_ERRINT_PO, + .flags = IORESOURCE_IRQ, + }, }; static const s16 am33xx_dma_rsv_chans[][2] = { - /* (offset, number) */ - {0, 2}, - {14, 2}, - {26, 6}, - {48, 4}, - {56, 8}, - {-1, -1} + /* (offset, number) */ + {0, 2}, + {14, 2}, + {26, 6}, + {48, 4}, + {56, 8}, + {-1, -1} }; static const s16 am33xx_dma_rsv_slots[][2] = { - /* (offset, number) */ - {0, 2}, - {14, 2}, - {26, 6}, - {48, 4}, - {56, 8}, - {64, 127}, - {-1, -1} + /* (offset, number) */ + {0, 2}, + {14, 2}, + {26, 6}, + {48, 4}, + {56, 8}, + {64, 127}, + {-1, -1} }; /* Three Transfer Controllers on AM33XX */ static const s8 am33xx_queue_tc_mapping[][2] = { - /* {event queue no, TC no} */ - {0, 0}, - {1, 1}, - {2, 2}, - {-1, -1} + /* {event queue no, TC no} */ + {0, 0}, + {1, 1}, + {2, 2}, + {-1, -1} }; static const s8 am33xx_queue_priority_mapping[][2] = { - /* {event queue no, Priority} */ - {0, 0}, - {1, 1}, - {2, 2}, - {-1, -1} + /* {event queue no, Priority} */ + {0, 0}, + {1, 1}, + {2, 2}, + {-1, -1} }; static struct event_to_channel_map am33xx_xbar_event_mapping[] = { - /* {xbar event no, Channel} */ - {1, 12}, /* SDTXEVT1 -> MMCHS2 */ - {2, 13}, /* SDRXEVT1 -> MMCHS2 */ - {3, -1}, - {4, -1}, - {5, -1}, - {6, -1}, - {7, -1}, - {8, -1}, - {9, -1}, - {10, -1}, - {11, -1}, - {12, -1}, - {13, -1}, - {14, -1}, - {15, -1}, - {16, -1}, - {17, -1}, - {18, -1}, - {19, -1}, - {20, -1}, - {21, -1}, - {22, -1}, - {23, -1}, - {24, -1}, - {25, -1}, - {26, -1}, - {27, -1}, - {28, -1}, - {29, -1}, - {30, -1}, - {31, -1}, - {-1, -1} + /* {xbar event no, Channel} */ + {1, 12}, /* SDTXEVT1 -> MMCHS2 */ + {2, 13}, /* SDRXEVT1 -> MMCHS2 */ + {3, -1}, + {4, -1}, + {5, -1}, + {6, -1}, + {7, -1}, + {8, -1}, + {9, -1}, + {10, -1}, + {11, -1}, + {12, -1}, + {13, -1}, + {14, -1}, + {15, -1}, + {16, -1}, + {17, -1}, + {18, -1}, + {19, -1}, + {20, -1}, + {21, -1}, + {22, -1}, + {23, -1}, + {24, -1}, + {25, -1}, + {26, -1}, + {27, -1}, + {28, -1}, + {29, -1}, + {30, -1}, + {31, -1}, + {-1, -1} }; /** @@ -922,108 +922,108 @@ static struct event_to_channel_map am33xx_xbar_event_mapping[] = { * Returns zero on success, else negative errno. */ int map_xbar_event_to_channel(unsigned int event, unsigned int *channel, - struct event_to_channel_map *xbar_event_mapping) + struct event_to_channel_map *xbar_event_mapping) { - unsigned int ctrl = 0; - unsigned int xbar_evt_no = 0; - unsigned int val = 0; - unsigned int offset = 0; - unsigned int mask = 0; - - ctrl = EDMA_CTLR(event); - xbar_evt_no = event - (edma_info[ctrl]->num_channels); - - if (event < edma_info[ctrl]->num_channels) { - *channel = event; - } else if (event < edma_info[ctrl]->num_events) { - *channel = xbar_event_mapping[xbar_evt_no].channel_no; - /* confirm the range */ - if (*channel < EDMA_MAX_DMACH) - clear_bit(*channel, edma_info[ctrl]->edma_unused); - mask = (*channel)%4; - offset = (*channel)/4; - offset *= 4; - offset += mask; - val = (unsigned int)__raw_readl(AM33XX_CTRL_REGADDR( - AM33XX_SCM_BASE_EDMA + offset)); - val = val & (~(0xFF)); - val = val | (xbar_event_mapping[xbar_evt_no].xbar_event_no); - __raw_writel(val, - AM33XX_CTRL_REGADDR(AM33XX_SCM_BASE_EDMA + offset)); - return 0; - } else { - return -EINVAL; - } - - return 0; + unsigned int ctrl = 0; + unsigned int xbar_evt_no = 0; + unsigned int val = 0; + unsigned int offset = 0; + unsigned int mask = 0; + + ctrl = EDMA_CTLR(event); + xbar_evt_no = event - (edma_info[ctrl]->num_channels); + + if (event < edma_info[ctrl]->num_channels) { + *channel = event; + } else if (event < edma_info[ctrl]->num_events) { + *channel = xbar_event_mapping[xbar_evt_no].channel_no; + /* confirm the range */ + if (*channel < EDMA_MAX_DMACH) + clear_bit(*channel, edma_info[ctrl]->edma_unused); + mask = (*channel)%4; + offset = (*channel)/4; + offset *= 4; + offset += mask; + val = (unsigned int)__raw_readl(AM33XX_CTRL_REGADDR( + AM33XX_SCM_BASE_EDMA + offset)); + val = val & (~(0xFF)); + val = val | (xbar_event_mapping[xbar_evt_no].xbar_event_no); + __raw_writel(val, + AM33XX_CTRL_REGADDR(AM33XX_SCM_BASE_EDMA + offset)); + return 0; + } else { + return -EINVAL; + } + + return 0; } static struct edma_soc_info am33xx_edma_info[] = { - { - .n_channel = 64, - .n_region = 4, - .n_slot = 256, - .n_tc = 3, - .n_cc = 1, - .rsv_chans = am33xx_dma_rsv_chans, - .rsv_slots = am33xx_dma_rsv_slots, - .queue_tc_mapping = am33xx_queue_tc_mapping, - .queue_priority_mapping = am33xx_queue_priority_mapping, - .is_xbar = 1, - .n_events = 95, - .xbar_event_mapping = am33xx_xbar_event_mapping, - .map_xbar_channel = map_xbar_event_to_channel, - }, + { + .n_channel = 64, + .n_region = 4, + .n_slot = 256, + .n_tc = 3, + .n_cc = 1, + .rsv_chans = am33xx_dma_rsv_chans, + .rsv_slots = am33xx_dma_rsv_slots, + .queue_tc_mapping = am33xx_queue_tc_mapping, + .queue_priority_mapping = am33xx_queue_priority_mapping, + .is_xbar = 1, + .n_events = 95, + .xbar_event_mapping = am33xx_xbar_event_mapping, + .map_xbar_channel = map_xbar_event_to_channel, + }, }; static struct platform_device am33xx_edma_device = { - .name = "edma", - .id = -1, - .dev = { - .platform_data = am33xx_edma_info, - }, - .num_resources = ARRAY_SIZE(am33xx_edma_resources), - .resource = am33xx_edma_resources, + .name = "edma", + .id = -1, + .dev = { + .platform_data = am33xx_edma_info, + }, + .num_resources = ARRAY_SIZE(am33xx_edma_resources), + .resource = am33xx_edma_resources, }; int __init am33xx_register_edma(void) { - struct platform_device *pdev; - static struct clk *edma_clk; - - if (cpu_is_am33xx()) - pdev = &am33xx_edma_device; - else { - pr_err("%s: platform not supported\n", __func__); - return -ENODEV; - } - - edma_clk = clk_get(NULL, "tpcc_ick"); - if (IS_ERR(edma_clk)) { - printk(KERN_ERR "EDMA: Failed to get clock\n"); - return -EBUSY; - } - clk_enable(edma_clk); - edma_clk = clk_get(NULL, "tptc0_ick"); - if (IS_ERR(edma_clk)) { - printk(KERN_ERR "EDMA: Failed to get clock\n"); - return -EBUSY; - } - clk_enable(edma_clk); - edma_clk = clk_get(NULL, "tptc1_ick"); - if (IS_ERR(edma_clk)) { - printk(KERN_ERR "EDMA: Failed to get clock\n"); - return -EBUSY; - } - clk_enable(edma_clk); - edma_clk = clk_get(NULL, "tptc2_ick"); - if (IS_ERR(edma_clk)) { - printk(KERN_ERR "EDMA: Failed to get clock\n"); - return -EBUSY; - } - clk_enable(edma_clk); - - return platform_device_register(pdev); + struct platform_device *pdev; + static struct clk *edma_clk; + + if (cpu_is_am33xx()) + pdev = &am33xx_edma_device; + else { + pr_err("%s: platform not supported\n", __func__); + return -ENODEV; + } + + edma_clk = clk_get(NULL, "tpcc_ick"); + if (IS_ERR(edma_clk)) { + printk(KERN_ERR "EDMA: Failed to get clock\n"); + return -EBUSY; + } + clk_enable(edma_clk); + edma_clk = clk_get(NULL, "tptc0_ick"); + if (IS_ERR(edma_clk)) { + printk(KERN_ERR "EDMA: Failed to get clock\n"); + return -EBUSY; + } + clk_enable(edma_clk); + edma_clk = clk_get(NULL, "tptc1_ick"); + if (IS_ERR(edma_clk)) { + printk(KERN_ERR "EDMA: Failed to get clock\n"); + return -EBUSY; + } + clk_enable(edma_clk); + edma_clk = clk_get(NULL, "tptc2_ick"); + if (IS_ERR(edma_clk)) { + printk(KERN_ERR "EDMA: Failed to get clock\n"); + return -EBUSY; + } + clk_enable(edma_clk); + + return platform_device_register(pdev); } #else @@ -1032,71 +1032,71 @@ static inline void am33xx_register_edma(void) {} #if defined (CONFIG_SOC_OMAPAM33XX) struct uio_pruss_pdata am335x_pruss_uio_pdata = { - .pintc_base = 0x20000, + .pintc_base = 0x20000, }; static struct resource am335x_pruss_resources[] = { - { - .start = AM33XX_ICSS_BASE, - .end = AM33XX_ICSS_BASE + AM33XX_ICSS_LEN, - .flags = IORESOURCE_MEM, - }, - { - .start = AM33XX_IRQ_ICSS0_0, - .end = AM33XX_IRQ_ICSS0_0, - .flags = IORESOURCE_IRQ, - }, - { - .start = AM33XX_IRQ_ICSS0_1, - .end = AM33XX_IRQ_ICSS0_1, - .flags = IORESOURCE_IRQ, - }, - { - .start = AM33XX_IRQ_ICSS0_2, - .end = AM33XX_IRQ_ICSS0_2, - .flags = IORESOURCE_IRQ, - }, - { - .start = AM33XX_IRQ_ICSS0_3, - .end = AM33XX_IRQ_ICSS0_3, - .flags = IORESOURCE_IRQ, - }, - { - .start = AM33XX_IRQ_ICSS0_4, - .end = AM33XX_IRQ_ICSS0_4, - .flags = IORESOURCE_IRQ, - }, - { - .start = AM33XX_IRQ_ICSS0_5, - .end = AM33XX_IRQ_ICSS0_5, - .flags = IORESOURCE_IRQ, - }, - { - .start = AM33XX_IRQ_ICSS0_6, - .end = AM33XX_IRQ_ICSS0_6, - .flags = IORESOURCE_IRQ, - }, - { - .start = AM33XX_IRQ_ICSS0_7, - .end = AM33XX_IRQ_ICSS0_7, - .flags = IORESOURCE_IRQ, - }, + { + .start = AM33XX_ICSS_BASE, + .end = AM33XX_ICSS_BASE + AM33XX_ICSS_LEN, + .flags = IORESOURCE_MEM, + }, + { + .start = AM33XX_IRQ_ICSS0_0, + .end = AM33XX_IRQ_ICSS0_0, + .flags = IORESOURCE_IRQ, + }, + { + .start = AM33XX_IRQ_ICSS0_1, + .end = AM33XX_IRQ_ICSS0_1, + .flags = IORESOURCE_IRQ, + }, + { + .start = AM33XX_IRQ_ICSS0_2, + .end = AM33XX_IRQ_ICSS0_2, + .flags = IORESOURCE_IRQ, + }, + { + .start = AM33XX_IRQ_ICSS0_3, + .end = AM33XX_IRQ_ICSS0_3, + .flags = IORESOURCE_IRQ, + }, + { + .start = AM33XX_IRQ_ICSS0_4, + .end = AM33XX_IRQ_ICSS0_4, + .flags = IORESOURCE_IRQ, + }, + { + .start = AM33XX_IRQ_ICSS0_5, + .end = AM33XX_IRQ_ICSS0_5, + .flags = IORESOURCE_IRQ, + }, + { + .start = AM33XX_IRQ_ICSS0_6, + .end = AM33XX_IRQ_ICSS0_6, + .flags = IORESOURCE_IRQ, + }, + { + .start = AM33XX_IRQ_ICSS0_7, + .end = AM33XX_IRQ_ICSS0_7, + .flags = IORESOURCE_IRQ, + }, }; static struct platform_device am335x_pruss_uio_dev = { - .name = "pruss_uio", - .id = -1, - .num_resources = ARRAY_SIZE(am335x_pruss_resources), - .resource = am335x_pruss_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - } + .name = "pruss_uio", + .id = -1, + .num_resources = ARRAY_SIZE(am335x_pruss_resources), + .resource = am335x_pruss_resources, + .dev = { + .coherent_dma_mask = 0xffffffff, + } }; int __init am335x_register_pruss_uio(struct uio_pruss_pdata *config) { - am335x_pruss_uio_dev.dev.platform_data = config; - return platform_device_register(&am335x_pruss_uio_dev); + am335x_pruss_uio_dev.dev.platform_data = config; + return platform_device_register(&am335x_pruss_uio_dev); } #endif @@ -1104,139 +1104,139 @@ int __init am335x_register_pruss_uio(struct uio_pruss_pdata *config) static int __init omap2_init_devices(void) { - /* - * please keep these calls, and their implementations above, - * in alphabetical order so they're easier to sort through. - */ - omap_init_audio(); - omap_init_camera(); - omap_init_mbox(); - omap_init_mcspi(); - omap_init_elm(); - omap_init_pmu(); - omap_hdq_init(); - omap_init_sti(); - omap_init_sham(); - omap_init_aes(); - omap_init_vout(); - am33xx_register_edma(); - am33xx_init_pcm(); + /* + * please keep these calls, and their implementations above, + * in alphabetical order so they're easier to sort through. + */ + omap_init_audio(); + omap_init_camera(); + omap_init_mbox(); + omap_init_mcspi(); + omap_init_elm(); + omap_init_pmu(); + omap_hdq_init(); + omap_init_sti(); + omap_init_sham(); + omap_init_aes(); + omap_init_vout(); + am33xx_register_edma(); + am33xx_init_pcm(); #if defined (CONFIG_SOC_OMAPAM33XX) - am335x_register_pruss_uio(&am335x_pruss_uio_pdata); + am335x_register_pruss_uio(&am335x_pruss_uio_pdata); #endif - return 0; + return 0; } arch_initcall(omap2_init_devices); -#define AM33XX_EMAC_MDIO_FREQ (1000000) +#define AM33XX_EMAC_MDIO_FREQ (1000000) static u64 am33xx_cpsw_dmamask = DMA_BIT_MASK(32); /* TODO : Verify the offsets */ static struct cpsw_slave_data am33xx_cpsw_slaves[] = { - { - .slave_reg_ofs = 0x208, - .sliver_reg_ofs = 0xd80, + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, #ifdef CONFIG_BASEBOARD_MITYARM335X_TESTFIXTURE - .phy_id = "0:01", + .phy_id = "0:01", #else - .phy_id = "0:00", + .phy_id = "0:01", #endif - }, - { - .slave_reg_ofs = 0x308, - .sliver_reg_ofs = 0xdc0, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, #ifdef CONFIG_BASEBOARD_MITYARM335X_TESTFIXTURE - .phy_id = "0:00", + .phy_id = "0:00", #else - .phy_id = "0:01", + .phy_id = "0:00", #endif - }, + }, }; static struct cpsw_platform_data am33xx_cpsw_pdata = { - .ss_reg_ofs = 0x1200, - .channels = 8, - .cpdma_reg_ofs = 0x800, - .slaves = 2, - .slave_data = am33xx_cpsw_slaves, - .ale_reg_ofs = 0xd00, - .ale_entries = 1024, - .host_port_reg_ofs = 0x108, - .hw_stats_reg_ofs = 0x900, - .bd_ram_ofs = 0x2000, - .bd_ram_size = SZ_16K, - .rx_descs = 64, - .mac_control = BIT(5), /* MIIEN */ - .gigabit_en = 1, - .host_port_num = 0, - .no_bd_ram = false, - .version = CPSW_VERSION_2, + .ss_reg_ofs = 0x1200, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 2, + .slave_data = am33xx_cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .bd_ram_size = SZ_16K, + .rx_descs = 64, + .mac_control = BIT(5), /* MIIEN */ + .gigabit_en = 0, + .host_port_num = 0, + .no_bd_ram = false, + .version = CPSW_VERSION_2, }; static struct mdio_platform_data am33xx_cpsw_mdiopdata = { - .bus_freq = AM33XX_EMAC_MDIO_FREQ, + .bus_freq = AM33XX_EMAC_MDIO_FREQ, }; static struct resource am33xx_cpsw_mdioresources[] = { - { - .start = AM33XX_CPSW_MDIO_BASE, - .end = AM33XX_CPSW_MDIO_BASE + SZ_256 - 1, - .flags = IORESOURCE_MEM, - }, + { + .start = AM33XX_CPSW_MDIO_BASE, + .end = AM33XX_CPSW_MDIO_BASE + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, }; static struct platform_device am33xx_cpsw_mdiodevice = { - .name = "davinci_mdio", - .id = 0, - .num_resources = ARRAY_SIZE(am33xx_cpsw_mdioresources), - .resource = am33xx_cpsw_mdioresources, - .dev.platform_data = &am33xx_cpsw_mdiopdata, + .name = "davinci_mdio", + .id = 0, + .num_resources = ARRAY_SIZE(am33xx_cpsw_mdioresources), + .resource = am33xx_cpsw_mdioresources, + .dev.platform_data = &am33xx_cpsw_mdiopdata, }; static struct resource am33xx_cpsw_resources[] = { - { - .start = AM33XX_CPSW_BASE, - .end = AM33XX_CPSW_BASE + SZ_2K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = AM33XX_CPSW_SS_BASE, - .end = AM33XX_CPSW_SS_BASE + SZ_256 - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = AM33XX_IRQ_CPSW_C0_RX, - .end = AM33XX_IRQ_CPSW_C0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = AM33XX_IRQ_DMTIMER5, - .end = AM33XX_IRQ_DMTIMER5, - .flags = IORESOURCE_IRQ, - }, - { - .start = AM33XX_IRQ_DMTIMER6, - .end = AM33XX_IRQ_DMTIMER6, - .flags = IORESOURCE_IRQ, - }, - { - .start = AM33XX_IRQ_CPSW_C0, - .end = AM33XX_IRQ_CPSW_C0, - .flags = IORESOURCE_IRQ, - }, + { + .start = AM33XX_CPSW_BASE, + .end = AM33XX_CPSW_BASE + SZ_2K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = AM33XX_CPSW_SS_BASE, + .end = AM33XX_CPSW_SS_BASE + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = AM33XX_IRQ_CPSW_C0_RX, + .end = AM33XX_IRQ_CPSW_C0_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = AM33XX_IRQ_DMTIMER5, + .end = AM33XX_IRQ_DMTIMER5, + .flags = IORESOURCE_IRQ, + }, + { + .start = AM33XX_IRQ_DMTIMER6, + .end = AM33XX_IRQ_DMTIMER6, + .flags = IORESOURCE_IRQ, + }, + { + .start = AM33XX_IRQ_CPSW_C0, + .end = AM33XX_IRQ_CPSW_C0, + .flags = IORESOURCE_IRQ, + }, }; static struct platform_device am33xx_cpsw_device = { - .name = "cpsw", - .id = 0, - .num_resources = ARRAY_SIZE(am33xx_cpsw_resources), - .resource = am33xx_cpsw_resources, - .dev = { - .platform_data = &am33xx_cpsw_pdata, - .dma_mask = &am33xx_cpsw_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, + .name = "cpsw", + .id = 0, + .num_resources = ARRAY_SIZE(am33xx_cpsw_resources), + .resource = am33xx_cpsw_resources, + .dev = { + .platform_data = &am33xx_cpsw_pdata, + .dma_mask = &am33xx_cpsw_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, }; static unsigned char am33xx_macid0[ETH_ALEN]; @@ -1254,8 +1254,8 @@ static unsigned int am33xx_evmid; */ void am33xx_evmid_fillup(unsigned int evmid) { - am33xx_evmid = evmid; - return; + am33xx_evmid = evmid; + return; } /* @@ -1271,214 +1271,233 @@ void am33xx_evmid_fillup(unsigned int evmid) */ void am33xx_cpsw_macidfillup(char *eeprommacid0, char *eeprommacid1) { - u32 i; + u32 i; - /* Fillup these mac addresses with the mac adresses from eeprom */ - for (i = 0; i < ETH_ALEN; i++) { - am33xx_macid0[i] = eeprommacid0[i]; - am33xx_macid1[i] = eeprommacid1[i]; - } + /* Fillup these mac addresses with the mac adresses from eeprom */ + for (i = 0; i < ETH_ALEN; i++) { + am33xx_macid0[i] = eeprommacid0[i]; + am33xx_macid1[i] = eeprommacid1[i]; + } - return; + return; } void am33xx_cpsw_init(unsigned int gigen) { - u32 mac_lo, mac_hi; - u32 i; - - mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_LO); - mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_HI); - am33xx_cpsw_slaves[0].mac_addr[0] = mac_hi & 0xFF; - am33xx_cpsw_slaves[0].mac_addr[1] = (mac_hi & 0xFF00) >> 8; - am33xx_cpsw_slaves[0].mac_addr[2] = (mac_hi & 0xFF0000) >> 16; - am33xx_cpsw_slaves[0].mac_addr[3] = (mac_hi & 0xFF000000) >> 24; - am33xx_cpsw_slaves[0].mac_addr[4] = mac_lo & 0xFF; - am33xx_cpsw_slaves[0].mac_addr[5] = (mac_lo & 0xFF00) >> 8; - - /* Read MACID0 from eeprom if eFuse MACID is invalid */ - if (!is_valid_ether_addr(am33xx_cpsw_slaves[0].mac_addr)) { - for (i = 0; i < ETH_ALEN; i++) - am33xx_cpsw_slaves[0].mac_addr[i] = am33xx_macid0[i]; - } - - mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_LO); - mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_HI); - am33xx_cpsw_slaves[1].mac_addr[0] = mac_hi & 0xFF; - am33xx_cpsw_slaves[1].mac_addr[1] = (mac_hi & 0xFF00) >> 8; - am33xx_cpsw_slaves[1].mac_addr[2] = (mac_hi & 0xFF0000) >> 16; - am33xx_cpsw_slaves[1].mac_addr[3] = (mac_hi & 0xFF000000) >> 24; - am33xx_cpsw_slaves[1].mac_addr[4] = mac_lo & 0xFF; - am33xx_cpsw_slaves[1].mac_addr[5] = (mac_lo & 0xFF00) >> 8; - - /* Read MACID1 from eeprom if eFuse MACID is invalid */ - if (!is_valid_ether_addr(am33xx_cpsw_slaves[1].mac_addr)) { - for (i = 0; i < ETH_ALEN; i++) - am33xx_cpsw_slaves[1].mac_addr[i] = am33xx_macid1[i]; - } - - if (am33xx_evmid == IND_AUT_MTR_EVM) { - am33xx_cpsw_slaves[0].phy_id = "0:1e"; - am33xx_cpsw_slaves[1].phy_id = "0:00"; - } - - am33xx_cpsw_pdata.gigabit_en = gigen; - - memcpy(am33xx_cpsw_pdata.mac_addr, - am33xx_cpsw_slaves[0].mac_addr, ETH_ALEN); - platform_device_register(&am33xx_cpsw_mdiodevice); - platform_device_register(&am33xx_cpsw_device); - clk_add_alias(NULL, dev_name(&am33xx_cpsw_mdiodevice.dev), - NULL, &am33xx_cpsw_device.dev); + u32 mac_lo, mac_hi; + u32 i; + + mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_LO); + mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_HI); + am33xx_cpsw_slaves[0].mac_addr[0] = mac_hi & 0xFF; + am33xx_cpsw_slaves[0].mac_addr[1] = (mac_hi & 0xFF00) >> 8; + am33xx_cpsw_slaves[0].mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + am33xx_cpsw_slaves[0].mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + am33xx_cpsw_slaves[0].mac_addr[4] = mac_lo & 0xFF; + am33xx_cpsw_slaves[0].mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + /* Read MACID0 from eeprom if eFuse MACID is invalid */ + if (!is_valid_ether_addr(am33xx_cpsw_slaves[0].mac_addr)) { + for (i = 0; i < ETH_ALEN; i++) + am33xx_cpsw_slaves[0].mac_addr[i] = am33xx_macid0[i]; + } + + mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_LO); + mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_HI); + am33xx_cpsw_slaves[1].mac_addr[0] = mac_hi & 0xFF; + am33xx_cpsw_slaves[1].mac_addr[1] = (mac_hi & 0xFF00) >> 8; + am33xx_cpsw_slaves[1].mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + am33xx_cpsw_slaves[1].mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + am33xx_cpsw_slaves[1].mac_addr[4] = mac_lo & 0xFF; + am33xx_cpsw_slaves[1].mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + /* Read MACID1 from eeprom if eFuse MACID is invalid */ + if (!is_valid_ether_addr(am33xx_cpsw_slaves[1].mac_addr)) { + for (i = 0; i < ETH_ALEN; i++) + am33xx_cpsw_slaves[1].mac_addr[i] = am33xx_macid1[i]; + } + + if (am33xx_evmid == IND_AUT_MTR_EVM) { + am33xx_cpsw_slaves[0].phy_id = "0:1e"; + am33xx_cpsw_slaves[1].phy_id = "0:00"; + } + + am33xx_cpsw_pdata.gigabit_en = gigen; + + + memcpy(am33xx_cpsw_pdata.mac_addr, + am33xx_cpsw_slaves[0].mac_addr, ETH_ALEN); + platform_device_register(&am33xx_cpsw_mdiodevice); + platform_device_register(&am33xx_cpsw_device); + + #define MII_MODE_ENABLE 0x0 +#define RMII_MODE_ENABLE 0x4 //5 +#define RGMII_MODE_ENABLE 0xA +#define MAC_MII_SEL 0x650 +#define SMA2_ADDR 0x1320 + + __raw_writel(RMII_MODE_ENABLE | 0xb0, //danm + AM33XX_CTRL_REGADDR(MAC_MII_SEL)); + + __raw_writel(0x0, //danm + AM33XX_CTRL_REGADDR(SMA2_ADDR)); + printk("%s gmii_sel 0x%x\n",__func__, + __raw_readl(AM33XX_CTRL_REGADDR(MAC_MII_SEL))); //danm + + + + + clk_add_alias(NULL, dev_name(&am33xx_cpsw_mdiodevice.dev), + NULL, &am33xx_cpsw_device.dev); } -#define AM33XX_D_CAN_RAM_BASE 0x1000 -#define AM33XX_D_CAN_NUM_MSG_OBJS 64 -#define AM33XX_D_CAN_VERSION 0x1 -#define AM33XX_CTL_DCAN_RAMINIT_OFFSET 0x644 -#define AM33XX_D_CAN_RAMINIT_START(n) (0x1 << n) +#define AM33XX_D_CAN_RAM_BASE 0x1000 +#define AM33XX_D_CAN_NUM_MSG_OBJS 64 +#define AM33XX_D_CAN_VERSION 0x1 +#define AM33XX_CTL_DCAN_RAMINIT_OFFSET 0x644 +#define AM33XX_D_CAN_RAMINIT_START(n) (0x1 << n) static void d_can_hw_raminit(unsigned int instance) { - u32 val; + u32 val; - /* Read the value */ - val = __raw_readl(AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET)); + /* Read the value */ + val = __raw_readl(AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET)); - /* Modify by setting "0" */ - val &= ~AM33XX_D_CAN_RAMINIT_START(instance); - __raw_writel(val, AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET)); + /* Modify by setting "0" */ + val &= ~AM33XX_D_CAN_RAMINIT_START(instance); + __raw_writel(val, AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET)); - /* Reset to one */ - val |= AM33XX_D_CAN_RAMINIT_START(instance); - __raw_writel(val, AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET)); + /* Reset to one */ + val |= AM33XX_D_CAN_RAMINIT_START(instance); + __raw_writel(val, AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET)); - /* Give some time delay for transition from 0 -> 1 */ - udelay(1); + /* Give some time delay for transition from 0 -> 1 */ + udelay(1); } static struct d_can_platform_data am33xx_evm_d_can0_pdata = { - .d_can_offset = 0, - .d_can_ram_offset = AM33XX_D_CAN_RAM_BASE, - .num_of_msg_objs = AM33XX_D_CAN_NUM_MSG_OBJS, - .dma_support = false, - .test_mode_enable = false, - .parity_check = false, - .fck_name = "dcan0_fck", - .ick_name = "dcan0_ick", - .version = AM33XX_D_CAN_VERSION, + .d_can_offset = 0, + .d_can_ram_offset = AM33XX_D_CAN_RAM_BASE, + .num_of_msg_objs = AM33XX_D_CAN_NUM_MSG_OBJS, + .dma_support = false, + .test_mode_enable = false, + .parity_check = false, + .fck_name = "dcan0_fck", + .ick_name = "dcan0_ick", + .version = AM33XX_D_CAN_VERSION, }; static struct resource am33xx_d_can0_resources[] = { - { - .start = AM33XX_D_CAN0_BASE, - .end = AM33XX_D_CAN0_BASE + 0x3FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "int0", - .start = AM33XX_IRQ_DCAN0_0, - .end = AM33XX_IRQ_DCAN0_0, - .flags = IORESOURCE_IRQ, - }, - { - .name = "int1", - .start = AM33XX_IRQ_DCAN0_1, - .end = AM33XX_IRQ_DCAN0_1, - .flags = IORESOURCE_IRQ, - }, + { + .start = AM33XX_D_CAN0_BASE, + .end = AM33XX_D_CAN0_BASE + 0x3FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "int0", + .start = AM33XX_IRQ_DCAN0_0, + .end = AM33XX_IRQ_DCAN0_0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "int1", + .start = AM33XX_IRQ_DCAN0_1, + .end = AM33XX_IRQ_DCAN0_1, + .flags = IORESOURCE_IRQ, + }, }; static struct platform_device am33xx_d_can0_device = { - .dev = { - .platform_data = &am33xx_evm_d_can0_pdata, - }, - .name = "d_can", - .id = 0, - .num_resources = ARRAY_SIZE(am33xx_d_can0_resources), - .resource = am33xx_d_can0_resources, + .dev = { + .platform_data = &am33xx_evm_d_can0_pdata, + }, + .name = "d_can", + .id = 0, + .num_resources = ARRAY_SIZE(am33xx_d_can0_resources), + .resource = am33xx_d_can0_resources, }; static struct resource am33xx_d_can1_resources[] = { - { - .start = AM33XX_D_CAN1_BASE, - .end = AM33XX_D_CAN1_BASE + 0x3FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "int0", - .start = AM33XX_IRQ_DCAN1_0, - .end = AM33XX_IRQ_DCAN1_0, - .flags = IORESOURCE_IRQ, - }, - { - .name = "int1", - .start = AM33XX_IRQ_DCAN1_1, - .end = AM33XX_IRQ_DCAN1_1, - .flags = IORESOURCE_IRQ, - }, + { + .start = AM33XX_D_CAN1_BASE, + .end = AM33XX_D_CAN1_BASE + 0x3FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "int0", + .start = AM33XX_IRQ_DCAN1_0, + .end = AM33XX_IRQ_DCAN1_0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "int1", + .start = AM33XX_IRQ_DCAN1_1, + .end = AM33XX_IRQ_DCAN1_1, + .flags = IORESOURCE_IRQ, + }, }; static struct d_can_platform_data am33xx_evm_d_can1_pdata = { - .d_can_offset = 0, - .d_can_ram_offset = AM33XX_D_CAN_RAM_BASE, - .num_of_msg_objs = AM33XX_D_CAN_NUM_MSG_OBJS, - .dma_support = false, - .test_mode_enable = false, - .parity_check = false, - .fck_name = "dcan1_fck", - .ick_name = "dcan1_ick", - .version = AM33XX_D_CAN_VERSION, + .d_can_offset = 0, + .d_can_ram_offset = AM33XX_D_CAN_RAM_BASE, + .num_of_msg_objs = AM33XX_D_CAN_NUM_MSG_OBJS, + .dma_support = false, + .test_mode_enable = false, + .parity_check = false, + .fck_name = "dcan1_fck", + .ick_name = "dcan1_ick", + .version = AM33XX_D_CAN_VERSION, }; static struct platform_device am33xx_d_can1_device = { - .dev = { - .platform_data = &am33xx_evm_d_can1_pdata, - }, - .name = "d_can", - .id = 1, - .num_resources = ARRAY_SIZE(am33xx_d_can1_resources), - .resource = am33xx_d_can1_resources, + .dev = { + .platform_data = &am33xx_evm_d_can1_pdata, + }, + .name = "d_can", + .id = 1, + .num_resources = ARRAY_SIZE(am33xx_d_can1_resources), + .resource = am33xx_d_can1_resources, }; void am33xx_d_can_init(unsigned int instance) { - switch (instance) { - case 0: - d_can_hw_raminit(instance); - platform_device_register(&am33xx_d_can0_device); - break; - case 1: - d_can_hw_raminit(instance); - platform_device_register(&am33xx_d_can1_device); - break; - default: - break; - } + switch (instance) { + case 0: + d_can_hw_raminit(instance); + platform_device_register(&am33xx_d_can0_device); + break; + case 1: + d_can_hw_raminit(instance); + platform_device_register(&am33xx_d_can1_device); + break; + default: + break; + } } #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) static int __init omap_init_wdt(void) { - int id = -1; - struct platform_device *pdev; - struct omap_hwmod *oh; - char *oh_name = "wd_timer2"; - char *dev_name = "omap_wdt"; - - if (!cpu_class_is_omap2()) - return 0; - - oh = omap_hwmod_lookup(oh_name); - if (!oh) { - pr_err("Could not look up wd_timer%d hwmod\n", id); - return -EINVAL; - } - - pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0); - WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n", - dev_name, oh->name); - return 0; + int id = -1; + struct platform_device *pdev; + struct omap_hwmod *oh; + char *oh_name = "wd_timer2"; + char *dev_name = "omap_wdt"; + + if (!cpu_class_is_omap2()) + return 0; + + oh = omap_hwmod_lookup(oh_name); + if (!oh) { + pr_err("Could not look up wd_timer%d hwmod\n", id); + return -EINVAL; + } + + pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0); + WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n", + dev_name, oh->name); + return 0; } subsys_initcall(omap_init_wdt); #endif diff --git a/arch/arm/mach-omap2/mux33xx.c b/arch/arm/mach-omap2/mux33xx.c index d71f188..6560a01 100644 --- a/arch/arm/mach-omap2/mux33xx.c +++ b/arch/arm/mach-omap2/mux33xx.c @@ -1,3 +1,5 @@ + + /* * AM33XX mux data * @@ -20,601 +22,601 @@ #ifdef CONFIG_OMAP_MUX -#define _AM33XX_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ -{ \ - .reg_offset = (AM33XX_CONTROL_PADCONF_##M0##_OFFSET), \ - .gpio = (g), \ - .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \ +#define _AM33XX_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ +{ \ + .reg_offset = (AM33XX_CONTROL_PADCONF_##M0##_OFFSET), \ + .gpio = (g), \ + .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \ } /* AM33XX pin mux super set */ static struct omap_mux __initdata am33xx_muxmodes[] = { - _AM33XX_MUXENTRY(GPMC_AD0, 0, - "gpmc_ad0", "mmc1_dat0", NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(GPMC_AD1, 0, - "gpmc_ad1", "mmc1_dat1", NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(GPMC_AD2, 0, - "gpmc_ad2", "mmc1_dat2", NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(GPMC_AD3, 0, - "gpmc_ad3", "mmc1_dat3", NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(GPMC_AD4, 0, - "gpmc_ad4", "mmc1_dat4", NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(GPMC_AD5, 0, - "gpmc_ad5", "mmc1_dat5", NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(GPMC_AD6, 0, - "gpmc_ad6", "mmc1_dat6", NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(GPMC_AD7, 0, - "gpmc_ad7", "mmc1_dat7", NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(GPMC_AD8, 0, - "gpmc_ad8", "lcd_data16", "mmc1_dat0", "mmc2_dat4", - NULL, NULL, NULL, "gpio0_22"), - _AM33XX_MUXENTRY(GPMC_AD9, 0, - "gpmc_ad9", "lcd_data17", "mmc1_dat1", "mmc2_dat5", - NULL, NULL, NULL, "gpio0_23"), - _AM33XX_MUXENTRY(GPMC_AD10, 0, - "gpmc_ad10", "lcd_data18", "mmc1_dat2", "mmc2_dat6", - NULL, NULL, NULL, "gpio0_26"), - _AM33XX_MUXENTRY(GPMC_AD11, 0, - "gpmc_ad11", "lcd_data19", "mmc1_dat3", "mmc2_dat7", - NULL, NULL, NULL, "gpio0_27"), - _AM33XX_MUXENTRY(GPMC_AD12, 0, - "gpmc_ad12", "lcd_data20", "mmc1_dat4", "mmc2_dat0", - NULL, NULL, NULL, "gpio1_12"), - _AM33XX_MUXENTRY(GPMC_AD13, 0, - "gpmc_ad13", "lcd_data21", "mmc1_dat5", "mmc2_dat1", - NULL, NULL, NULL, "gpio1_13"), - _AM33XX_MUXENTRY(GPMC_AD14, 0, - "gpmc_ad14", "lcd_data22", "mmc1_dat6", "mmc2_dat2", - NULL, NULL, NULL, "gpio1_14"), - _AM33XX_MUXENTRY(GPMC_AD15, 0, - "gpmc_ad15", "lcd_data23", "mmc1_dat7", "mmc2_dat3", - NULL, NULL, NULL, "gpio1_15"), - _AM33XX_MUXENTRY(GPMC_A0, 0, - "gpmc_a0", "mii2_txen", "rgmii2_tctl", "rmii2_txen", - NULL, NULL, NULL, "gpio1_16"), - _AM33XX_MUXENTRY(GPMC_A1, 0, - "gpmc_a1", "mii2_rxdv", "rgmii2_rctl", "mmc2_dat0", - NULL, NULL, NULL, "gpio1_17"), - _AM33XX_MUXENTRY(GPMC_A2, 0, - "gpmc_a2", "mii2_txd3", "rgmii2_td3", "mmc2_dat1", - NULL, NULL, NULL, "gpio1_18"), - _AM33XX_MUXENTRY(GPMC_A3, 0, - "gpmc_a3", "mii2_txd2", "rgmii2_td2", "mmc2_dat2", - NULL, NULL, NULL, "gpio1_19"), - _AM33XX_MUXENTRY(GPMC_A4, 0, - "gpmc_a4", "mii2_txd1", "rgmii2_td1", "rmii2_txd1", - "gpmc_a20", NULL, NULL, "gpio1_20"), - _AM33XX_MUXENTRY(GPMC_A5, 0, - "gpmc_a5", "mii2_txd0", "rgmii2_td0", "rmii2_txd0", - "gpmc_a21", NULL, NULL, "gpio1_21"), - _AM33XX_MUXENTRY(GPMC_A6, 0, - "gpmc_a6", "mii2_txclk", "rgmii2_tclk", "mmc2_dat4", - "gpmc_a22", NULL, NULL, "gpio1_22"), - _AM33XX_MUXENTRY(GPMC_A7, 0, - "gpmc_a7", "mii2_rxclk", "rgmii2_rclk", "mmc2_dat5", - NULL, NULL, NULL, "gpio1_23"), - _AM33XX_MUXENTRY(GPMC_A8, 0, - "gpmc_a8", "mii2_rxd3", "rgmii2_rd3", "mmc2_dat6", - NULL, NULL, "mcasp0_aclkx", "gpio1_24"), - _AM33XX_MUXENTRY(GPMC_A9, 0, - "gpmc_a9", "mii2_rxd2", "rgmii2_rd2", "mmc2_dat7", - NULL, NULL, "mcasp0_fsx", "gpio1_25"), - _AM33XX_MUXENTRY(GPMC_A10, 0, - "gpmc_a10", "mii2_rxd1", "rgmii2_rd1", "rmii2_rxd1", - NULL, NULL, "mcasp0_axr0", "gpio1_26"), - _AM33XX_MUXENTRY(GPMC_A11, 0, - "gpmc_a11", "mii2_rxd0", "rgmii2_rd0", "rmii2_rxd0", - NULL, NULL, "mcasp0_axr1", "gpio1_27"), - _AM33XX_MUXENTRY(GPMC_WAIT0, 0, - "gpmc_wait0", "mii2_crs", NULL, "rmii2_crs_dv", - "mmc1_sdcd", NULL, NULL, NULL), - _AM33XX_MUXENTRY(GPMC_WPN, 0, - "gpmc_wpn", "mii2_rxerr", NULL, "rmii2_rxerr", - "mmc2_sdcd", NULL, NULL, NULL), - _AM33XX_MUXENTRY(GPMC_BEN1, 0, - "gpmc_ben1", "mii2_col", NULL, "mmc2_dat3", - NULL, NULL, "mcasp0_aclkr", "gpio1_28"), - _AM33XX_MUXENTRY(GPMC_CSN0, 0, - "gpmc_csn0", NULL, NULL, NULL, - NULL, NULL, NULL, "mmc1_sdwp"), - _AM33XX_MUXENTRY(GPMC_CSN1, 0, - "gpmc_csn1", NULL, "mmc1_clk", NULL, - NULL, NULL, NULL, "gpio1_30"), - _AM33XX_MUXENTRY(GPMC_CSN2, 0, - "gpmc_csn2", NULL, "mmc1_cmd", NULL, - NULL, NULL, NULL, "gpio1_31"), - _AM33XX_MUXENTRY(GPMC_CSN3, 0, - "gpmc_csn3", NULL, NULL, "mmc2_cmd", - NULL, NULL, NULL, "gpio2_0"), - _AM33XX_MUXENTRY(GPMC_CLK, 0, - "gpmc_clk", "lcd_memory_clk_mux", NULL, "mmc2_clk", - NULL, NULL, "mcasp0_fsr", "gpio2_1"), - _AM33XX_MUXENTRY(GPMC_ADVN_ALE, 0, - "gpmc_advn_ale", NULL, NULL, NULL, - NULL, NULL, NULL, "mmc1_sdcd"), - _AM33XX_MUXENTRY(GPMC_OEN_REN, 0, - "gpmc_oen_ren", NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(GPMC_WEN, 0, - "gpmc_wen", NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(GPMC_BEN0_CLE, 0, - "gpmc_ben0_cle", NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(LCD_DATA0, 0, - "lcd_data0", "gpmc_a0", NULL, NULL, - NULL, NULL, NULL, "gpio2_6"), - _AM33XX_MUXENTRY(LCD_DATA1, 0, - "lcd_data1", "gpmc_a1", NULL, NULL, - NULL, NULL, NULL, "gpio2_7"), - _AM33XX_MUXENTRY(LCD_DATA2, 0, - "lcd_data2", "gpmc_a2", NULL, NULL, - NULL, NULL, NULL, "gpio2_8"), - _AM33XX_MUXENTRY(LCD_DATA3, 0, - "lcd_data3", "gpmc_a3", NULL, NULL, - NULL, NULL, NULL, "gpio2_9"), - _AM33XX_MUXENTRY(LCD_DATA4, 0, - "lcd_data4", "gpmc_a4", NULL, NULL, - NULL, NULL, NULL, "gpio2_10"), - _AM33XX_MUXENTRY(LCD_DATA5, 0, - "lcd_data5", "gpmc_a5", NULL, NULL, - NULL, NULL, NULL, "gpio2_11"), - _AM33XX_MUXENTRY(LCD_DATA6, 0, - "lcd_data6", "gpmc_a6", NULL, NULL, - NULL, NULL, NULL, "gpio2_12"), - _AM33XX_MUXENTRY(LCD_DATA7, 0, - "lcd_data7", "gpmc_a7", NULL, NULL, - NULL, NULL, NULL, "gpio2_13"), - _AM33XX_MUXENTRY(LCD_DATA8, 0, - "lcd_data8", "gpmc_a12", NULL, "mcasp0_aclkx", - NULL, NULL, "uart2_ctsn", "gpio2_14"), - _AM33XX_MUXENTRY(LCD_DATA9, 0, - "lcd_data9", "gpmc_a13", NULL, "mcasp0_fsx", - NULL, NULL, "uart2_rtsn", "gpio2_15"), - _AM33XX_MUXENTRY(LCD_DATA10, 0, - "lcd_data10", "gpmc_a14", NULL, "mcasp0_axr0", - NULL, NULL, NULL, "gpio2_16"), - _AM33XX_MUXENTRY(LCD_DATA11, 0, - "lcd_data11", "gpmc_a15", NULL, "mcasp0_ahclkr", - "mcasp0_axr2", NULL, NULL, "gpio2_17"), - _AM33XX_MUXENTRY(LCD_DATA12, 0, - "lcd_data12", "gpmc_a16", NULL, "mcasp0_aclkr", - "mcasp0_axr2", NULL, NULL, "gpio0_8"), - _AM33XX_MUXENTRY(LCD_DATA13, 0, - "lcd_data13", "gpmc_a17", NULL, "mcasp0_fsr", - "mcasp0_axr3", NULL, NULL, "gpio0_9"), - _AM33XX_MUXENTRY(LCD_DATA14, 0, - "lcd_data14", "gpmc_a18", NULL, "mcasp0_axr1", - NULL, NULL, NULL, "gpio0_10"), - _AM33XX_MUXENTRY(LCD_DATA15, 0, - "lcd_data15", "gpmc_a19", NULL, "mcasp0_ahclkx", - "mcasp0_axr3", NULL, NULL, "gpio0_11"), - _AM33XX_MUXENTRY(LCD_VSYNC, 0, - "lcd_vsync", NULL, NULL, NULL, - NULL, NULL, NULL, "gpio2_22"), - _AM33XX_MUXENTRY(LCD_HSYNC, 0, - "lcd_hsync", NULL, NULL, NULL, - NULL, NULL, NULL, "gpio2_23"), - _AM33XX_MUXENTRY(LCD_PCLK, 0, - "lcd_pclk", NULL, NULL, NULL, - NULL, NULL, NULL, "gpio2_24"), - _AM33XX_MUXENTRY(LCD_AC_BIAS_EN, 0, - "lcd_ac_bias_en", NULL, NULL, NULL, - NULL, NULL, NULL, "gpio2_25"), - _AM33XX_MUXENTRY(MMC0_DAT3, 0, - "mmc0_dat3", NULL, NULL, NULL, - NULL, NULL, NULL, "gpio2_26"), - _AM33XX_MUXENTRY(MMC0_DAT2, 0, - "mmc0_dat2", NULL, NULL, NULL, - NULL, NULL, NULL, "gpio2_27"), - _AM33XX_MUXENTRY(MMC0_DAT1, 0, - "mmc0_dat1", NULL, NULL, NULL, - NULL, NULL, NULL, "gpio2_28"), - _AM33XX_MUXENTRY(MMC0_DAT0, 0, - "mmc0_dat0", NULL, NULL, NULL, - NULL, NULL, NULL, "gpio2_29"), - _AM33XX_MUXENTRY(MMC0_CLK, 0, - "mmc0_clk", NULL, NULL, NULL, - NULL, NULL, NULL, "gpio2_30"), - _AM33XX_MUXENTRY(MMC0_CMD, 0, - "mmc0_cmd", NULL, NULL, NULL, - NULL, NULL, NULL, "gpio2_31"), - _AM33XX_MUXENTRY(MII1_COL, 0, - "mii1_col", "rmii2_refclk", "spi1_sclk", NULL, - "mcasp1_axr2", "mmc2_dat3", "mcasp0_axr2", "gpio3_0"), - _AM33XX_MUXENTRY(MII1_CRS, 0, - "mii1_crs", "rmii1_crs_dv", "spi1_d0", "i2c1_sda", - "mcasp1_aclkx", NULL, NULL, NULL), - _AM33XX_MUXENTRY(MII1_RXERR, 0, - "mii1_rxerr", "rmii1_rxerr", "spi1_d1", "i2c1_scl", - "mcasp1_fsx", NULL, NULL, NULL), - _AM33XX_MUXENTRY(MII1_TXEN, 0, - "mii1_txen", "rmii1_txen", "rgmii1_tctl", NULL, - "mcasp1_axr0", NULL, "mmc2_cmd", "gpio3_3"), - _AM33XX_MUXENTRY(MII1_RXDV, 0, - "mii1_rxdv", NULL, "rgmii1_rctl", NULL, - "mcasp1_aclx", "mmc2_dat0", "mcasp0_aclkr", NULL), - _AM33XX_MUXENTRY(MII1_TXD3, 0, - "mii1_txd3", "d_can0_tx", "rgmii1_td3", NULL, - "mcasp1_fsx", "mmc2_dat1", "mcasp0_fsr", NULL), - _AM33XX_MUXENTRY(MII1_TXD2, 0, - "mii1_txd2", "d_can0_rx", "rgmii1_td2", NULL, - "mcasp1_axr0", "mmc2_dat2", "mcasp0_ahclkx", NULL), - _AM33XX_MUXENTRY(MII1_TXD1, 0, - "mii1_txd1", "rmii1_txd1", "rgmii1_td1", "mcasp1_fsr", - "mcasp1_axr1", NULL, "mmc1_cmd", NULL), - _AM33XX_MUXENTRY(MII1_TXD0, 0, - "mii1_txd0", "rmii1_txd0", "rgmii1_td0", "mcasp1_axr2", - "mcasp1_aclkr", NULL, "mmc1_clk", "gpio0_28"), - _AM33XX_MUXENTRY(MII1_TXCLK, 0, - "mii1_txclk", NULL, "rgmii1_tclk", "mmc0_dat7", - "mmc1_dat0", NULL, "mcasp0_aclkx", "gpio3_9"), - _AM33XX_MUXENTRY(MII1_RXCLK, 0, - "mii1_rxclk", NULL, "rgmii1_rclk", "mmc0_dat6", - "mmc1_dat1", NULL, "mcasp0_fsx", NULL), - _AM33XX_MUXENTRY(MII1_RXD3, 0, - "mii1_rxd3", "uart3_rxd", "rgmii1_rd3", "mmc0_dat5", - "mmc1_dat2", "uart1_dtrn", "mcasp0_axr0", "gpio2_18"), - _AM33XX_MUXENTRY(MII1_RXD2, 0, - "mii1_rxd2", "uart3_txd", "rgmii1_rd2", "mmc0_dat4", - "mmc1_dat3", "uart1_rin", "mcasp0_axr1", "gpio2_19"), - _AM33XX_MUXENTRY(MII1_RXD1, 0, - "mii1_rxd1", "rmii1_rxd1", "rgmii1_rd1", "mcasp1_axr3", - "mcasp1_fsr", NULL, "mmc2_clk", "gpio2_20"), - _AM33XX_MUXENTRY(MII1_RXD0, 0, - "mii1_rxd0", "rmii1_rxd0", "rgmii1_rd0", "mcasp1_ahclkx", - "mcasp1_ahclkr", "mcasp1_aclkr", "mcasp0_axr3", NULL), - _AM33XX_MUXENTRY(MII1_REFCLK, 0, - "rmii1_refclk", NULL, "spi1_cs0", NULL, - "mcasp1_axr3", "mmc0_pow", "mcasp1_ahclkx", "gpio0_29"), - _AM33XX_MUXENTRY(MDIO_DATA, 0, - "mdio_data", NULL, NULL, NULL, - "mmc0_sdcd", "mmc1_cmd", "mmc2_cmd", NULL), - _AM33XX_MUXENTRY(MDIO_CLK, 0, - "mdio_clk", NULL, NULL, NULL, - "mmc0_sdwp", "mmc1_clk", "mmc2_clk", NULL), - _AM33XX_MUXENTRY(SPI0_SCLK, 0, - "spi0_sclk", "uart2_rxd", NULL, NULL, - NULL, NULL, NULL, "gpio0_2"), - _AM33XX_MUXENTRY(SPI0_D0, 0, - "spi0_d0", "uart2_txd", NULL, NULL, - NULL, NULL, NULL, "gpio0_3"), - _AM33XX_MUXENTRY(SPI0_D1, 0, - "spi0_d1", "mmc1_sdwp", "i2c1_sda", NULL, - NULL, NULL, NULL, "gpio0_4"), - _AM33XX_MUXENTRY(SPI0_CS0, 0, - "spi0_cs0", "mmc2_sdwp", "i2c1_scl", NULL, - NULL, NULL, NULL, "gpio0_5"), - _AM33XX_MUXENTRY(SPI0_CS1, 0, - "spi0_cs1", "uart3_rxd", NULL, "mmc0_pow", - NULL, "mmc0_sdcd", NULL, "gpio0_6"), - _AM33XX_MUXENTRY(ECAP0_IN_PWM0_OUT, 0, - "ecap0_in_pwm0_out", "uart3_txd", "spi1_cs1", NULL, - "spi1_sclk", "mmc0_sdwp", NULL, "gpio0_7"), - _AM33XX_MUXENTRY(UART0_CTSN, 0, - "uart0_ctsn", "uart4_rxd", "d_can1_tx", "i2c1_sda", - "spi1_d0", "timer7", "pr1_edc_sync0_out", "gpio1_8"), - _AM33XX_MUXENTRY(UART0_RTSN, 0, - "uart0_rtsn", "uart4_txd", "d_can1_rx", "i2c1_scl", - "spi1_d1", "spi1_cs0", "pr1_edc_sync1_out", "gpio1_9"), - _AM33XX_MUXENTRY(UART0_RXD, 0, - "uart0_rxd", "spi1_cs0", "d_can0_tx", NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(UART0_TXD, 0, - "uart0_txd", "spi1_cs1", "d_can0_rx", NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(UART1_CTSN, 0, - "uart1_ctsn", NULL, NULL, "i2c2_sda", - "spi1_cs0", NULL, NULL, NULL), - _AM33XX_MUXENTRY(UART1_RTSN, 0, - "uart1_rtsn", NULL, NULL, "i2c2_scl", - "spi1_cs1", NULL, NULL, NULL), - _AM33XX_MUXENTRY(UART1_RXD, 0, - "uart1_rxd", "mmc1_sdwp", "d_can1_tx", NULL, - NULL, "pr1_uart0_rxd_mux1", NULL, "gpio0_14"), - _AM33XX_MUXENTRY(UART1_TXD, 0, - "uart1_txd", "mmc2_sdwp", "d_can1_rx", NULL, - NULL, "pr1_uart0_txd_mux1", NULL, "gpio0_15"), - _AM33XX_MUXENTRY(I2C0_SDA, 0, - "i2c0_sda", NULL, NULL, NULL, - NULL, NULL, NULL, "gpio3_5"), - _AM33XX_MUXENTRY(I2C0_SCL, 0, - "i2c0_scl", NULL, NULL, NULL, - NULL, NULL, NULL, "gpio3_6"), - _AM33XX_MUXENTRY(MCASP0_ACLKX, 0, - "mcasp0_aclkx", "ehrpwm0a", NULL, "spi1_sclk", - "mmc0_sdcd", "pr1_pru0_pru_r30_0", "pr1_pru0_pru_r31_0", - "gpio3_14"), - _AM33XX_MUXENTRY(MCASP0_FSX, 0, - "mcasp0_fsx", NULL, NULL, "spi1_d0", - "mmc1_sdcd", NULL, NULL, NULL), - _AM33XX_MUXENTRY(MCASP0_AXR0, 0, - "mcasp0_axr0", NULL, NULL, "spi1_d1", - "mmc2_sdcd", NULL, NULL, NULL), - _AM33XX_MUXENTRY(MCASP0_AHCLKR, 0, - "mcasp0_ahclkr", NULL, "mcasp0_axr2", "spi1_cs0", - NULL, NULL, NULL, "gpio3_17"), - _AM33XX_MUXENTRY(MCASP0_ACLKR, 0, - "mcasp0_aclkr", NULL, "mcasp0_axr2", "mcasp1_aclkx", - "mmc0_sdwp", NULL, NULL, "gpio3_18"), - _AM33XX_MUXENTRY(MCASP0_FSR, 0, - "mcasp0_fsr", NULL, "mcasp0_axr3", "mcasp1_fsx", - NULL, "pr1_pru0_pru_r30_5", NULL, "gpio3_19"), - _AM33XX_MUXENTRY(MCASP0_AXR1, 0, - "mcasp0_axr1", NULL, NULL, "mcasp1_axr0", - NULL, NULL, NULL, "gpio3_20"), - _AM33XX_MUXENTRY(MCASP0_AHCLKX, 0, - "mcasp0_ahclkx", "mcasp0_axr3", NULL, "mcasp1_axr1", - NULL, NULL, NULL, "gpio3_21"), - _AM33XX_MUXENTRY(XDMA_EVENT_INTR0, 0, - "xdma_event_intr0", NULL, NULL, NULL, - "spi1_cs1", NULL, NULL, "gpio0_19"), - _AM33XX_MUXENTRY(XDMA_EVENT_INTR1, 0, - "xdma_event_intr1", NULL, NULL, "clkout2", - NULL, NULL, NULL, "gpio0_20"), - _AM33XX_MUXENTRY(WARMRSTN, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(PWRONRSTN, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(NMIN, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(XTALIN, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(XTALOUT, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(TMS, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(TDI, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(TDO, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(TCK, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(TRSTN, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(EMU0, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(EMU1, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(RTC_XTALIN, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(RTC_XTALOUT, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(RTC_PWRONRSTN, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(PMIC_POWER_EN, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(EXT_WAKEUP, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(USB0_DRVVBUS, 0, - "usb0_drvvbus", NULL, NULL, NULL, - NULL, NULL, NULL, "gpio0_18"), - _AM33XX_MUXENTRY(USB1_DRVVBUS, 0, - "usb1_drvvbus", NULL, NULL, NULL, - NULL, NULL, NULL, "gpio3_13"), - _AM33XX_MUXENTRY(DDR_RESETN, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_CSN0, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_CKE, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_CK, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_CKN, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_CASN, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_RASN, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_WEN, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_BA0, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_BA1, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_BA2, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_A0, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_A1, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_A2, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_A3, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_A4, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_A5, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_A6, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_A7, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_A8, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_A9, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_A10, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_A11, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_A12, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_A13, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_A14, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_A15, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_ODT, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_D0, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_D1, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_D2, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_D3, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_D4, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_D5, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_D6, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_D7, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_D8, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_D9, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_D10, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_D11, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_D12, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_D13, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_D14, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_D15, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_DQM0, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_DQM1, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_DQS0, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_DQSN0, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_DQS1, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_DQSN1, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_VREF, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(DDR_VTP, 0, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(AIN0, 0, - "ain0", NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(AIN1, 0, - "ain1", NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(AIN2, 0, - "ain2", NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(AIN3, 0, - "ain3", NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(AIN4, 0, - "ain4", NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(AIN5, 0, - "ain5", NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(AIN6, 0, - "ain6", NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(AIN7, 0, - "ain7", NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(VREFP, 0, - "vrefp", NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _AM33XX_MUXENTRY(VREFN, 0, - "vrefn", NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - { .reg_offset = OMAP_MUX_TERMINATOR }, + _AM33XX_MUXENTRY(GPMC_AD0, 0, + "gpmc_ad0", "mmc1_dat0", NULL, NULL, + NULL, NULL, NULL, "gpio1_0"), // danm + _AM33XX_MUXENTRY(GPMC_AD1, 0, + "gpmc_ad1", "mmc1_dat1", NULL, NULL, + NULL, NULL, NULL, "gpio1_1"), + _AM33XX_MUXENTRY(GPMC_AD2, 0, + "gpmc_ad2", "mmc1_dat2", NULL, NULL, + NULL, NULL, NULL, "gpio1_2"), + _AM33XX_MUXENTRY(GPMC_AD3, 0, + "gpmc_ad3", "mmc1_dat3", NULL, NULL, + NULL, NULL, NULL, "gpio1_3"), + _AM33XX_MUXENTRY(GPMC_AD4, 0, + "gpmc_ad4", "mmc1_dat4", NULL, NULL, + NULL, NULL, NULL, "gpio1_4"), + _AM33XX_MUXENTRY(GPMC_AD5, 0, + "gpmc_ad5", "mmc1_dat5", NULL, NULL, + NULL, NULL, NULL, "gpio1_5"), + _AM33XX_MUXENTRY(GPMC_AD6, 0, + "gpmc_ad6", "mmc1_dat6", NULL, NULL, + NULL, NULL, NULL, "gpio1_6"), + _AM33XX_MUXENTRY(GPMC_AD7, 0, + "gpmc_ad7", "mmc1_dat7", NULL, NULL, + NULL, NULL, NULL, "gpio1_7"), + _AM33XX_MUXENTRY(GPMC_AD8, 0, + "gpmc_ad8", "lcd_data16", "mmc1_dat0", "mmc2_dat4", + NULL, NULL, NULL, "gpio0_22"), + _AM33XX_MUXENTRY(GPMC_AD9, 0, + "gpmc_ad9", "lcd_data17", "mmc1_dat1", "mmc2_dat5", + "ehrpwm2B", NULL, NULL, "gpio0_23"), + _AM33XX_MUXENTRY(GPMC_AD10, 0, + "gpmc_ad10", "lcd_data18", "mmc1_dat2", "mmc2_dat6", + NULL, NULL, NULL, "gpio0_26"), + _AM33XX_MUXENTRY(GPMC_AD11, 0, + "gpmc_ad11", "lcd_data19", "mmc1_dat3", "mmc2_dat7", + NULL, NULL, NULL, "gpio0_27"), + _AM33XX_MUXENTRY(GPMC_AD12, 0, + "gpmc_ad12", "lcd_data20", "mmc1_dat4", "mmc2_dat0", + NULL, NULL, NULL, "gpio1_12"), + _AM33XX_MUXENTRY(GPMC_AD13, 0, + "gpmc_ad13", "lcd_data21", "mmc1_dat5", "mmc2_dat1", + NULL, NULL, NULL, "gpio1_13"), + _AM33XX_MUXENTRY(GPMC_AD14, 0, + "gpmc_ad14", "lcd_data22", "mmc1_dat6", "mmc2_dat2", + NULL, NULL, NULL, "gpio1_14"), + _AM33XX_MUXENTRY(GPMC_AD15, 0, + "gpmc_ad15", "lcd_data23", "mmc1_dat7", "mmc2_dat3", + NULL, NULL, NULL, "gpio1_15"), + _AM33XX_MUXENTRY(GPMC_A0, 0, + "gpmc_a0", "mii2_txen", "rgmii2_tctl", "rmii2_txen", + NULL, NULL, NULL, "gpio1_16"), + _AM33XX_MUXENTRY(GPMC_A1, 0, + "gpmc_a1", "mii2_rxdv", "rgmii2_rctl", "mmc2_dat0", + NULL, NULL, NULL, "gpio1_17"), + _AM33XX_MUXENTRY(GPMC_A2, 0, + "gpmc_a2", "mii2_txd3", "rgmii2_td3", "mmc2_dat1", + NULL, NULL, NULL, "gpio1_18"), + _AM33XX_MUXENTRY(GPMC_A3, 0, + "gpmc_a3", "mii2_txd2", "rgmii2_td2", "mmc2_dat2", + NULL, NULL, NULL, "gpio1_19"), + _AM33XX_MUXENTRY(GPMC_A4, 0, + "gpmc_a4", "mii2_txd1", "rgmii2_td1", "rmii2_txd1", + "gpmc_a20", NULL, NULL, "gpio1_20"), + _AM33XX_MUXENTRY(GPMC_A5, 0, + "gpmc_a5", "mii2_txd0", "rgmii2_td0", "rmii2_txd0", + "gpmc_a21", NULL, NULL, "gpio1_21"), + _AM33XX_MUXENTRY(GPMC_A6, 0, + "gpmc_a6", "mii2_txclk", "rgmii2_tclk", "mmc2_dat4", + "gpmc_a22", NULL, NULL, "gpio1_22"), + _AM33XX_MUXENTRY(GPMC_A7, 0, + "gpmc_a7", "mii2_rxclk", "rgmii2_rclk", "mmc2_dat5", + NULL, NULL, NULL, "gpio1_23"), + _AM33XX_MUXENTRY(GPMC_A8, 0, + "gpmc_a8", "mii2_rxd3", "rgmii2_rd3", "mmc2_dat6", + NULL, NULL, "mcasp0_aclkx", "gpio1_24"), + _AM33XX_MUXENTRY(GPMC_A9, 0, + "gpmc_a9", "mii2_rxd2", "rgmii2_rd2", "mmc2_dat7", + NULL, NULL, "mcasp0_fsx", "gpio1_25"), + _AM33XX_MUXENTRY(GPMC_A10, 0, + "gpmc_a10", "mii2_rxd1", "rgmii2_rd1", "rmii2_rxd1", + NULL, NULL, "mcasp0_axr0", "gpio1_26"), + _AM33XX_MUXENTRY(GPMC_A11, 0, + "gpmc_a11", "mii2_rxd0", "rgmii2_rd0", "rmii2_rxd0", + NULL, NULL, "mcasp0_axr1", "gpio1_27"), + _AM33XX_MUXENTRY(GPMC_WAIT0, 0, + "gpmc_wait0", "mii2_crs", NULL, "rmii2_crs_dv", + "mmc1_sdcd", NULL, NULL, "gpio0_30"), + _AM33XX_MUXENTRY(GPMC_WPN, 0, + "gpmc_wpn", "mii2_rxerr", NULL, "rmii2_rxerr", + "mmc2_sdcd", NULL, NULL, "gpio0_31"), + _AM33XX_MUXENTRY(GPMC_BEN1, 0, + "gpmc_ben1", "mii2_col", NULL, "mmc2_dat3", + NULL, NULL, "mcasp0_aclkr", "gpio1_28"), + _AM33XX_MUXENTRY(GPMC_CSN0, 0, + "gpmc_csn0", NULL, NULL, NULL, + NULL, NULL, NULL, "gpio1_29"), + _AM33XX_MUXENTRY(GPMC_CSN1, 0, + "gpmc_csn1", NULL, "mmc1_clk", NULL, + NULL, NULL, NULL, "gpio1_30"), + _AM33XX_MUXENTRY(GPMC_CSN2, 0, + "gpmc_csn2", NULL, "mmc1_cmd", NULL, + NULL, NULL, NULL, "gpio1_31"), + _AM33XX_MUXENTRY(GPMC_CSN3, 0, + "gpmc_csn3", NULL, "rmii2_crs_dv", "mmc2_cmd", + NULL, NULL, NULL, "gpio2_0"), + _AM33XX_MUXENTRY(GPMC_CLK, 0, + "gpmc_clk", "lcd_memory_clk_mux", NULL, "mmc2_clk", + NULL, NULL, "mcasp0_fsr", "gpio2_1"), + _AM33XX_MUXENTRY(GPMC_ADVN_ALE, 0, + "gpmc_advn_ale", NULL, NULL, NULL, + NULL, NULL, NULL, "mmc1_sdcd"), + _AM33XX_MUXENTRY(GPMC_OEN_REN, 0, + "gpmc_oen_ren", NULL, NULL, NULL, + NULL, NULL, NULL, "gpio2_3"), + _AM33XX_MUXENTRY(GPMC_WEN, 0, + "gpmc_wen", NULL, NULL, NULL, + NULL, NULL, NULL, "gpio2_4"), + _AM33XX_MUXENTRY(GPMC_BEN0_CLE, 0, + "gpmc_ben0_cle", NULL, NULL, NULL, + NULL, NULL, NULL, "gpio2_5"), + _AM33XX_MUXENTRY(LCD_DATA0, 0, + "lcd_data0", "gpmc_a0", NULL, NULL, + NULL, NULL, NULL, "gpio2_6"), + _AM33XX_MUXENTRY(LCD_DATA1, 0, + "lcd_data1", "gpmc_a1", NULL, NULL, + NULL, NULL, NULL, "gpio2_7"), + _AM33XX_MUXENTRY(LCD_DATA2, 0, + "lcd_data2", "gpmc_a2", NULL, NULL, + NULL, NULL, NULL, "gpio2_8"), + _AM33XX_MUXENTRY(LCD_DATA3, 0, + "lcd_data3", "gpmc_a3", NULL, NULL, + NULL, NULL, NULL, "gpio2_9"), + _AM33XX_MUXENTRY(LCD_DATA4, 0, + "lcd_data4", "gpmc_a4", NULL, NULL, + NULL, NULL, NULL, "gpio2_10"), + _AM33XX_MUXENTRY(LCD_DATA5, 0, + "lcd_data5", "gpmc_a5", NULL, NULL, + NULL, NULL, NULL, "gpio2_11"), + _AM33XX_MUXENTRY(LCD_DATA6, 0, + "lcd_data6", "gpmc_a6", NULL, NULL, + NULL, NULL, NULL, "gpio2_12"), + _AM33XX_MUXENTRY(LCD_DATA7, 0, + "lcd_data7", "gpmc_a7", NULL, NULL, + NULL, NULL, NULL, "gpio2_13"), + _AM33XX_MUXENTRY(LCD_DATA8, 0, + "lcd_data8", "gpmc_a12", NULL, "mcasp0_aclkx", + "uart5_txd", NULL, "uart2_ctsn", "gpio2_14"), + _AM33XX_MUXENTRY(LCD_DATA9, 0, + "lcd_data9", "gpmc_a13", NULL, "mcasp0_fsx", + "uart5_rxd", NULL, "uart2_rtsn", "gpio2_15"), + _AM33XX_MUXENTRY(LCD_DATA10, 0, + "lcd_data10", "gpmc_a14", NULL, "mcasp0_axr0", + NULL, NULL, NULL, "gpio2_16"), + _AM33XX_MUXENTRY(LCD_DATA11, 0, + "lcd_data11", "gpmc_a15", NULL, "mcasp0_ahclkr", + "mcasp0_axr2", NULL, NULL, "gpio2_17"), + _AM33XX_MUXENTRY(LCD_DATA12, 0, + "lcd_data12", "gpmc_a16", NULL, "mcasp0_aclkr", + "mcasp0_axr2", NULL, NULL, "gpio0_8"), + _AM33XX_MUXENTRY(LCD_DATA13, 0, + "lcd_data13", "gpmc_a17", NULL, "mcasp0_fsr", + "mcasp0_axr3", NULL, NULL, "gpio0_9"), + _AM33XX_MUXENTRY(LCD_DATA14, 0, + "lcd_data14", "gpmc_a18", NULL, "mcasp0_axr1", + NULL, NULL, NULL, "gpio0_10"), + _AM33XX_MUXENTRY(LCD_DATA15, 0, + "lcd_data15", "gpmc_a19", NULL, "mcasp0_ahclkx", + "mcasp0_axr3", NULL, NULL, "gpio0_11"), + _AM33XX_MUXENTRY(LCD_VSYNC, 0, + "lcd_vsync", NULL, NULL, NULL, + NULL, NULL, NULL, "gpio2_22"), + _AM33XX_MUXENTRY(LCD_HSYNC, 0, + "lcd_hsync", NULL, NULL, NULL, + NULL, NULL, NULL, "gpio2_23"), + _AM33XX_MUXENTRY(LCD_PCLK, 0, + "lcd_pclk", NULL, NULL, NULL, + NULL, NULL, NULL, "gpio2_24"), + _AM33XX_MUXENTRY(LCD_AC_BIAS_EN, 0, + "lcd_ac_bias_en", NULL, NULL, NULL, + NULL, NULL, NULL, "gpio2_25"), + _AM33XX_MUXENTRY(MMC0_DAT3, 0, + "mmc0_dat3", NULL, NULL, NULL, + NULL, NULL, NULL, "gpio2_26"), + _AM33XX_MUXENTRY(MMC0_DAT2, 0, + "mmc0_dat2", NULL, NULL, NULL, + NULL, NULL, NULL, "gpio2_27"), + _AM33XX_MUXENTRY(MMC0_DAT1, 0, + "mmc0_dat1", NULL, NULL, NULL, + NULL, NULL, NULL, "gpio2_28"), + _AM33XX_MUXENTRY(MMC0_DAT0, 0, + "mmc0_dat0", NULL, NULL, NULL, + NULL, NULL, NULL, "gpio2_29"), + _AM33XX_MUXENTRY(MMC0_CLK, 0, // skyline danm + "mmc0_clk", "gpmc_a24", "uart3_ctsn", "uart2_rxd", + NULL, NULL, NULL, "gpio2_30"), + _AM33XX_MUXENTRY(MMC0_CMD, 0, // skyline danm + "mmc0_cmd", "gpmc_a25", "uart3_rtsn", "uart2_txd", + NULL, NULL, NULL, "gpio2_31"), + _AM33XX_MUXENTRY(MII1_COL, 0, + "mii1_col", "rmii2_refclk", "spi1_sclk", NULL, + "mcasp1_axr2", "mmc2_dat3", "mcasp0_axr2", "gpio3_0"), + _AM33XX_MUXENTRY(MII1_CRS, 0, + "mii1_crs", "rmii1_crs_dv", "spi1_d0", "i2c1_sda", + "mcasp1_aclkx", NULL, NULL, "gpio3_1"), + _AM33XX_MUXENTRY(MII1_RXERR, 0, + "mii1_rxerr", "rmii1_rxerr", "spi1_d1", "i2c1_scl", + "mcasp1_fsx", NULL, NULL, "gpio3_2"), + _AM33XX_MUXENTRY(MII1_TXEN, 0, + "mii1_txen", "rmii1_txen", "rgmii1_tctl", NULL, + "mcasp1_axr0", NULL, "mmc2_cmd", "gpio3_3"), + _AM33XX_MUXENTRY(MII1_RXDV, 0, + "mii1_rxdv", NULL, "rgmii1_rctl", NULL, + "mcasp1_aclx", "mmc2_dat0", "mcasp0_aclkr", "gpio3_4"), + _AM33XX_MUXENTRY(MII1_TXD3, 0, + "mii1_txd3", "d_can0_tx", "rgmii1_td3", "uart4_rxd", + "mcasp1_fsx", "mmc2_dat1", "mcasp0_fsr", "gpio0_16"), + _AM33XX_MUXENTRY(MII1_TXD2, 0, + "mii1_txd2", "d_can0_rx", "rgmii1_td2", "uart4_txd", + "mcasp1_axr0", "mmc2_dat2", "mcasp0_ahclkx", "gpio0_17"), + _AM33XX_MUXENTRY(MII1_TXD1, 0, + "mii1_txd1", "rmii1_txd1", "rgmii1_td1", "mcasp1_fsr", + "mcasp1_axr1", NULL, "mmc1_cmd", "gpio0_21"), + _AM33XX_MUXENTRY(MII1_TXD0, 0, + "mii1_txd0", "rmii1_txd0", "rgmii1_td0", "mcasp1_axr2", + "mcasp1_aclkr", NULL, "mmc1_clk", "gpio0_28"), + _AM33XX_MUXENTRY(MII1_TXCLK, 0, + "mii1_txclk", NULL, "rgmii1_tclk", "mmc0_dat7", + "mmc1_dat0", "uart1_dcdn", "mcasp0_aclkx", "gpio3_9"), + _AM33XX_MUXENTRY(MII1_RXCLK, 0, + "mii1_rxclk", NULL, "rgmii1_rclk", "mmc0_dat6", + "mmc1_dat1", "uart1_dsrn", "mcasp0_fsx", "gpio3_10"), + _AM33XX_MUXENTRY(MII1_RXD3, 0, + "mii1_rxd3", "uart3_rxd", "rgmii1_rd3", "mmc0_dat5", + "mmc1_dat2", "uart1_dtrn", "mcasp0_axr0", "gpio2_18"), + _AM33XX_MUXENTRY(MII1_RXD2, 0, + "mii1_rxd2", "uart3_txd", "rgmii1_rd2", "mmc0_dat4", + "mmc1_dat3", "uart1_rin", "mcasp0_axr1", "gpio2_19"), + _AM33XX_MUXENTRY(MII1_RXD1, 0, + "mii1_rxd1", "rmii1_rxd1", "rgmii1_rd1", "mcasp1_axr3", + "mcasp1_fsr", NULL, "mmc2_clk", "gpio2_20"), + _AM33XX_MUXENTRY(MII1_RXD0, 0, + "mii1_rxd0", "rmii1_rxd0", "rgmii1_rd0", "mcasp1_ahclkx", + "mcasp1_ahclkr", "mcasp1_aclkr", "mcasp0_axr3", "gpio2_21"), + _AM33XX_MUXENTRY(MII1_REFCLK, 0, + "rmii1_refclk", NULL, "spi1_cs0", NULL, + "mcasp1_axr3", "mmc0_pow", "mcasp1_ahclkx", "gpio0_29"), + _AM33XX_MUXENTRY(MDIO_DATA, 0, + "mdio_data", NULL, NULL, NULL, + "mmc0_sdcd", "mmc1_cmd", "mmc2_cmd", "gpio0_0"), + _AM33XX_MUXENTRY(MDIO_CLK, 0, + "mdio_clk", NULL, NULL, NULL, + "mmc0_sdwp", "mmc1_clk", "mmc2_clk", "gpio0_1"), + _AM33XX_MUXENTRY(SPI0_SCLK, 0, + "spi0_sclk", "uart2_rxd", "i2c2_sda", NULL, + NULL, NULL, NULL, "gpio0_2"), + _AM33XX_MUXENTRY(SPI0_D0, 0, + "spi0_d0", "uart2_txd", "i2c2_scl", NULL, + NULL, NULL, NULL, "gpio0_3"), + _AM33XX_MUXENTRY(SPI0_D1, 0, + "spi0_d1", "mmc1_sdwp", "i2c1_sda", NULL, + NULL, NULL, NULL, "gpio0_4"), + _AM33XX_MUXENTRY(SPI0_CS0, 0, + "spi0_cs0", "mmc2_sdwp", "i2c1_scl", NULL, + NULL, NULL, NULL, "gpio0_5"), + _AM33XX_MUXENTRY(SPI0_CS1, 0, + "spi0_cs1", "uart3_rxd", NULL, "mmc0_pow", + NULL, "mmc0_sdcd", NULL, "gpio0_6"), + _AM33XX_MUXENTRY(ECAP0_IN_PWM0_OUT, 0, + "ecap0_in_pwm0_out", "uart3_txd", "spi1_cs1", NULL, + "spi1_sclk", "mmc0_sdwp", NULL, "gpio0_7"), + _AM33XX_MUXENTRY(UART0_CTSN, 0, + "uart0_ctsn", "uart4_rxd", "d_can1_tx", "i2c1_sda", + "spi1_d0", "timer7", "pr1_edc_sync0_out", "gpio1_8"), + _AM33XX_MUXENTRY(UART0_RTSN, 0, + "uart0_rtsn", "uart4_txd", "d_can1_rx", "i2c1_scl", + "spi1_d1", "spi1_cs0", "pr1_edc_sync1_out", "gpio1_9"), + _AM33XX_MUXENTRY(UART0_RXD, 0, + "uart0_rxd", "spi1_cs0", "d_can0_tx", "i2c2_sda", + NULL, NULL, NULL, "gpio1_10"), + _AM33XX_MUXENTRY(UART0_TXD, 0, + "uart0_txd", "spi1_cs1", "d_can0_rx", "i2c2_scl", + NULL, NULL, NULL, "gpio1_11"), + _AM33XX_MUXENTRY(UART1_CTSN, 0, + "uart1_ctsn", NULL, NULL, "i2c2_sda", + "spi1_cs0", NULL, NULL, "gpio0_12"), + _AM33XX_MUXENTRY(UART1_RTSN, 0, + "uart1_rtsn", NULL, NULL, "i2c2_scl", + "spi1_cs1", NULL, NULL, "gpio0_13"), + _AM33XX_MUXENTRY(UART1_RXD, 0, + "uart1_rxd", "mmc1_sdwp", "d_can1_tx", "i2c1_sda", + NULL, "pr1_uart0_rxd_mux1", NULL, "gpio0_14"), + _AM33XX_MUXENTRY(UART1_TXD, 0, + "uart1_txd", "mmc2_sdwp", "d_can1_rx", "i2c1_scl", + NULL, "pr1_uart0_txd_mux1", NULL, "gpio0_15"), + _AM33XX_MUXENTRY(I2C0_SDA, 0, + "i2c0_sda", NULL, NULL, NULL, + NULL, NULL, NULL, "gpio3_5"), + _AM33XX_MUXENTRY(I2C0_SCL, 0, + "i2c0_scl", NULL, NULL, NULL, + NULL, NULL, NULL, "gpio3_6"), + _AM33XX_MUXENTRY(MCASP0_ACLKX, 0, + "mcasp0_aclkx", "ehrpwm0a", NULL, "spi1_sclk", + "mmc0_sdcd", "pr1_pru0_pru_r30_0", "pr1_pru0_pru_r31_0", "gpio3_14"), + _AM33XX_MUXENTRY(MCASP0_FSX, 0, + "mcasp0_fsx", NULL, NULL, "spi1_d0", + "mmc1_sdcd", NULL, NULL, "gpio3_15"), + _AM33XX_MUXENTRY(MCASP0_AXR0, 0, + "mcasp0_axr0", NULL, NULL, "spi1_d1", + "mmc2_sdcd", NULL, NULL, "gpio3_16"), + _AM33XX_MUXENTRY(MCASP0_AHCLKR, 0, + "mcasp0_ahclkr", NULL, "mcasp0_axr2", "spi1_cs0", + NULL, NULL, NULL, "gpio3_17"), + _AM33XX_MUXENTRY(MCASP0_ACLKR, 0, + "mcasp0_aclkr", NULL, "mcasp0_axr2", "mcasp1_aclkx", + "mmc0_sdwp", NULL, NULL, "gpio3_18"), + _AM33XX_MUXENTRY(MCASP0_FSR, 0, + "mcasp0_fsr", NULL, "mcasp0_axr3", "mcasp1_fsx", + NULL, "pr1_pru0_pru_r30_5", NULL, "gpio3_19"), + _AM33XX_MUXENTRY(MCASP0_AXR1, 0, + "mcasp0_axr1", NULL, NULL, "mcasp1_axr0", + NULL, NULL, NULL, "gpio3_20"), + _AM33XX_MUXENTRY(MCASP0_AHCLKX, 0, + "mcasp0_ahclkx", NULL, "mcasp0_axr3", "mcasp1_axr1", + NULL, NULL, NULL, "gpio3_21"), + _AM33XX_MUXENTRY(XDMA_EVENT_INTR0, 0, + "xdma_event_intr0", NULL, NULL, NULL, + "spi1_cs1", NULL, NULL, "gpio0_19"), + _AM33XX_MUXENTRY(XDMA_EVENT_INTR1, 0, + "xdma_event_intr1", NULL, NULL, "clkout2", + NULL, NULL, NULL, "gpio0_20"), + _AM33XX_MUXENTRY(WARMRSTN, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(PWRONRSTN, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(NMIN, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(XTALIN, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(XTALOUT, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(TMS, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(TDI, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(TDO, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(TCK, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(TRSTN, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(EMU0, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, "gpio3_7"), + _AM33XX_MUXENTRY(EMU1, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, "gpio3_8"), + _AM33XX_MUXENTRY(RTC_XTALIN, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(RTC_XTALOUT, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(RTC_PWRONRSTN, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(PMIC_POWER_EN, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(EXT_WAKEUP, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(USB0_DRVVBUS, 0, + "usb0_drvvbus", NULL, NULL, NULL, + NULL, NULL, NULL, "gpio0_18"), + _AM33XX_MUXENTRY(USB1_DRVVBUS, 0, + "usb1_drvvbus", NULL, NULL, NULL, + NULL, NULL, NULL, "gpio3_13"), + _AM33XX_MUXENTRY(DDR_RESETN, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_CSN0, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_CKE, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_CK, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_CKN, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_CASN, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_RASN, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_WEN, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_BA0, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_BA1, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_BA2, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_A0, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_A1, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_A2, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_A3, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_A4, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_A5, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_A6, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_A7, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_A8, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_A9, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_A10, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_A11, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_A12, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_A13, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_A14, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_A15, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_ODT, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_D0, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_D1, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_D2, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_D3, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_D4, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_D5, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_D6, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_D7, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_D8, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_D9, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_D10, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_D11, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_D12, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_D13, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_D14, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_D15, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_DQM0, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_DQM1, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_DQS0, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_DQSN0, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_DQS1, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_DQSN1, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_VREF, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(DDR_VTP, 0, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(AIN0, 0, + "ain0", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(AIN1, 0, + "ain1", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(AIN2, 0, + "ain2", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(AIN3, 0, + "ain3", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(AIN4, 0, + "ain4", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(AIN5, 0, + "ain5", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(AIN6, 0, + "ain6", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(AIN7, 0, + "ain7", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(VREFP, 0, + "vrefp", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _AM33XX_MUXENTRY(VREFN, 0, + "vrefn", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + { .reg_offset = OMAP_MUX_TERMINATOR }, }; int __init am33xx_mux_init(struct omap_board_mux *board_subset) { - return omap_mux_init("core", 0, AM33XX_CONTROL_PADCONF_MUX_PBASE, - AM33XX_CONTROL_PADCONF_MUX_SIZE, am33xx_muxmodes, - NULL, board_subset, NULL); + return omap_mux_init("core", 0, AM33XX_CONTROL_PADCONF_MUX_PBASE, + AM33XX_CONTROL_PADCONF_MUX_SIZE, am33xx_muxmodes, + NULL, board_subset, NULL); } #else int __init am33xx_mux_init(struct omap_board_mux *board_subset) { - return 0; + return 0; } #endif + diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 0643847..a7cdc4e 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -33,69 +33,69 @@ #include "davinci_cpdma.h" -#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ - NETIF_MSG_DRV | NETIF_MSG_LINK | \ - NETIF_MSG_IFUP | NETIF_MSG_INTR | \ - NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ - NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ - NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ - NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ - NETIF_MSG_RX_STATUS) - -#define msg(level, type, format, ...) \ -do { \ - if (netif_msg_##type(priv) && net_ratelimit()) \ - dev_##level(priv->dev, format, ## __VA_ARGS__); \ +#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ + NETIF_MSG_DRV | NETIF_MSG_LINK | \ + NETIF_MSG_IFUP | NETIF_MSG_INTR | \ + NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ + NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ + NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ + NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ + NETIF_MSG_RX_STATUS) + +#define msg(level, type, format, ...) \ +do { \ + if (netif_msg_##type(priv) && net_ratelimit()) \ + dev_##level(priv->dev, format, ## __VA_ARGS__); \ } while (0) -#define CPDMA_RXTHRESH 0x0c0 -#define CPDMA_RXFREE 0x0e0 -#define CPDMA_TXHDP_VER1 0x100 -#define CPDMA_TXHDP_VER2 0x200 -#define CPDMA_RXHDP_VER1 0x120 -#define CPDMA_RXHDP_VER2 0x220 -#define CPDMA_TXCP_VER1 0x140 -#define CPDMA_TXCP_VER2 0x240 -#define CPDMA_RXCP_VER1 0x160 -#define CPDMA_RXCP_VER2 0x260 - -#define CPSW_POLL_WEIGHT 64 -#define CPSW_MIN_PACKET_SIZE 60 -#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) -#define CPSW_PHY_SPEED 1000 +#define CPDMA_RXTHRESH 0x0c0 +#define CPDMA_RXFREE 0x0e0 +#define CPDMA_TXHDP_VER1 0x100 +#define CPDMA_TXHDP_VER2 0x200 +#define CPDMA_RXHDP_VER1 0x120 +#define CPDMA_RXHDP_VER2 0x220 +#define CPDMA_TXCP_VER1 0x140 +#define CPDMA_TXCP_VER2 0x240 +#define CPDMA_RXCP_VER1 0x160 +#define CPDMA_RXCP_VER2 0x260 + +#define CPSW_POLL_WEIGHT 64 +#define CPSW_MIN_PACKET_SIZE 60 +#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) +#define CPSW_PHY_SPEED 1000 /* CPSW control module masks */ -#define CPSW_INTPACEEN (0x3 << 16) -#define CPSW_INTPRESCALE_MASK (0x7FF << 0) -#define CPSW_CMINTMAX_CNT 63 -#define CPSW_CMINTMIN_CNT 2 -#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) -#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) +#define CPSW_INTPACEEN (0x3 << 16) +#define CPSW_INTPRESCALE_MASK (0x7FF << 0) +#define CPSW_CMINTMAX_CNT 63 +#define CPSW_CMINTMIN_CNT 2 +#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) +#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) #define CPSW_IRQ_QUIRK #ifdef CPSW_IRQ_QUIRK -#define cpsw_enable_irq(priv) \ - do { \ - u32 i; \ - for (i = 0; i < priv->num_irqs; i++) \ - enable_irq(priv->irqs_table[i]); \ - } while (0); -#define cpsw_disable_irq(priv) \ - do { \ - u32 i; \ - for (i = 0; i < priv->num_irqs; i++) \ - disable_irq_nosync(priv->irqs_table[i]); \ - } while (0); +#define cpsw_enable_irq(priv) \ + do { \ + u32 i; \ + for (i = 0; i < priv->num_irqs; i++) \ + enable_irq(priv->irqs_table[i]); \ + } while (0); +#define cpsw_disable_irq(priv) \ + do { \ + u32 i; \ + for (i = 0; i < priv->num_irqs; i++) \ + disable_irq_nosync(priv->irqs_table[i]); \ + } while (0); #else #define cpsw_enable_irq(priv) do { } while (0); #define cpsw_disable_irq(priv) do { } while (0); #endif -#define CPSW_CPDMA_EOI_REG 0x894 -#define CPSW_TIMER_MASK 0xA0908 -#define CPSW_TIMER_CAP_REG 0xFD0 -#define CPSW_RX_TIMER_REQ 5 -#define CPSW_TX_TIMER_REQ 6 +#define CPSW_CPDMA_EOI_REG 0x894 +#define CPSW_TIMER_MASK 0xA0908 +#define CPSW_TIMER_CAP_REG 0xFD0 +#define CPSW_RX_TIMER_REQ 5 +#define CPSW_TX_TIMER_REQ 6 struct omap_dm_timer *dmtimer_rx; struct omap_dm_timer *dmtimer_tx; @@ -116,763 +116,767 @@ module_param(rx_packet_max, int, 0); MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); struct cpsw_ss_regs { - u32 id_ver; - u32 soft_reset; - u32 control; - u32 int_control; - u32 rx_thresh_en; - u32 rx_en; - u32 tx_en; - u32 misc_en; - u32 mem_allign1[8]; - u32 rx_thresh_stat; - u32 rx_stat; - u32 tx_stat; - u32 misc_stat; - u32 mem_allign2[8]; - u32 rx_imax; - u32 tx_imax; + u32 id_ver; + u32 soft_reset; + u32 control; + u32 int_control; + u32 rx_thresh_en; + u32 rx_en; + u32 tx_en; + u32 misc_en; + u32 mem_allign1[8]; + u32 rx_thresh_stat; + u32 rx_stat; + u32 tx_stat; + u32 misc_stat; + u32 mem_allign2[8]; + u32 rx_imax; + u32 tx_imax; }; struct cpsw_regs { - u32 id_ver; - u32 control; - u32 soft_reset; - u32 stat_port_en; - u32 ptype; + u32 id_ver; + u32 control; + u32 soft_reset; + u32 stat_port_en; + u32 ptype; }; struct cpsw_slave_regs { - u32 max_blks; - u32 blk_cnt; - u32 flow_thresh; - u32 port_vlan; - u32 tx_pri_map; - u32 ts_seq_mtype; + u32 max_blks; + u32 blk_cnt; + u32 flow_thresh; + u32 port_vlan; + u32 tx_pri_map; + u32 ts_seq_mtype; #ifdef CONFIG_ARCH_TI814X - u32 ts_ctl; - u32 ts_seq_ltype; - u32 ts_vlan; + u32 ts_ctl; + u32 ts_seq_ltype; + u32 ts_vlan; #endif - u32 sa_lo; - u32 sa_hi; + u32 sa_lo; + u32 sa_hi; }; struct cpsw_host_regs { - u32 max_blks; - u32 blk_cnt; - u32 flow_thresh; - u32 port_vlan; - u32 tx_pri_map; - u32 cpdma_tx_pri_map; - u32 cpdma_rx_chan_map; + u32 max_blks; + u32 blk_cnt; + u32 flow_thresh; + u32 port_vlan; + u32 tx_pri_map; + u32 cpdma_tx_pri_map; + u32 cpdma_rx_chan_map; }; struct cpsw_sliver_regs { - u32 id_ver; - u32 mac_control; - u32 mac_status; - u32 soft_reset; - u32 rx_maxlen; - u32 __reserved_0; - u32 rx_pause; - u32 tx_pause; - u32 __reserved_1; - u32 rx_pri_map; + u32 id_ver; + u32 mac_control; + u32 mac_status; + u32 soft_reset; + u32 rx_maxlen; + u32 __reserved_0; + u32 rx_pause; + u32 tx_pause; + u32 __reserved_1; + u32 rx_pri_map; }; struct cpsw_hw_stats { - u32 rxgoodframes; - u32 rxbroadcastframes; - u32 rxmulticastframes; - u32 rxpauseframes; - u32 rxcrcerrors; - u32 rxaligncodeerrors; - u32 rxoversizedframes; - u32 rxjabberframes; - u32 rxundersizedframes; - u32 rxfragments; - u32 __pad_0[2]; - u32 rxoctets; - u32 txgoodframes; - u32 txbroadcastframes; - u32 txmulticastframes; - u32 txpauseframes; - u32 txdeferredframes; - u32 txcollisionframes; - u32 txsinglecollframes; - u32 txmultcollframes; - u32 txexcessivecollisions; - u32 txlatecollisions; - u32 txunderrun; - u32 txcarriersenseerrors; - u32 txoctets; - u32 octetframes64; - u32 octetframes65t127; - u32 octetframes128t255; - u32 octetframes256t511; - u32 octetframes512t1023; - u32 octetframes1024tup; - u32 netoctets; - u32 rxsofoverruns; - u32 rxmofoverruns; - u32 rxdmaoverruns; + u32 rxgoodframes; + u32 rxbroadcastframes; + u32 rxmulticastframes; + u32 rxpauseframes; + u32 rxcrcerrors; + u32 rxaligncodeerrors; + u32 rxoversizedframes; + u32 rxjabberframes; + u32 rxundersizedframes; + u32 rxfragments; + u32 __pad_0[2]; + u32 rxoctets; + u32 txgoodframes; + u32 txbroadcastframes; + u32 txmulticastframes; + u32 txpauseframes; + u32 txdeferredframes; + u32 txcollisionframes; + u32 txsinglecollframes; + u32 txmultcollframes; + u32 txexcessivecollisions; + u32 txlatecollisions; + u32 txunderrun; + u32 txcarriersenseerrors; + u32 txoctets; + u32 octetframes64; + u32 octetframes65t127; + u32 octetframes128t255; + u32 octetframes256t511; + u32 octetframes512t1023; + u32 octetframes1024tup; + u32 netoctets; + u32 rxsofoverruns; + u32 rxmofoverruns; + u32 rxdmaoverruns; }; struct cpsw_slave { - struct cpsw_slave_regs __iomem *regs; - struct cpsw_sliver_regs __iomem *sliver; - int slave_num; - u32 mac_control; - struct cpsw_slave_data *data; - struct phy_device *phy; + struct cpsw_slave_regs __iomem *regs; + struct cpsw_sliver_regs __iomem *sliver; + int slave_num; + u32 mac_control; + struct cpsw_slave_data *data; + struct phy_device *phy; }; struct cpsw_priv { - spinlock_t lock; - struct platform_device *pdev; - struct net_device *ndev; - struct resource *cpsw_res; - struct resource *cpsw_ss_res; - struct napi_struct napi; -#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) - struct device *dev; - struct cpsw_platform_data data; - struct cpsw_regs __iomem *regs; - struct cpsw_ss_regs __iomem *ss_regs; - struct cpsw_hw_stats __iomem *hw_stats; - struct cpsw_host_regs __iomem *host_port_regs; - u32 msg_enable; - u32 coal_intvl; - u32 bus_freq_mhz; - struct net_device_stats stats; - int rx_packet_max; - int host_port; - struct clk *clk; - u8 mac_addr[ETH_ALEN]; - struct cpsw_slave *slaves; -#define for_each_slave(priv, func, arg...) \ - do { \ - int idx; \ - for (idx = 0; idx < (priv)->data.slaves; idx++) \ - (func)((priv)->slaves + idx, ##arg); \ - } while (0) - - struct cpdma_ctlr *dma; - struct cpdma_chan *txch, *rxch; - struct cpsw_ale *ale; + spinlock_t lock; + struct platform_device *pdev; + struct net_device *ndev; + struct resource *cpsw_res; + struct resource *cpsw_ss_res; + struct napi_struct napi; +#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) + struct device *dev; + struct cpsw_platform_data data; + struct cpsw_regs __iomem *regs; + struct cpsw_ss_regs __iomem *ss_regs; + struct cpsw_hw_stats __iomem *hw_stats; + struct cpsw_host_regs __iomem *host_port_regs; + u32 msg_enable; + u32 coal_intvl; + u32 bus_freq_mhz; + struct net_device_stats stats; + int rx_packet_max; + int host_port; + struct clk *clk; + u8 mac_addr[ETH_ALEN]; + struct cpsw_slave *slaves; +#define for_each_slave(priv, func, arg...) \ + do { \ + int idx; \ + for (idx = 0; idx < (priv)->data.slaves; idx++) \ + (func)((priv)->slaves + idx, ##arg); \ + } while (0) + + struct cpdma_ctlr *dma; + struct cpdma_chan *txch, *rxch; + struct cpsw_ale *ale; #ifdef CPSW_IRQ_QUIRK - /* snapshot of IRQ numbers */ - u32 irqs_table[4]; - u32 num_irqs; + /* snapshot of IRQ numbers */ + u32 irqs_table[4]; + u32 num_irqs; #endif }; static int cpsw_set_coalesce(struct net_device *ndev, - struct ethtool_coalesce *coal); + struct ethtool_coalesce *coal); static void cpsw_intr_enable(struct cpsw_priv *priv) { - __raw_writel(0xFF, &priv->ss_regs->tx_en); - __raw_writel(0xFF, &priv->ss_regs->rx_en); + __raw_writel(0xFF, &priv->ss_regs->tx_en); + __raw_writel(0xFF, &priv->ss_regs->rx_en); - cpdma_ctlr_int_ctrl(priv->dma, true); - return; + cpdma_ctlr_int_ctrl(priv->dma, true); + return; } static void cpsw_intr_disable(struct cpsw_priv *priv) { - __raw_writel(0, &priv->ss_regs->tx_en); - __raw_writel(0, &priv->ss_regs->rx_en); + __raw_writel(0, &priv->ss_regs->tx_en); + __raw_writel(0, &priv->ss_regs->rx_en); - cpdma_ctlr_int_ctrl(priv->dma, false); - return; + cpdma_ctlr_int_ctrl(priv->dma, false); + return; } void cpsw_tx_handler(void *token, int len, int status) { - struct sk_buff *skb = token; - struct net_device *ndev = skb->dev; - struct cpsw_priv *priv = netdev_priv(ndev); - - if (unlikely(netif_queue_stopped(ndev))) - netif_start_queue(ndev); - priv->stats.tx_packets++; - priv->stats.tx_bytes += len; - dev_kfree_skb_any(skb); + struct sk_buff *skb = token; + struct net_device *ndev = skb->dev; + struct cpsw_priv *priv = netdev_priv(ndev); + + if (unlikely(netif_queue_stopped(ndev))) + netif_start_queue(ndev); + priv->stats.tx_packets++; + priv->stats.tx_bytes += len; + dev_kfree_skb_any(skb); } void cpsw_rx_handler(void *token, int len, int status) { - struct sk_buff *skb = token; - struct net_device *ndev = skb->dev; - struct cpsw_priv *priv = netdev_priv(ndev); - int ret = 0; - - if (likely(status >= 0)) { - skb_put(skb, len); - skb->protocol = eth_type_trans(skb, ndev); - netif_receive_skb(skb); - priv->stats.rx_bytes += len; - priv->stats.rx_packets++; - skb = NULL; - } - - - if (unlikely(!netif_running(ndev))) { - if (skb) - dev_kfree_skb_any(skb); - return; - } - - if (likely(!skb)) { - skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); - if (WARN_ON(!skb)) - return; - - ret = cpdma_chan_submit(priv->rxch, skb, skb->data, - skb_tailroom(skb), GFP_KERNEL); - } - - WARN_ON(ret < 0); + struct sk_buff *skb = token; + struct net_device *ndev = skb->dev; + struct cpsw_priv *priv = netdev_priv(ndev); + int ret = 0; + + if (likely(status >= 0)) { + skb_put(skb, len); + skb->protocol = eth_type_trans(skb, ndev); + netif_receive_skb(skb); + priv->stats.rx_bytes += len; + priv->stats.rx_packets++; + skb = NULL; + } + + + if (unlikely(!netif_running(ndev))) { + if (skb) + dev_kfree_skb_any(skb); + return; + } + + if (likely(!skb)) { + skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); + if (WARN_ON(!skb)) + return; + + ret = cpdma_chan_submit(priv->rxch, skb, skb->data, + skb_tailroom(skb), GFP_KERNEL); + } + + WARN_ON(ret < 0); } static void set_cpsw_dmtimer_clear(void) { - omap_dm_timer_write_status(dmtimer_rx, OMAP_TIMER_INT_CAPTURE); - omap_dm_timer_write_status(dmtimer_tx, OMAP_TIMER_INT_CAPTURE); + omap_dm_timer_write_status(dmtimer_rx, OMAP_TIMER_INT_CAPTURE); + omap_dm_timer_write_status(dmtimer_tx, OMAP_TIMER_INT_CAPTURE); - return; + return; } static irqreturn_t cpsw_interrupt(int irq, void *dev_id) { - struct cpsw_priv *priv = dev_id; + struct cpsw_priv *priv = dev_id; - if (likely(netif_running(priv->ndev))) { - cpsw_intr_disable(priv); - cpsw_disable_irq(priv); - napi_schedule(&priv->napi); - } + if (likely(netif_running(priv->ndev))) { + cpsw_intr_disable(priv); + cpsw_disable_irq(priv); + napi_schedule(&priv->napi); + } - return IRQ_HANDLED; + return IRQ_HANDLED; } static int cpsw_poll(struct napi_struct *napi, int budget) { - struct cpsw_priv *priv = napi_to_priv(napi); - int num_tx, num_rx; + struct cpsw_priv *priv = napi_to_priv(napi); + int num_tx, num_rx; - num_tx = cpdma_chan_process(priv->txch, 128); - num_rx = cpdma_chan_process(priv->rxch, budget); + num_tx = cpdma_chan_process(priv->txch, 128); + num_rx = cpdma_chan_process(priv->rxch, budget); - if (num_rx || num_tx) - msg(dbg, intr, "poll %d rx, %d tx pkts\n", num_rx, num_tx); + if (num_rx || num_tx) + msg(dbg, intr, "poll %d rx, %d tx pkts\n", num_rx, num_tx); - if (num_rx < budget) { - napi_complete(napi); - cpdma_ctlr_eoi(priv->dma); - set_cpsw_dmtimer_clear(); - cpsw_intr_enable(priv); - cpsw_enable_irq(priv); - } + if (num_rx < budget) { + napi_complete(napi); + cpdma_ctlr_eoi(priv->dma); + set_cpsw_dmtimer_clear(); + cpsw_intr_enable(priv); + cpsw_enable_irq(priv); + } - return num_rx; + return num_rx; } static inline void soft_reset(const char *module, void __iomem *reg) { - unsigned long timeout = jiffies + HZ; + unsigned long timeout = jiffies + HZ; - __raw_writel(1, reg); - do { - cpu_relax(); - } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); + __raw_writel(1, reg); + do { + cpu_relax(); + } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); - WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); + WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); } -#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ - ((mac)[2] << 16) | ((mac)[3] << 24)) -#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) +#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ + ((mac)[2] << 16) | ((mac)[3] << 24)) +#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) static void cpsw_set_slave_mac(struct cpsw_slave *slave, - struct cpsw_priv *priv) + struct cpsw_priv *priv) { - __raw_writel(mac_hi(priv->mac_addr), &slave->regs->sa_hi); - __raw_writel(mac_lo(priv->mac_addr), &slave->regs->sa_lo); + __raw_writel(mac_hi(priv->mac_addr), &slave->regs->sa_hi); + __raw_writel(mac_lo(priv->mac_addr), &slave->regs->sa_lo); } static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) { - if (priv->host_port == 0) - return slave_num + 1; - else - return slave_num; + if (priv->host_port == 0) + return slave_num + 1; + else + return slave_num; } static void _cpsw_adjust_link(struct cpsw_slave *slave, - struct cpsw_priv *priv, bool *link) + struct cpsw_priv *priv, bool *link) { - struct phy_device *phy = slave->phy; - u32 mac_control = 0; - u32 slave_port; - - if (!phy) - return; - - slave_port = cpsw_get_slave_port(priv, slave->slave_num); - - if (phy->link) { - /* enable forwarding */ - cpsw_ale_control_set(priv->ale, slave_port, - ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); - - mac_control = priv->data.mac_control; - if (phy->speed == 10) - mac_control |= BIT(18); /* In Band mode */ - if (phy->speed == 1000) { - mac_control |= BIT(7); /* Enable gigabit mode */ - } - if (phy->speed == 100) - mac_control |= BIT(15); - if (phy->duplex) - mac_control |= BIT(0); /* FULLDUPLEXEN */ - if (phy->interface == PHY_INTERFACE_MODE_RGMII) /* RGMII */ - mac_control |= (BIT(15)|BIT(16)); - *link = true; - } else { - cpsw_ale_control_set(priv->ale, slave_port, - ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); - mac_control = 0; - } - - if (mac_control != slave->mac_control) { - phy_print_status(phy); - __raw_writel(mac_control, &slave->sliver->mac_control); - } - - slave->mac_control = mac_control; + struct phy_device *phy = slave->phy; + u32 mac_control = 0; + u32 slave_port; + + if (!phy) + return; + + slave_port = cpsw_get_slave_port(priv, slave->slave_num); + + if (phy->link) { + /* enable forwarding */ + cpsw_ale_control_set(priv->ale, slave_port, + ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); + + mac_control = priv->data.mac_control; + if (phy->speed == 10) + mac_control |= BIT(18); /* In Band mode */ + if (phy->speed == 1000) { + mac_control |= BIT(7); /* Enable gigabit mode */ + } + if (phy->speed == 100) + mac_control |= BIT(15); + if (phy->duplex) + mac_control |= BIT(0); /* FULLDUPLEXEN */ + if (phy->interface == PHY_INTERFACE_MODE_RMII) /* RMII */ + mac_control |= (BIT(15)|BIT(16)); + *link = true; + } else { + cpsw_ale_control_set(priv->ale, slave_port, + ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); + mac_control = 0; + } + + // printk("danm 2 - mac control 0x%x 0x%p slave num %x, slave port 0x%x\n",mac_control, + // danm &slave->sliver->mac_control,slave->slave_num,slave_port); + + if (mac_control != slave->mac_control) { + phy_print_status(phy); + __raw_writel(mac_control, &slave->sliver->mac_control); + } + + slave->mac_control = mac_control; } static void cpsw_adjust_link(struct net_device *ndev) { - struct cpsw_priv *priv = netdev_priv(ndev); - bool link = false; - - for_each_slave(priv, _cpsw_adjust_link, priv, &link); - - if (link) { - netif_carrier_on(ndev); - if (netif_running(ndev)) - netif_wake_queue(ndev); - } else { - netif_carrier_off(ndev); - netif_stop_queue(ndev); - } + struct cpsw_priv *priv = netdev_priv(ndev); + bool link = false; + + for_each_slave(priv, _cpsw_adjust_link, priv, &link); + + if (link) { + netif_carrier_on(ndev); + if (netif_running(ndev)) + netif_wake_queue(ndev); + } else { + netif_carrier_off(ndev); + netif_stop_queue(ndev); + } } static inline int __show_stat(char *buf, int maxlen, const char* name, u32 val) { - static char *leader = "........................................"; + static char *leader = "........................................"; - if (!val) - return 0; - else - return snprintf(buf, maxlen, "%s %s %10d\n", name, - leader + strlen(name), val); + if (!val) + return 0; + else + return snprintf(buf, maxlen, "%s %s %10d\n", name, + leader + strlen(name), val); } static ssize_t cpsw_hw_stats_show(struct device *dev, - struct device_attribute *attr, - char *buf) + struct device_attribute *attr, + char *buf) { - struct net_device *ndev = to_net_dev(dev); - struct cpsw_priv *priv = netdev_priv(ndev); - int len = 0; - struct cpdma_chan_stats dma_stats; - -#define show_stat(x) do { \ - len += __show_stat(buf + len, SZ_4K - len, #x, \ - __raw_readl(&priv->hw_stats->x)); \ + struct net_device *ndev = to_net_dev(dev); + struct cpsw_priv *priv = netdev_priv(ndev); + int len = 0; + struct cpdma_chan_stats dma_stats; + +#define show_stat(x) do { \ + len += __show_stat(buf + len, SZ_4K - len, #x, \ + __raw_readl(&priv->hw_stats->x)); \ } while (0) -#define show_dma_stat(x) do { \ - len += __show_stat(buf + len, SZ_4K - len, #x, dma_stats.x); \ +#define show_dma_stat(x) do { \ + len += __show_stat(buf + len, SZ_4K - len, #x, dma_stats.x); \ } while (0) - len += snprintf(buf + len, SZ_4K - len, "CPSW Statistics:\n"); - show_stat(rxgoodframes); show_stat(rxbroadcastframes); - show_stat(rxmulticastframes); show_stat(rxpauseframes); - show_stat(rxcrcerrors); show_stat(rxaligncodeerrors); - show_stat(rxoversizedframes); show_stat(rxjabberframes); - show_stat(rxundersizedframes); show_stat(rxfragments); - show_stat(rxoctets); show_stat(txgoodframes); - show_stat(txbroadcastframes); show_stat(txmulticastframes); - show_stat(txpauseframes); show_stat(txdeferredframes); - show_stat(txcollisionframes); show_stat(txsinglecollframes); - show_stat(txmultcollframes); show_stat(txexcessivecollisions); - show_stat(txlatecollisions); show_stat(txunderrun); - show_stat(txcarriersenseerrors); show_stat(txoctets); - show_stat(octetframes64); show_stat(octetframes65t127); - show_stat(octetframes128t255); show_stat(octetframes256t511); - show_stat(octetframes512t1023); show_stat(octetframes1024tup); - show_stat(netoctets); show_stat(rxsofoverruns); - show_stat(rxmofoverruns); show_stat(rxdmaoverruns); - - cpdma_chan_get_stats(priv->rxch, &dma_stats); - len += snprintf(buf + len, SZ_4K - len, "\nRX DMA Statistics:\n"); - show_dma_stat(head_enqueue); show_dma_stat(tail_enqueue); - show_dma_stat(pad_enqueue); show_dma_stat(misqueued); - show_dma_stat(desc_alloc_fail); show_dma_stat(pad_alloc_fail); - show_dma_stat(runt_receive_buff); show_dma_stat(runt_transmit_buff); - show_dma_stat(empty_dequeue); show_dma_stat(busy_dequeue); - show_dma_stat(good_dequeue); show_dma_stat(teardown_dequeue); - - cpdma_chan_get_stats(priv->txch, &dma_stats); - len += snprintf(buf + len, SZ_4K - len, "\nTX DMA Statistics:\n"); - show_dma_stat(head_enqueue); show_dma_stat(tail_enqueue); - show_dma_stat(pad_enqueue); show_dma_stat(misqueued); - show_dma_stat(desc_alloc_fail); show_dma_stat(pad_alloc_fail); - show_dma_stat(runt_receive_buff); show_dma_stat(runt_transmit_buff); - show_dma_stat(empty_dequeue); show_dma_stat(busy_dequeue); - show_dma_stat(good_dequeue); show_dma_stat(teardown_dequeue); - - return len; + len += snprintf(buf + len, SZ_4K - len, "CPSW Statistics:\n"); + show_stat(rxgoodframes); show_stat(rxbroadcastframes); + show_stat(rxmulticastframes); show_stat(rxpauseframes); + show_stat(rxcrcerrors); show_stat(rxaligncodeerrors); + show_stat(rxoversizedframes); show_stat(rxjabberframes); + show_stat(rxundersizedframes); show_stat(rxfragments); + show_stat(rxoctets); show_stat(txgoodframes); + show_stat(txbroadcastframes); show_stat(txmulticastframes); + show_stat(txpauseframes); show_stat(txdeferredframes); + show_stat(txcollisionframes); show_stat(txsinglecollframes); + show_stat(txmultcollframes); show_stat(txexcessivecollisions); + show_stat(txlatecollisions); show_stat(txunderrun); + show_stat(txcarriersenseerrors); show_stat(txoctets); + show_stat(octetframes64); show_stat(octetframes65t127); + show_stat(octetframes128t255); show_stat(octetframes256t511); + show_stat(octetframes512t1023); show_stat(octetframes1024tup); + show_stat(netoctets); show_stat(rxsofoverruns); + show_stat(rxmofoverruns); show_stat(rxdmaoverruns); + + cpdma_chan_get_stats(priv->rxch, &dma_stats); + len += snprintf(buf + len, SZ_4K - len, "\nRX DMA Statistics:\n"); + show_dma_stat(head_enqueue); show_dma_stat(tail_enqueue); + show_dma_stat(pad_enqueue); show_dma_stat(misqueued); + show_dma_stat(desc_alloc_fail); show_dma_stat(pad_alloc_fail); + show_dma_stat(runt_receive_buff); show_dma_stat(runt_transmit_buff); + show_dma_stat(empty_dequeue); show_dma_stat(busy_dequeue); + show_dma_stat(good_dequeue); show_dma_stat(teardown_dequeue); + + cpdma_chan_get_stats(priv->txch, &dma_stats); + len += snprintf(buf + len, SZ_4K - len, "\nTX DMA Statistics:\n"); + show_dma_stat(head_enqueue); show_dma_stat(tail_enqueue); + show_dma_stat(pad_enqueue); show_dma_stat(misqueued); + show_dma_stat(desc_alloc_fail); show_dma_stat(pad_alloc_fail); + show_dma_stat(runt_receive_buff); show_dma_stat(runt_transmit_buff); + show_dma_stat(empty_dequeue); show_dma_stat(busy_dequeue); + show_dma_stat(good_dequeue); show_dma_stat(teardown_dequeue); + + return len; } DEVICE_ATTR(hw_stats, S_IRUGO, cpsw_hw_stats_show, NULL); -#define PHY_CONFIG_REG 22 +#define PHY_CONFIG_REG 22 static void cpsw_set_phy_config(struct cpsw_priv *priv, struct phy_device *phy) { - struct cpsw_platform_data *pdata = priv->pdev->dev.platform_data; - struct mii_bus *miibus; - int phy_addr = 0; - u16 val = 0; - u16 tmp = 0; - - if (!phy) - return; - - miibus = phy->bus; - - if (!miibus) - return; - - phy_addr = phy->addr; - - /* Disable 1 Gig mode support if it is not supported */ - if (!pdata->gigabit_en) - phy->supported &= ~(SUPPORTED_1000baseT_Half | - SUPPORTED_1000baseT_Full); - - /* Following lines enable gigbit advertisement capability even in case - * the advertisement is not enabled by default - */ - val = miibus->read(miibus, phy_addr, MII_BMCR); - val |= (BMCR_SPEED100 | BMCR_ANENABLE | BMCR_FULLDPLX); - miibus->write(miibus, phy_addr, MII_BMCR, val); - tmp = miibus->read(miibus, phy_addr, MII_BMCR); - - /* Enable gigabit support only if the speed is 1000Mbps */ - if (phy->speed == CPSW_PHY_SPEED) { - tmp = miibus->read(miibus, phy_addr, MII_BMSR); - if (tmp & 0x1) { - val = miibus->read(miibus, phy_addr, MII_CTRL1000); - val |= BIT(9); - miibus->write(miibus, phy_addr, MII_CTRL1000, val); - tmp = miibus->read(miibus, phy_addr, MII_CTRL1000); - } - } - - val = miibus->read(miibus, phy_addr, MII_ADVERTISE); - val |= (ADVERTISE_10HALF | ADVERTISE_10FULL | \ - ADVERTISE_100HALF | ADVERTISE_100FULL); - miibus->write(miibus, phy_addr, MII_ADVERTISE, val); - tmp = miibus->read(miibus, phy_addr, MII_ADVERTISE); - - /* TODO : This check is required. This should be - * moved to a board init section as its specific - * to a phy.*/ - if (phy->phy_id == 0x0282F014) { - /* This enables TX_CLK-ing in case of 10/100MBps operation */ - val = miibus->read(miibus, phy_addr, PHY_CONFIG_REG); - val |= BIT(5); - miibus->write(miibus, phy_addr, PHY_CONFIG_REG, val); - tmp = miibus->read(miibus, phy_addr, PHY_CONFIG_REG); - } - - return; + struct cpsw_platform_data *pdata = priv->pdev->dev.platform_data; + struct mii_bus *miibus; + int phy_addr = 0; + u16 val = 0; + u16 tmp = 0; + + if (!phy) + return; + + miibus = phy->bus; + + if (!miibus) + return; + + phy_addr = phy->addr; + phy->interface = PHY_INTERFACE_MODE_RMII; + + /* Disable 1 Gig mode support if it is not supported */ + if (!pdata->gigabit_en) + phy->supported &= ~(SUPPORTED_1000baseT_Half | + SUPPORTED_1000baseT_Full); + + /* Following lines enable gigbit advertisement capability even in case + * the advertisement is not enabled by default + */ + val = miibus->read(miibus, phy_addr, MII_BMCR); + val |= (BMCR_SPEED100 | BMCR_ANENABLE | BMCR_FULLDPLX); + miibus->write(miibus, phy_addr, MII_BMCR, val); + tmp = miibus->read(miibus, phy_addr, MII_BMCR); + + /* Enable gigabit support only if the speed is 1000Mbps */ + if (phy->speed == CPSW_PHY_SPEED) { + tmp = miibus->read(miibus, phy_addr, MII_BMSR); + if (tmp & 0x1) { + val = miibus->read(miibus, phy_addr, MII_CTRL1000); + val |= BIT(9); + miibus->write(miibus, phy_addr, MII_CTRL1000, val); + tmp = miibus->read(miibus, phy_addr, MII_CTRL1000); + } + } + + val = miibus->read(miibus, phy_addr, MII_ADVERTISE); + val |= (ADVERTISE_10HALF | ADVERTISE_10FULL | \ + ADVERTISE_100HALF | ADVERTISE_100FULL); + miibus->write(miibus, phy_addr, MII_ADVERTISE, val); + tmp = miibus->read(miibus, phy_addr, MII_ADVERTISE); + + /* TODO : This check is required. This should be + * moved to a board init section as its specific + * to a phy.*/ + if (phy->phy_id == 0x0282F014) { + /* This enables TX_CLK-ing in case of 10/100MBps operation */ + val = miibus->read(miibus, phy_addr, PHY_CONFIG_REG); + val |= BIT(5); + miibus->write(miibus, phy_addr, PHY_CONFIG_REG, val); + tmp = miibus->read(miibus, phy_addr, PHY_CONFIG_REG); + } + + return; } static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) { - char name[32]; - u32 slave_port; - - sprintf(name, "slave-%d", slave->slave_num); - - soft_reset(name, &slave->sliver->soft_reset); - - /* setup priority mapping */ - __raw_writel(0x76543210, &slave->sliver->rx_pri_map); - __raw_writel(0x33221100, &slave->regs->tx_pri_map); - - /* setup max packet size, and mac address */ - __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); - cpsw_set_slave_mac(slave, priv); - - slave->mac_control = 0; /* no link yet */ - - slave_port = cpsw_get_slave_port(priv, slave->slave_num); - cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, - 1 << slave_port); - - slave->phy = phy_connect(priv->ndev, slave->data->phy_id, - &cpsw_adjust_link, 0, slave->data->phy_if); - if (IS_ERR(slave->phy)) { - msg(err, ifup, "phy %s not found on slave %d\n", - slave->data->phy_id, slave->slave_num); - slave->phy = NULL; - } else { - printk(KERN_ERR"\nCPSW phy found : id is : 0x%x\n", - slave->phy->phy_id); - cpsw_set_phy_config(priv, slave->phy); - phy_start(slave->phy); - } + char name[32]; + u32 slave_port; + + sprintf(name, "slave-%d", slave->slave_num); + + soft_reset(name, &slave->sliver->soft_reset); + + /* setup priority mapping */ + __raw_writel(0x76543210, &slave->sliver->rx_pri_map); + __raw_writel(0x33221100, &slave->regs->tx_pri_map); + + /* setup max packet size, and mac address */ + __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); + cpsw_set_slave_mac(slave, priv); + + slave->mac_control = 0; /* no link yet */ + + slave_port = cpsw_get_slave_port(priv, slave->slave_num); + cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, + 1 << slave_port); + + slave->phy = phy_connect(priv->ndev, slave->data->phy_id, + &cpsw_adjust_link, 0, slave->data->phy_if); + if (IS_ERR(slave->phy)) { + msg(err, ifup, "phy %s not found on slave %d\n", + slave->data->phy_id, slave->slave_num); + slave->phy = NULL; + } else { + printk(KERN_ERR"\nCPSW phy found : id is : 0x%x\n", + slave->phy->phy_id); + cpsw_set_phy_config(priv, slave->phy); + phy_start(slave->phy); + } } static void cpsw_init_host_port(struct cpsw_priv *priv) { - /* soft reset the controller and initialize ale */ - soft_reset("cpsw", &priv->regs->soft_reset); - cpsw_ale_start(priv->ale); + /* soft reset the controller and initialize ale */ + soft_reset("cpsw", &priv->regs->soft_reset); + cpsw_ale_start(priv->ale); - /* switch to vlan unaware mode */ - cpsw_ale_control_set(priv->ale, 0, ALE_VLAN_AWARE, 0); + /* switch to vlan unaware mode */ + cpsw_ale_control_set(priv->ale, 0, ALE_VLAN_AWARE, 0); - /* setup host port priority mapping */ - __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map); - __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); + /* setup host port priority mapping */ + __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map); + __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); - cpsw_ale_control_set(priv->ale, priv->host_port, - ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); + cpsw_ale_control_set(priv->ale, priv->host_port, + ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); - cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, - 0); - /* ALE_SECURE); */ - cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, - 1 << priv->host_port); + cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, + 0); + /* ALE_SECURE); */ + cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, + 1 << priv->host_port); } static int cpsw_ndo_open(struct net_device *ndev) { - struct cpsw_priv *priv = netdev_priv(ndev); - int i, ret; - u32 reg; - - cpsw_intr_disable(priv); - netif_carrier_off(ndev); - - ret = clk_enable(priv->clk); - if (ret < 0) { - dev_err(priv->dev, "unable to turn on device clock\n"); - return ret; - } - - ret = device_create_file(&ndev->dev, &dev_attr_hw_stats); - if (ret < 0) { - dev_err(priv->dev, "unable to add device attr\n"); - return ret; - } - - if (priv->data.phy_control) - (*priv->data.phy_control)(true); - - reg = __raw_readl(&priv->regs->id_ver); - - msg(info, ifup, "initializing cpsw version %d.%d (%d)\n", - (reg >> 8 & 0x7), reg & 0xff, (reg >> 11) & 0x1f); - - /* initialize host and slave ports */ - cpsw_init_host_port(priv); - for_each_slave(priv, cpsw_slave_open, priv); - - /* setup tx dma to fixed prio and zero offset */ - cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); - cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); - - /* disable priority elevation and enable statistics on all ports */ - __raw_writel(0, &priv->regs->ptype); - - /* enable statistics collection only on the host port */ - /* __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en); */ - __raw_writel(0x7, &priv->regs->stat_port_en); - - if (WARN_ON(!priv->data.rx_descs)) - priv->data.rx_descs = 128; - - for (i = 0; i < priv->data.rx_descs; i++) { - struct sk_buff *skb; - - ret = -ENOMEM; - skb = netdev_alloc_skb_ip_align(priv->ndev, - priv->rx_packet_max); - if (!skb) - break; - ret = cpdma_chan_submit(priv->rxch, skb, skb->data, - skb_tailroom(skb), GFP_KERNEL); - if (WARN_ON(ret < 0)) - break; - } - /* continue even if we didn't manage to submit all receive descs */ - msg(info, ifup, "submitted %d rx descriptors\n", i); - - /* Enable Interrupt pacing if configured */ - if (priv->coal_intvl != 0) { - struct ethtool_coalesce coal; - - coal.rx_coalesce_usecs = (priv->coal_intvl << 4); - cpsw_set_coalesce(ndev, &coal); - } - - cpdma_ctlr_start(priv->dma); - cpsw_intr_enable(priv); - napi_enable(&priv->napi); - cpdma_ctlr_eoi(priv->dma); - - return 0; + struct cpsw_priv *priv = netdev_priv(ndev); + int i, ret; + u32 reg; + + cpsw_intr_disable(priv); + netif_carrier_off(ndev); + + ret = clk_enable(priv->clk); + if (ret < 0) { + dev_err(priv->dev, "unable to turn on device clock\n"); + return ret; + } + + ret = device_create_file(&ndev->dev, &dev_attr_hw_stats); + if (ret < 0) { + dev_err(priv->dev, "unable to add device attr\n"); + return ret; + } + + if (priv->data.phy_control) + (*priv->data.phy_control)(true); + + reg = __raw_readl(&priv->regs->id_ver); + + msg(info, ifup, "initializing cpsw version %d.%d (%d)\n", + (reg >> 8 & 0x7), reg & 0xff, (reg >> 11) & 0x1f); + + /* initialize host and slave ports */ + cpsw_init_host_port(priv); + for_each_slave(priv, cpsw_slave_open, priv); + + /* setup tx dma to fixed prio and zero offset */ + cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); + cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); + + /* disable priority elevation and enable statistics on all ports */ + __raw_writel(0, &priv->regs->ptype); + + /* enable statistics collection only on the host port */ + /* __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en); */ + __raw_writel(0x7, &priv->regs->stat_port_en); + + if (WARN_ON(!priv->data.rx_descs)) + priv->data.rx_descs = 128; + + for (i = 0; i < priv->data.rx_descs; i++) { + struct sk_buff *skb; + + ret = -ENOMEM; + skb = netdev_alloc_skb_ip_align(priv->ndev, + priv->rx_packet_max); + if (!skb) + break; + ret = cpdma_chan_submit(priv->rxch, skb, skb->data, + skb_tailroom(skb), GFP_KERNEL); + if (WARN_ON(ret < 0)) + break; + } + /* continue even if we didn't manage to submit all receive descs */ + msg(info, ifup, "submitted %d rx descriptors\n", i); + + /* Enable Interrupt pacing if configured */ + if (priv->coal_intvl != 0) { + struct ethtool_coalesce coal; + + coal.rx_coalesce_usecs = (priv->coal_intvl << 4); + cpsw_set_coalesce(ndev, &coal); + } + + cpdma_ctlr_start(priv->dma); + cpsw_intr_enable(priv); + napi_enable(&priv->napi); + cpdma_ctlr_eoi(priv->dma); + + return 0; } static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) { - if (!slave->phy) - return; - phy_stop(slave->phy); - phy_disconnect(slave->phy); - slave->phy = NULL; + if (!slave->phy) + return; + phy_stop(slave->phy); + phy_disconnect(slave->phy); + slave->phy = NULL; } static int cpsw_ndo_stop(struct net_device *ndev) { - struct cpsw_priv *priv = netdev_priv(ndev); - - msg(info, ifdown, "shutting down cpsw device\n"); - cpsw_intr_disable(priv); - cpdma_ctlr_int_ctrl(priv->dma, false); - cpdma_ctlr_stop(priv->dma); - netif_stop_queue(priv->ndev); - napi_disable(&priv->napi); - netif_carrier_off(priv->ndev); - cpsw_ale_stop(priv->ale); - device_remove_file(&ndev->dev, &dev_attr_hw_stats); - for_each_slave(priv, cpsw_slave_stop, priv); - if (priv->data.phy_control) - (*priv->data.phy_control)(false); - clk_disable(priv->clk); - return 0; + struct cpsw_priv *priv = netdev_priv(ndev); + + msg(info, ifdown, "shutting down cpsw device\n"); + cpsw_intr_disable(priv); + cpdma_ctlr_int_ctrl(priv->dma, false); + cpdma_ctlr_stop(priv->dma); + netif_stop_queue(priv->ndev); + napi_disable(&priv->napi); + netif_carrier_off(priv->ndev); + cpsw_ale_stop(priv->ale); + device_remove_file(&ndev->dev, &dev_attr_hw_stats); + for_each_slave(priv, cpsw_slave_stop, priv); + if (priv->data.phy_control) + (*priv->data.phy_control)(false); + clk_disable(priv->clk); + return 0; } static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, - struct net_device *ndev) + struct net_device *ndev) { - struct cpsw_priv *priv = netdev_priv(ndev); - int ret; + struct cpsw_priv *priv = netdev_priv(ndev); + int ret; - ndev->trans_start = jiffies; + ndev->trans_start = jiffies; - ret = skb_padto(skb, CPSW_MIN_PACKET_SIZE); - if (unlikely(ret < 0)) { - msg(err, tx_err, "packet pad failed"); - goto fail; - } + ret = skb_padto(skb, CPSW_MIN_PACKET_SIZE); + if (unlikely(ret < 0)) { + msg(err, tx_err, "packet pad failed"); + goto fail; + } - ret = cpdma_chan_submit(priv->txch, skb, skb->data, - skb->len, GFP_KERNEL); - if (unlikely(ret != 0)) { - msg(err, tx_err, "desc submit failed"); - goto fail; - } + ret = cpdma_chan_submit(priv->txch, skb, skb->data, + skb->len, GFP_KERNEL); + if (unlikely(ret != 0)) { + msg(err, tx_err, "desc submit failed"); + goto fail; + } - return NETDEV_TX_OK; + return NETDEV_TX_OK; fail: - priv->stats.tx_dropped++; - netif_stop_queue(ndev); - return NETDEV_TX_BUSY; + priv->stats.tx_dropped++; + netif_stop_queue(ndev); + return NETDEV_TX_BUSY; } static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags) { - /* - * The switch cannot operate in promiscuous mode without substantial - * headache. For promiscuous mode to work, we would need to put the - * ALE in bypass mode and route all traffic to the host port. - * Subsequently, the host will need to operate as a "bridge", learn, - * and flood as needed. For now, we simply complain here and - * do nothing about it :-) - */ - if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC)) - dev_err(&ndev->dev, "promiscuity ignored!\n"); - - /* - * The switch cannot filter multicast traffic unless it is configured - * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a - * whole bunch of additional logic that this driver does not implement - * at present. - */ - if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI)) - dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n"); + /* + * The switch cannot operate in promiscuous mode without substantial + * headache. For promiscuous mode to work, we would need to put the + * ALE in bypass mode and route all traffic to the host port. + * Subsequently, the host will need to operate as a "bridge", learn, + * and flood as needed. For now, we simply complain here and + * do nothing about it :-) + */ + if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC)) + dev_err(&ndev->dev, "promiscuity ignored!\n"); + + /* + * The switch cannot filter multicast traffic unless it is configured + * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a + * whole bunch of additional logic that this driver does not implement + * at present. + */ + if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI)) + dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n"); } static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *addr) { - struct cpsw_priv *priv = netdev_priv(ndev); - - cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port); - memcpy(priv->mac_addr, ndev->dev_addr, ETH_ALEN); - cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, - 0); - /* ALE_SECURE); */ - for_each_slave(priv, cpsw_set_slave_mac, priv); - return 0; + struct cpsw_priv *priv = netdev_priv(ndev); + + cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port); + memcpy(priv->mac_addr, ndev->dev_addr, ETH_ALEN); + cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, + 0); + /* ALE_SECURE); */ + for_each_slave(priv, cpsw_set_slave_mac, priv); + return 0; } static void cpsw_ndo_tx_timeout(struct net_device *ndev) { - struct cpsw_priv *priv = netdev_priv(ndev); - - msg(err, tx_err, "transmit timeout, restarting dma"); - priv->stats.tx_errors++; - cpsw_intr_disable(priv); - cpdma_ctlr_int_ctrl(priv->dma, false); - cpdma_chan_stop(priv->txch); - cpdma_chan_start(priv->txch); - cpdma_ctlr_int_ctrl(priv->dma, true); - cpsw_intr_enable(priv); - cpdma_ctlr_eoi(priv->dma); + struct cpsw_priv *priv = netdev_priv(ndev); + + msg(err, tx_err, "transmit timeout, restarting dma"); + priv->stats.tx_errors++; + cpsw_intr_disable(priv); + cpdma_ctlr_int_ctrl(priv->dma, false); + cpdma_chan_stop(priv->txch); + cpdma_chan_start(priv->txch); + cpdma_ctlr_int_ctrl(priv->dma, true); + cpsw_intr_enable(priv); + cpdma_ctlr_eoi(priv->dma); } static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev) { - struct cpsw_priv *priv = netdev_priv(ndev); - return &priv->stats; + struct cpsw_priv *priv = netdev_priv(ndev); + return &priv->stats; } #ifdef CONFIG_NET_POLL_CONTROLLER static void cpsw_ndo_poll_controller(struct net_device *ndev) { - struct cpsw_priv *priv = netdev_priv(ndev); - - cpsw_intr_disable(priv); - cpdma_ctlr_int_ctrl(priv->dma, false); - cpsw_interrupt(ndev->irq, priv); - cpdma_ctlr_int_ctrl(priv->dma, true); - cpsw_intr_enable(priv); - cpdma_ctlr_eoi(priv->dma); + struct cpsw_priv *priv = netdev_priv(ndev); + + cpsw_intr_disable(priv); + cpdma_ctlr_int_ctrl(priv->dma, false); + cpsw_interrupt(ndev->irq, priv); + cpdma_ctlr_int_ctrl(priv->dma, true); + cpsw_intr_enable(priv); + cpdma_ctlr_eoi(priv->dma); } #endif @@ -885,12 +889,12 @@ static void cpsw_ndo_poll_controller(struct net_device *ndev) * */ static int cpsw_get_coalesce(struct net_device *ndev, - struct ethtool_coalesce *coal) + struct ethtool_coalesce *coal) { - struct cpsw_priv *priv = netdev_priv(ndev); + struct cpsw_priv *priv = netdev_priv(ndev); - coal->rx_coalesce_usecs = priv->coal_intvl; - return 0; + coal->rx_coalesce_usecs = priv->coal_intvl; + return 0; } /** @@ -902,451 +906,451 @@ static int cpsw_get_coalesce(struct net_device *ndev, * */ static int cpsw_set_coalesce(struct net_device *ndev, - struct ethtool_coalesce *coal) + struct ethtool_coalesce *coal) { - struct cpsw_priv *priv = netdev_priv(ndev); - u32 int_ctrl; - u32 num_interrupts = 0; - u32 prescale = 0; - u32 addnl_dvdr = 1; - u32 coal_intvl = 0; - - if (!coal->rx_coalesce_usecs) - return -EINVAL; - - coal_intvl = coal->rx_coalesce_usecs; - - int_ctrl = __raw_readl(&priv->ss_regs->int_control); - prescale = priv->bus_freq_mhz * 4; - - if (coal_intvl < CPSW_CMINTMIN_INTVL) - coal_intvl = CPSW_CMINTMIN_INTVL; - - if (coal_intvl > CPSW_CMINTMAX_INTVL) { - /* - * Interrupt pacer works with 4us Pulse, we can - * throttle further by dilating the 4us pulse. - */ - addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; - - if (addnl_dvdr > 1) { - prescale *= addnl_dvdr; - if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) - coal_intvl = (CPSW_CMINTMAX_INTVL - * addnl_dvdr); - } else { - addnl_dvdr = 1; - coal_intvl = CPSW_CMINTMAX_INTVL; - } - } - - num_interrupts = (1000 * addnl_dvdr) / coal_intvl; - - int_ctrl |= CPSW_INTPACEEN; - int_ctrl &= (~CPSW_INTPRESCALE_MASK); - int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); - __raw_writel(int_ctrl, &priv->ss_regs->int_control); - - __raw_writel(num_interrupts, &priv->ss_regs->rx_imax); - __raw_writel(num_interrupts, &priv->ss_regs->tx_imax); - - printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl); - priv->coal_intvl = coal_intvl; - - return 0; + struct cpsw_priv *priv = netdev_priv(ndev); + u32 int_ctrl; + u32 num_interrupts = 0; + u32 prescale = 0; + u32 addnl_dvdr = 1; + u32 coal_intvl = 0; + + if (!coal->rx_coalesce_usecs) + return -EINVAL; + + coal_intvl = coal->rx_coalesce_usecs; + + int_ctrl = __raw_readl(&priv->ss_regs->int_control); + prescale = priv->bus_freq_mhz * 4; + + if (coal_intvl < CPSW_CMINTMIN_INTVL) + coal_intvl = CPSW_CMINTMIN_INTVL; + + if (coal_intvl > CPSW_CMINTMAX_INTVL) { + /* + * Interrupt pacer works with 4us Pulse, we can + * throttle further by dilating the 4us pulse. + */ + addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; + + if (addnl_dvdr > 1) { + prescale *= addnl_dvdr; + if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) + coal_intvl = (CPSW_CMINTMAX_INTVL + * addnl_dvdr); + } else { + addnl_dvdr = 1; + coal_intvl = CPSW_CMINTMAX_INTVL; + } + } + + num_interrupts = (1000 * addnl_dvdr) / coal_intvl; + + int_ctrl |= CPSW_INTPACEEN; + int_ctrl &= (~CPSW_INTPRESCALE_MASK); + int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); + __raw_writel(int_ctrl, &priv->ss_regs->int_control); + + __raw_writel(num_interrupts, &priv->ss_regs->rx_imax); + __raw_writel(num_interrupts, &priv->ss_regs->tx_imax); + + printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl); + priv->coal_intvl = coal_intvl; + + return 0; } static const struct net_device_ops cpsw_netdev_ops = { - .ndo_open = cpsw_ndo_open, - .ndo_stop = cpsw_ndo_stop, - .ndo_start_xmit = cpsw_ndo_start_xmit, - .ndo_change_rx_flags = cpsw_ndo_change_rx_flags, - .ndo_set_mac_address = cpsw_ndo_set_mac_address, - .ndo_validate_addr = eth_validate_addr, - .ndo_tx_timeout = cpsw_ndo_tx_timeout, - .ndo_get_stats = cpsw_ndo_get_stats, + .ndo_open = cpsw_ndo_open, + .ndo_stop = cpsw_ndo_stop, + .ndo_start_xmit = cpsw_ndo_start_xmit, + .ndo_change_rx_flags = cpsw_ndo_change_rx_flags, + .ndo_set_mac_address = cpsw_ndo_set_mac_address, + .ndo_validate_addr = eth_validate_addr, + .ndo_tx_timeout = cpsw_ndo_tx_timeout, + .ndo_get_stats = cpsw_ndo_get_stats, #ifdef CONFIG_NET_POLL_CONTROLLER - .ndo_poll_controller = cpsw_ndo_poll_controller, + .ndo_poll_controller = cpsw_ndo_poll_controller, #endif }; static void cpsw_get_drvinfo(struct net_device *ndev, - struct ethtool_drvinfo *info) + struct ethtool_drvinfo *info) { - struct cpsw_priv *priv = netdev_priv(ndev); - strcpy(info->driver, "TI CPSW Driver v1.0"); - strcpy(info->version, "1.0"); - strcpy(info->bus_info, priv->pdev->name); + struct cpsw_priv *priv = netdev_priv(ndev); + strcpy(info->driver, "TI CPSW Driver v1.0"); + strcpy(info->version, "1.0"); + strcpy(info->bus_info, priv->pdev->name); } static u32 cpsw_get_msglevel(struct net_device *ndev) { - struct cpsw_priv *priv = netdev_priv(ndev); - return priv->msg_enable; + struct cpsw_priv *priv = netdev_priv(ndev); + return priv->msg_enable; } static void cpsw_set_msglevel(struct net_device *ndev, u32 value) { - struct cpsw_priv *priv = netdev_priv(ndev); - priv->msg_enable = value; + struct cpsw_priv *priv = netdev_priv(ndev); + priv->msg_enable = value; } static const struct ethtool_ops cpsw_ethtool_ops = { - .get_drvinfo = cpsw_get_drvinfo, - .get_msglevel = cpsw_get_msglevel, - .set_msglevel = cpsw_set_msglevel, - .get_link = ethtool_op_get_link, - .get_coalesce = cpsw_get_coalesce, - .set_coalesce = cpsw_set_coalesce, + .get_drvinfo = cpsw_get_drvinfo, + .get_msglevel = cpsw_get_msglevel, + .set_msglevel = cpsw_set_msglevel, + .get_link = ethtool_op_get_link, + .get_coalesce = cpsw_get_coalesce, + .set_coalesce = cpsw_set_coalesce, }; static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv) { - void __iomem *regs = priv->regs; - int slave_num = slave->slave_num; - struct cpsw_slave_data *data = priv->data.slave_data + slave_num; + void __iomem *regs = priv->regs; + int slave_num = slave->slave_num; + struct cpsw_slave_data *data = priv->data.slave_data + slave_num; - slave->data = data; - slave->regs = regs + data->slave_reg_ofs; - slave->sliver = regs + data->sliver_reg_ofs; + slave->data = data; + slave->regs = regs + data->slave_reg_ofs; + slave->sliver = regs + data->sliver_reg_ofs; } static int __devinit cpsw_probe(struct platform_device *pdev) { - struct cpsw_platform_data *data = pdev->dev.platform_data; - struct net_device *ndev; - struct cpsw_priv *priv; - struct cpdma_params dma_params; - struct cpsw_ale_params ale_params; - void __iomem *regs; - struct resource *res; - int ret = 0, i, k = 0; - - if (!data) { - pr_err("cpsw: platform data missing\n"); - return -ENODEV; - } - - ndev = alloc_etherdev(sizeof(struct cpsw_priv)); - if (!ndev) { - pr_err("cpsw: error allocating net_device\n"); - return -ENOMEM; - } - - platform_set_drvdata(pdev, ndev); - priv = netdev_priv(ndev); - spin_lock_init(&priv->lock); - priv->data = *data; - priv->pdev = pdev; - priv->ndev = ndev; - priv->dev = &ndev->dev; - priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); - priv->rx_packet_max = max(rx_packet_max, 128); - - if (is_valid_ether_addr(data->mac_addr)) { - memcpy(priv->mac_addr, data->mac_addr, ETH_ALEN); - printk(KERN_INFO"Detected MACID=%x:%x:%x:%x:%x:%x\n", - priv->mac_addr[0], priv->mac_addr[1], - priv->mac_addr[2], priv->mac_addr[3], - priv->mac_addr[4], priv->mac_addr[5]); - } else { - random_ether_addr(priv->mac_addr); - printk(KERN_INFO"Random MACID=%x:%x:%x:%x:%x:%x\n", - priv->mac_addr[0], priv->mac_addr[1], - priv->mac_addr[2], priv->mac_addr[3], - priv->mac_addr[4], priv->mac_addr[5]); - } - - memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); - - priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves, - GFP_KERNEL); - if (!priv->slaves) { - dev_err(priv->dev, "failed to allocate slave ports\n"); - ret = -EBUSY; - goto clean_ndev_ret; - } - for (i = 0; i < data->slaves; i++) - priv->slaves[i].slave_num = i; - - priv->clk = clk_get(&pdev->dev, NULL); - if (IS_ERR(priv->clk)) - dev_err(priv->dev, "failed to get device clock\n"); - - priv->coal_intvl = 0; - priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000; - - priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!priv->cpsw_res) { - dev_err(priv->dev, "error getting i/o resource\n"); - ret = -ENOENT; - goto clean_clk_ret; - } - - if (!request_mem_region(priv->cpsw_res->start, - resource_size(priv->cpsw_res), ndev->name)) { - dev_err(priv->dev, "failed request i/o region\n"); - ret = -ENXIO; - goto clean_clk_ret; - } - - regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res)); - if (!regs) { - dev_err(priv->dev, "unable to map i/o region\n"); - goto clean_cpsw_iores_ret; - } - priv->regs = regs; - priv->host_port = data->host_port_num; - priv->host_port_regs = regs + data->host_port_reg_ofs; - priv->hw_stats = regs + data->hw_stats_reg_ofs; - - priv->cpsw_ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (!priv->cpsw_ss_res) { - dev_err(priv->dev, "error getting i/o resource\n"); - ret = -ENOENT; - goto clean_clk_ret; - } - - if (!request_mem_region(priv->cpsw_ss_res->start, - resource_size(priv->cpsw_ss_res), ndev->name)) { - dev_err(priv->dev, "failed request i/o region\n"); - ret = -ENXIO; - goto clean_clk_ret; - } - - regs = ioremap(priv->cpsw_ss_res->start, - resource_size(priv->cpsw_ss_res)); - if (!regs) { - dev_err(priv->dev, "unable to map i/o region\n"); - goto clean_cpsw_ss_iores_ret; - } - priv->ss_regs = regs; - - - for_each_slave(priv, cpsw_slave_init, priv); - - omap_ctrl_writel(CPSW_TIMER_MASK, CPSW_TIMER_CAP_REG); - - /* Enable Timer for capturing cpsw rx interrupts */ - dmtimer_rx = omap_dm_timer_request_specific(CPSW_RX_TIMER_REQ); - omap_dm_timer_set_int_enable(dmtimer_rx, OMAP_TIMER_INT_CAPTURE); - omap_dm_timer_set_capture(dmtimer_rx, 1, 0, 0); - omap_dm_timer_enable(dmtimer_rx); - - /* Enable Timer for capturing cpsw tx interrupts */ - dmtimer_tx = omap_dm_timer_request_specific(CPSW_TX_TIMER_REQ); - omap_dm_timer_set_int_enable(dmtimer_tx, OMAP_TIMER_INT_CAPTURE); - omap_dm_timer_set_capture(dmtimer_tx, 1, 0, 0); - omap_dm_timer_enable(dmtimer_tx); - - memset(&dma_params, 0, sizeof(dma_params)); - dma_params.dev = &pdev->dev; - dma_params.dmaregs = (void __iomem *)(((u32)priv->regs) + - data->cpdma_reg_ofs); - dma_params.rxthresh = (void __iomem *)(((u32)priv->regs) + - data->cpdma_reg_ofs + CPDMA_RXTHRESH); - dma_params.rxfree = (void __iomem *)(((u32)priv->regs) + - data->cpdma_reg_ofs + CPDMA_RXFREE); - - if (data->version == CPSW_VERSION_2) { - dma_params.txhdp = (void __iomem *)(((u32)priv->regs) + - data->cpdma_reg_ofs + CPDMA_TXHDP_VER2); - dma_params.rxhdp = (void __iomem *)(((u32)priv->regs) + - data->cpdma_reg_ofs + CPDMA_RXHDP_VER2); - dma_params.txcp = (void __iomem *)(((u32)priv->regs) + - data->cpdma_reg_ofs + CPDMA_TXCP_VER2); - dma_params.rxcp = (void __iomem *)(((u32)priv->regs) + - data->cpdma_reg_ofs + CPDMA_RXCP_VER2); - } else { - dma_params.txhdp = (void __iomem *)(((u32)priv->regs) + - data->cpdma_reg_ofs + CPDMA_TXHDP_VER1); - dma_params.rxhdp = (void __iomem *)(((u32)priv->regs) + - data->cpdma_reg_ofs + CPDMA_RXHDP_VER1); - dma_params.txcp = (void __iomem *)(((u32)priv->regs) + - data->cpdma_reg_ofs + CPDMA_TXCP_VER1); - dma_params.rxcp = (void __iomem *)(((u32)priv->regs) + - data->cpdma_reg_ofs + CPDMA_RXCP_VER1); - } - - dma_params.num_chan = data->channels; - dma_params.has_soft_reset = true; - dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; - dma_params.desc_mem_size = data->bd_ram_size; - dma_params.desc_align = 16; - dma_params.has_ext_regs = true; - dma_params.desc_mem_phys = data->no_bd_ram ? 0 : - (u32 __force)priv->cpsw_res->start + data->bd_ram_ofs; - dma_params.desc_hw_addr = data->hw_ram_addr ? - data->hw_ram_addr : dma_params.desc_mem_phys ; - - priv->dma = cpdma_ctlr_create(&dma_params); - if (!priv->dma) { - dev_err(priv->dev, "error initializing dma\n"); - ret = -ENOMEM; - goto clean_iomap_ret; - } - - priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), - cpsw_tx_handler); - priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), - cpsw_rx_handler); - - if (WARN_ON(!priv->txch || !priv->rxch)) { - dev_err(priv->dev, "error initializing dma channels\n"); - ret = -ENOMEM; - goto clean_dma_ret; - } - - memset(&ale_params, 0, sizeof(ale_params)); - ale_params.dev = &ndev->dev; - ale_params.ale_regs = (void *)((u32)priv->regs) + - ((u32)data->ale_reg_ofs); - ale_params.ale_ageout = ale_ageout; - ale_params.ale_entries = data->ale_entries; - ale_params.ale_ports = data->slaves; - - priv->ale = cpsw_ale_create(&ale_params); - if (!priv->ale) { - dev_err(priv->dev, "error initializing ale engine\n"); - ret = -ENODEV; - goto clean_dma_ret; - } - - ndev->irq = platform_get_irq(pdev, 0); - if (ndev->irq < 0) { - dev_err(priv->dev, "error getting irq resource\n"); - ret = -ENOENT; - goto clean_ale_ret; - } - - while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { - for (i = res->start; i <= res->end; i++) { - if (request_irq(i, cpsw_interrupt, IRQF_DISABLED, - dev_name(&pdev->dev), priv)) { - dev_err(priv->dev, "error attaching irq\n"); - goto clean_ale_ret; - } - #ifdef CPSW_IRQ_QUIRK - priv->irqs_table[k] = i; - priv->num_irqs = k; - #endif - } - k++; - } - - ndev->flags |= IFF_ALLMULTI; /* see cpsw_ndo_change_rx_flags() */ - - ndev->netdev_ops = &cpsw_netdev_ops; - SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); - netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); - - /* register the network device */ - SET_NETDEV_DEV(ndev, &pdev->dev); - ret = register_netdev(ndev); - if (ret) { - dev_err(priv->dev, "error registering net device\n"); - ret = -ENODEV; - goto clean_irq_ret; - } - - msg(notice, probe, "initialized device (regs %x, irq %d)\n", - priv->cpsw_res->start, ndev->irq); - - return 0; + struct cpsw_platform_data *data = pdev->dev.platform_data; + struct net_device *ndev; + struct cpsw_priv *priv; + struct cpdma_params dma_params; + struct cpsw_ale_params ale_params; + void __iomem *regs; + struct resource *res; + int ret = 0, i, k = 0; + + if (!data) { + pr_err("cpsw: platform data missing\n"); + return -ENODEV; + } + + ndev = alloc_etherdev(sizeof(struct cpsw_priv)); + if (!ndev) { + pr_err("cpsw: error allocating net_device\n"); + return -ENOMEM; + } + + platform_set_drvdata(pdev, ndev); + priv = netdev_priv(ndev); + spin_lock_init(&priv->lock); + priv->data = *data; + priv->pdev = pdev; + priv->ndev = ndev; + priv->dev = &ndev->dev; + priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); + priv->rx_packet_max = max(rx_packet_max, 128); + + if (is_valid_ether_addr(data->mac_addr)) { + memcpy(priv->mac_addr, data->mac_addr, ETH_ALEN); + printk(KERN_INFO"Detected MACID=%x:%x:%x:%x:%x:%x\n", + priv->mac_addr[0], priv->mac_addr[1], + priv->mac_addr[2], priv->mac_addr[3], + priv->mac_addr[4], priv->mac_addr[5]); + } else { + random_ether_addr(priv->mac_addr); + printk(KERN_INFO"Random MACID=%x:%x:%x:%x:%x:%x\n", + priv->mac_addr[0], priv->mac_addr[1], + priv->mac_addr[2], priv->mac_addr[3], + priv->mac_addr[4], priv->mac_addr[5]); + } + + memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); + + priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves, + GFP_KERNEL); + if (!priv->slaves) { + dev_err(priv->dev, "failed to allocate slave ports\n"); + ret = -EBUSY; + goto clean_ndev_ret; + } + for (i = 0; i < data->slaves; i++) + priv->slaves[i].slave_num = i; + + priv->clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(priv->clk)) + dev_err(priv->dev, "failed to get device clock\n"); + + priv->coal_intvl = 0; + priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000; + + priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!priv->cpsw_res) { + dev_err(priv->dev, "error getting i/o resource\n"); + ret = -ENOENT; + goto clean_clk_ret; + } + + if (!request_mem_region(priv->cpsw_res->start, + resource_size(priv->cpsw_res), ndev->name)) { + dev_err(priv->dev, "failed request i/o region\n"); + ret = -ENXIO; + goto clean_clk_ret; + } + + regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res)); + if (!regs) { + dev_err(priv->dev, "unable to map i/o region\n"); + goto clean_cpsw_iores_ret; + } + priv->regs = regs; + priv->host_port = data->host_port_num; + priv->host_port_regs = regs + data->host_port_reg_ofs; + priv->hw_stats = regs + data->hw_stats_reg_ofs; + + priv->cpsw_ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!priv->cpsw_ss_res) { + dev_err(priv->dev, "error getting i/o resource\n"); + ret = -ENOENT; + goto clean_clk_ret; + } + + if (!request_mem_region(priv->cpsw_ss_res->start, + resource_size(priv->cpsw_ss_res), ndev->name)) { + dev_err(priv->dev, "failed request i/o region\n"); + ret = -ENXIO; + goto clean_clk_ret; + } + + regs = ioremap(priv->cpsw_ss_res->start, + resource_size(priv->cpsw_ss_res)); + if (!regs) { + dev_err(priv->dev, "unable to map i/o region\n"); + goto clean_cpsw_ss_iores_ret; + } + priv->ss_regs = regs; + + + for_each_slave(priv, cpsw_slave_init, priv); + + omap_ctrl_writel(CPSW_TIMER_MASK, CPSW_TIMER_CAP_REG); + + /* Enable Timer for capturing cpsw rx interrupts */ + dmtimer_rx = omap_dm_timer_request_specific(CPSW_RX_TIMER_REQ); + omap_dm_timer_set_int_enable(dmtimer_rx, OMAP_TIMER_INT_CAPTURE); + omap_dm_timer_set_capture(dmtimer_rx, 1, 0, 0); + omap_dm_timer_enable(dmtimer_rx); + + /* Enable Timer for capturing cpsw tx interrupts */ + dmtimer_tx = omap_dm_timer_request_specific(CPSW_TX_TIMER_REQ); + omap_dm_timer_set_int_enable(dmtimer_tx, OMAP_TIMER_INT_CAPTURE); + omap_dm_timer_set_capture(dmtimer_tx, 1, 0, 0); + omap_dm_timer_enable(dmtimer_tx); + + memset(&dma_params, 0, sizeof(dma_params)); + dma_params.dev = &pdev->dev; + dma_params.dmaregs = (void __iomem *)(((u32)priv->regs) + + data->cpdma_reg_ofs); + dma_params.rxthresh = (void __iomem *)(((u32)priv->regs) + + data->cpdma_reg_ofs + CPDMA_RXTHRESH); + dma_params.rxfree = (void __iomem *)(((u32)priv->regs) + + data->cpdma_reg_ofs + CPDMA_RXFREE); + + if (data->version == CPSW_VERSION_2) { + dma_params.txhdp = (void __iomem *)(((u32)priv->regs) + + data->cpdma_reg_ofs + CPDMA_TXHDP_VER2); + dma_params.rxhdp = (void __iomem *)(((u32)priv->regs) + + data->cpdma_reg_ofs + CPDMA_RXHDP_VER2); + dma_params.txcp = (void __iomem *)(((u32)priv->regs) + + data->cpdma_reg_ofs + CPDMA_TXCP_VER2); + dma_params.rxcp = (void __iomem *)(((u32)priv->regs) + + data->cpdma_reg_ofs + CPDMA_RXCP_VER2); + } else { + dma_params.txhdp = (void __iomem *)(((u32)priv->regs) + + data->cpdma_reg_ofs + CPDMA_TXHDP_VER1); + dma_params.rxhdp = (void __iomem *)(((u32)priv->regs) + + data->cpdma_reg_ofs + CPDMA_RXHDP_VER1); + dma_params.txcp = (void __iomem *)(((u32)priv->regs) + + data->cpdma_reg_ofs + CPDMA_TXCP_VER1); + dma_params.rxcp = (void __iomem *)(((u32)priv->regs) + + data->cpdma_reg_ofs + CPDMA_RXCP_VER1); + } + + dma_params.num_chan = data->channels; + dma_params.has_soft_reset = true; + dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; + dma_params.desc_mem_size = data->bd_ram_size; + dma_params.desc_align = 16; + dma_params.has_ext_regs = true; + dma_params.desc_mem_phys = data->no_bd_ram ? 0 : + (u32 __force)priv->cpsw_res->start + data->bd_ram_ofs; + dma_params.desc_hw_addr = data->hw_ram_addr ? + data->hw_ram_addr : dma_params.desc_mem_phys ; + + priv->dma = cpdma_ctlr_create(&dma_params); + if (!priv->dma) { + dev_err(priv->dev, "error initializing dma\n"); + ret = -ENOMEM; + goto clean_iomap_ret; + } + + priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), + cpsw_tx_handler); + priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), + cpsw_rx_handler); + + if (WARN_ON(!priv->txch || !priv->rxch)) { + dev_err(priv->dev, "error initializing dma channels\n"); + ret = -ENOMEM; + goto clean_dma_ret; + } + + memset(&ale_params, 0, sizeof(ale_params)); + ale_params.dev = &ndev->dev; + ale_params.ale_regs = (void *)((u32)priv->regs) + + ((u32)data->ale_reg_ofs); + ale_params.ale_ageout = ale_ageout; + ale_params.ale_entries = data->ale_entries; + ale_params.ale_ports = data->slaves; + + priv->ale = cpsw_ale_create(&ale_params); + if (!priv->ale) { + dev_err(priv->dev, "error initializing ale engine\n"); + ret = -ENODEV; + goto clean_dma_ret; + } + + ndev->irq = platform_get_irq(pdev, 0); + if (ndev->irq < 0) { + dev_err(priv->dev, "error getting irq resource\n"); + ret = -ENOENT; + goto clean_ale_ret; + } + + while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { + for (i = res->start; i <= res->end; i++) { + if (request_irq(i, cpsw_interrupt, IRQF_DISABLED, + dev_name(&pdev->dev), priv)) { + dev_err(priv->dev, "error attaching irq\n"); + goto clean_ale_ret; + } + #ifdef CPSW_IRQ_QUIRK + priv->irqs_table[k] = i; + priv->num_irqs = k; + #endif + } + k++; + } + + ndev->flags |= IFF_ALLMULTI; /* see cpsw_ndo_change_rx_flags() */ + + ndev->netdev_ops = &cpsw_netdev_ops; + SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); + netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); + + /* register the network device */ + SET_NETDEV_DEV(ndev, &pdev->dev); + ret = register_netdev(ndev); + if (ret) { + dev_err(priv->dev, "error registering net device\n"); + ret = -ENODEV; + goto clean_irq_ret; + } + + msg(notice, probe, "initialized device (regs %x, irq %d)\n", + priv->cpsw_res->start, ndev->irq); + + return 0; clean_irq_ret: - free_irq(ndev->irq, priv); + free_irq(ndev->irq, priv); clean_ale_ret: - cpsw_ale_destroy(priv->ale); + cpsw_ale_destroy(priv->ale); clean_dma_ret: - cpdma_chan_destroy(priv->txch); - cpdma_chan_destroy(priv->rxch); - cpdma_ctlr_destroy(priv->dma); + cpdma_chan_destroy(priv->txch); + cpdma_chan_destroy(priv->rxch); + cpdma_ctlr_destroy(priv->dma); clean_iomap_ret: - iounmap(priv->regs); + iounmap(priv->regs); clean_cpsw_ss_iores_ret: - release_mem_region(priv->cpsw_ss_res->start, - resource_size(priv->cpsw_ss_res)); + release_mem_region(priv->cpsw_ss_res->start, + resource_size(priv->cpsw_ss_res)); clean_cpsw_iores_ret: - release_mem_region(priv->cpsw_res->start, - resource_size(priv->cpsw_res)); + release_mem_region(priv->cpsw_res->start, + resource_size(priv->cpsw_res)); clean_clk_ret: - clk_put(priv->clk); - kfree(priv->slaves); + clk_put(priv->clk); + kfree(priv->slaves); clean_ndev_ret: - free_netdev(ndev); - return ret; + free_netdev(ndev); + return ret; } static int __devexit cpsw_remove(struct platform_device *pdev) { - struct net_device *ndev = platform_get_drvdata(pdev); - struct cpsw_priv *priv = netdev_priv(ndev); - - msg(notice, probe, "removing device\n"); - platform_set_drvdata(pdev, NULL); - - free_irq(ndev->irq, priv); - cpsw_ale_destroy(priv->ale); - cpdma_chan_destroy(priv->txch); - cpdma_chan_destroy(priv->rxch); - cpdma_ctlr_destroy(priv->dma); - iounmap(priv->regs); - release_mem_region(priv->cpsw_res->start, - resource_size(priv->cpsw_res)); - release_mem_region(priv->cpsw_ss_res->start, - resource_size(priv->cpsw_ss_res)); - clk_put(priv->clk); - kfree(priv->slaves); - free_netdev(ndev); - - return 0; + struct net_device *ndev = platform_get_drvdata(pdev); + struct cpsw_priv *priv = netdev_priv(ndev); + + msg(notice, probe, "removing device\n"); + platform_set_drvdata(pdev, NULL); + + free_irq(ndev->irq, priv); + cpsw_ale_destroy(priv->ale); + cpdma_chan_destroy(priv->txch); + cpdma_chan_destroy(priv->rxch); + cpdma_ctlr_destroy(priv->dma); + iounmap(priv->regs); + release_mem_region(priv->cpsw_res->start, + resource_size(priv->cpsw_res)); + release_mem_region(priv->cpsw_ss_res->start, + resource_size(priv->cpsw_ss_res)); + clk_put(priv->clk); + kfree(priv->slaves); + free_netdev(ndev); + + return 0; } static int cpsw_suspend(struct device *dev) { - struct platform_device *pdev = to_platform_device(dev); - struct net_device *ndev = platform_get_drvdata(pdev); + struct platform_device *pdev = to_platform_device(dev); + struct net_device *ndev = platform_get_drvdata(pdev); - if (netif_running(ndev)) - cpsw_ndo_stop(ndev); - return 0; + if (netif_running(ndev)) + cpsw_ndo_stop(ndev); + return 0; } static int cpsw_resume(struct device *dev) { - struct platform_device *pdev = to_platform_device(dev); - struct net_device *ndev = platform_get_drvdata(pdev); + struct platform_device *pdev = to_platform_device(dev); + struct net_device *ndev = platform_get_drvdata(pdev); - if (netif_running(ndev)) - cpsw_ndo_open(ndev); - return 0; + if (netif_running(ndev)) + cpsw_ndo_open(ndev); + return 0; } static const struct dev_pm_ops cpsw_pm_ops = { - .suspend = cpsw_suspend, - .resume = cpsw_resume, + .suspend = cpsw_suspend, + .resume = cpsw_resume, }; static struct platform_driver cpsw_driver = { - .driver = { - .name = "cpsw", - .owner = THIS_MODULE, - .pm = &cpsw_pm_ops, - }, - .probe = cpsw_probe, - .remove = __devexit_p(cpsw_remove), + .driver = { + .name = "cpsw", + .owner = THIS_MODULE, + .pm = &cpsw_pm_ops, + }, + .probe = cpsw_probe, + .remove = __devexit_p(cpsw_remove), }; static int __init cpsw_init(void) { - return platform_driver_register(&cpsw_driver); + return platform_driver_register(&cpsw_driver); } late_initcall(cpsw_init); static void __exit cpsw_exit(void) { - platform_driver_unregister(&cpsw_driver); + platform_driver_unregister(&cpsw_driver); } module_exit(cpsw_exit); -- 1.7.10.4