//--------------------------------------------------------------------------
    // UPPCTL - tx/rx selection, data width, data format, data rate,
    //            data interleave enable
    //--------------------------------------------------------------------------
    iowrite32( 0x02020007, (void *)(upp_base + UPCTL) );
    reg_val = ioread32( (void *)(upp_base + UPCTL) );
    //    printk( KERN_ALERT "UPCTL = 0x%08x\n", reg_val);

    //--------------------------------------------------------------------------
    // UPPICR - signal enable, signal inversion, clk div (tx only)
    //--------------------------------------------------------------------------
    //    iowrite32( 0x0F180F20, (void *)(upp_base + UPICR) );
    //    iowrite32( 0x0F180F20, (void *)(upp_base + UPICR) );
    iowrite32( 0x0F180F20, (void *)(upp_base + UPICR) );
    reg_val = ioread32( (void *)(upp_base + UPICR) );
    //    printk( KERN_ALERT "UPICR = 0x%08x\n", reg_val);

    //--------------------------------------------------------------------------
    // UPPIVR - idle value (tx only)
    //--------------------------------------------------------------------------
    iowrite32( 0x1234, (void *)(upp_base + UPIVR) );
    reg_val = ioread32( (void *)(upp_base + UPIVR) );
    //    printk( KERN_ALERT "UPIVR = 0x%08x\n", reg_val);

    //--------------------------------------------------------------------------
    // UPPTCR - i/o tx thresh (tx only), dma read burst size
    //--------------------------------------------------------------------------
    //    iowrite32( 0x00010100, (void *)(upp_base + UPTCR) );
    iowrite32( 0x00000000, (void *)(upp_base + UPTCR) );
    reg_val = ioread32( (void *)(upp_base + UPTCR) );
    //    printk( KERN_ALERT "UPTCR = 0x%08x\n", reg_val);

    //--------------------------------------------------------------------------
    // UPPDLB - digital loopback
    //--------------------------------------------------------------------------
    if ( UPP_CFG_DOLOOPBACK )
    {
        iowrite32( 0x00001000, (void *)(upp_base + UPDLB) );
    }
    else
    {
        iowrite32( 0x00000000, (void *)(upp_base + UPDLB) );
    }


//the rxdma_line_size and txdma_line_size are bot 0x40 
// the rxdma_line_count and txdma_line count are both 0x01
    //--------------------------------------------------------------------------
    // UPQD0 - Channel B (Rx)
    //--------------------------------------------------------------------------
    iowrite32( rx_start_addr, (void *)(upp_base + UPQD0) );
    printk( KERN_ALERT "UPQD0 = 0x%08x\n", *(int32_t *)(upp_base + UPQD0));

    //--------------------------------------------------------------------------
    // UPQD1 - Channel B (Rx)
    //--------------------------------------------------------------------------
    iowrite32( (rxdma_line_count << 16 | rxdma_line_size),
            (void *)(upp_base + UPQD1) );
    printk( KERN_ALERT "UPQD1 = 0x%08x\n", *(int32_t *)(upp_base + UPQD1));

    //--------------------------------------------------------------------------
    // UPQD2 - Channel B (Rx)
    //--------------------------------------------------------------------------
    iowrite32( rxdma_line_size, (void *)(upp_base + UPQD2) );
    printk( KERN_ALERT "UPQD2 = 0x%08x\n", *(int32_t *)(upp_base + UPQD2));

    return 0;
}


//static int upp_txdma_config( upp_dev_t *dev )
static int upp_txdma_config( void)
{
  //    int32_t reg_val;

    // wait for dma active/pending bits to clear
    while ( ioread32( upp_base + UPIS2 ) & 0x00000002 )
        ;


    //==========================================================================
    // Program DMA channel desc. reg's
    //   - UPID0-2 and/or UPQD0-2.
    //==========================================================================

    //--------------------------------------------------------------------------
    // UPID0 - Channel A (Tx)
    //--------------------------------------------------------------------------
    iowrite32( tx_start_addr, (void *)(upp_base + UPID0) );
    printk( KERN_ALERT "UPID0 = 0x%08x\n", *(int32_t *)(upp_base + UPID0));

    //--------------------------------------------------------------------------
    // UPID1 - Channel A (Tx)
    //--------------------------------------------------------------------------
    iowrite32( (txdma_line_count << 16 | txdma_line_size),
            (void *)(upp_base + UPID1) );
    printk( KERN_ALERT "UPID1 = 0x%08x\n", *(int32_t *)(upp_base + UPID1));

    //--------------------------------------------------------------------------
    // UPID2 - Channel A (Tx)
    //--------------------------------------------------------------------------
    iowrite32( txdma_line_size, (void *)(upp_base + UPID2) );
    printk( KERN_ALERT "UPID2 = 0x%08x\n", *(int32_t *)(upp_base + UPID2));


    return 0;
}