MityDSP-L138 (ARM9 Based Platforms): Software Development
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2024-03-07T20:48:12Z
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Software Development: RE: DSP FPGA EMIF GPIO Failure
http://support.criticallink.com/redmine/boards/10/topics/6582?r=6588#message-6588
2024-03-07T20:48:12Z
Jonathan Cormier
jcormier@criticallink.com
<p>Alright, let's simplify. The base module's register 0 contains some version info. You can read it 4 times in a row and then it will start repeating. For example on my board:<br /><pre>
root@mityomapl138:~# memtool 0x66000000 1
Reading 0x1 count starting at address 0x66000000
0x66000000: 00000000 <-------
root@mityomapl138:~# memtool 0x66000000 1
Reading 0x1 count starting at address 0x66000000
0x66000000: 00004A11 <-------
root@mityomapl138:~# memtool 0x66000000 1
Reading 0x1 count starting at address 0x66000000
0x66000000: 0000891B <-------
root@mityomapl138:~# memtool 0x66000000 1
Reading 0x1 count starting at address 0x66000000
0x66000000: 0000C000 <-------
root@mityomapl138:~# memtool 0x66000000 1
Reading 0x1 count starting at address 0x66000000
0x66000000: 00000000 <-------
</pre></p>
<p>If you can read this register from the DSP and get the four different values then you will at least know your talking to the FPGA correctly.</p>
Software Development: RE: DSP FPGA EMIF GPIO Failure
http://support.criticallink.com/redmine/boards/10/topics/6582?r=6584#message-6584
2024-03-06T00:50:10Z
Kyungguk Bok
<p>Thank you for answer.</p>
<p>I modified the part you mentioned and changed it to 0x66000080, but it still doesn't work.</p>
<p>today<br /><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Quick_Start">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Quick_Start</a><br />I've tried loading it all, but the .out file is loaded but doesn't seem to work.</p>
<p>Is there anything else I need to do to get it to work?</p>
<p>p.s By changing the HelloDSP example in a Linux environment, I was able to control the FPGA's GPIO.<br />By executing the command below, we were able to confirm that the .out file was executed and the FPGA's GPIO was controlled.<br />clipboard-202403060949-yen2s.png</p>
Software Development: RE: DSP FPGA EMIF GPIO Failure
http://support.criticallink.com/redmine/boards/10/topics/6582?r=6583#message-6583
2024-03-05T17:05:23Z
Jonathan Cormier
jcormier@criticallink.com
<p>Kyungguk Bok wrote:</p>
<blockquote>
<p>hello.</p>
<p>I am having a problem controlling GPIO with MityDSP-L138F through DSP and FPGA EMIF communication, so I am leaving a question.</p>
<p>FPGA source</p>
<p>constant CORE_BASE_MODULE: integer := 0;<br />constant CORE_TS_MODULE : integer := 5;<br />constant CORE_I2C_MODULE : integer := 2;<br />constant CORE_LCD_MODULE : integer := 3;<br />constant CORE_DVI_MODULE : integer := 4;<br />constant CORE_GPIO_MODULE : integer := 1;<br />constant CORE_PWM_MODULE : integer := 6;</p>
<p>constant CORE_GPIO_IRQ_LEVEL : integer := 1; --DSP: 1, ARM: 0<br />constant CORE_GPIO_IRQ_VECTOR : integer := 1;</p>
<p>gpio1 : gpio<br />generic map (<br />NUM_BANKS => 1,<br />NUM_IO_PER_BANK => 2<br />)<br />Port Map (<br />clk => ema_clk,<br />i_ABus => addr_r,<br />i_DBus => edi_r,<br />o_DBus => edo_arm(CORE_GPIO_MODULE),--edo_dsp(CORE_GPIO_MODULE),<br />i_wr_en => wr_r,<br />i_rd_en => rd_r,<br />i_cs => arm_cs5_r(CORE_GPIO_MODULE),--dsp_cs4_r(CORE_GPIO_MODULE),<br />o_irq => irq_map(CORE_GPIO_IRQ_LEVEL)(CORE_GPIO_IRQ_VECTOR);<br />i_ilevel => conv_std_logic_vector(CORE_GPIO_IRQ_LEVEL, 2);<br />i_ivector => conv_std_logic_vector(CORE_GPIO_IRQ_VECTOR, 4);<br />i_io => "00",<br />t_io => open,<br />o_io => o_diode,--s_diode,--o_diode,<br />i_initdir => "11",<br />i_initoutval => "00" <br />);</p>
<p>DSP source</p>
<p>int main()
{<br />tcDspFirmware::set_firmware_base((void*)FPGA_BASE_ADDR);</p>
<p>MityDSP::tcDspFpgaGpio* mpGpio;<br />mpGpio = new tcDspFpgaGpio((void*)0x66000080);</p>
<p>mpGpio->SetPinDirection(0,0,true,0);<br />mpGpio->SetPinDirection(0,1,true,0);</p>
<p>mpGpio->SetPinValue(0,0,1);<br />mpGpio->SetPinValue(0,1,1);</p>
<p>return 0;<br />}</p>
<p>Is there anything strange about the above source?<br />Measured with a chipscope, there is no change.<br />(Attach photos.)</p>
<p>Is it true that the .out file was loaded in the u-boot environment as shown below, and the .out file was executed properly?<br />(I tried saving it to Nand flash and loading it, but the result is the same.)</p>
<p>Aside from this, FPGA GPIO control through fpga_ctrl.ko and fpga_gpio.ko on ARM works well.</p>
</blockquote>
<p>Okay, so that should mean your fpga code is fine. Note its a good idea to make sure the fpga_gpio.ko kernel module isn't loaded if you are trying to control it from the DSP. They could fight each other.</p>
<p>Note your u-boot log shows the GPIO core is loaded at 0x66000280. Not 0x66000080</p>
<p><img src="http://support.criticallink.com/redmine/attachments/download/35183/clipboard-202403051204-ids1j.png" alt="" /></p>
Software Development: DSP FPGA EMIF GPIO Failure
http://support.criticallink.com/redmine/boards/10/topics/6582
2024-03-04T09:29:05Z
Kyungguk Bok
<p>hello.</p>
<p>I am having a problem controlling GPIO with MityDSP-L138F through DSP and FPGA EMIF communication, so I am leaving a question.</p>
<p>FPGA source</p>
<p>constant CORE_BASE_MODULE: integer := 0;<br />constant CORE_TS_MODULE : integer := 5;<br />constant CORE_I2C_MODULE : integer := 2;<br />constant CORE_LCD_MODULE : integer := 3;<br />constant CORE_DVI_MODULE : integer := 4;<br />constant CORE_GPIO_MODULE : integer := 1;<br />constant CORE_PWM_MODULE : integer := 6;</p>
<p>constant CORE_GPIO_IRQ_LEVEL : integer := 1; --DSP: 1, ARM: 0<br />constant CORE_GPIO_IRQ_VECTOR : integer := 1;</p>
<p>gpio1 : gpio<br /> generic map (<br /> NUM_BANKS => 1,<br /> NUM_IO_PER_BANK => 2<br />)<br />Port Map (<br /> clk => ema_clk,<br /> i_ABus => addr_r,<br /> i_DBus => edi_r,<br /> o_DBus => edo_arm(CORE_GPIO_MODULE),--edo_dsp(CORE_GPIO_MODULE),<br /> i_wr_en => wr_r,<br /> i_rd_en => rd_r,<br /> i_cs => arm_cs5_r(CORE_GPIO_MODULE),--dsp_cs4_r(CORE_GPIO_MODULE),<br /> o_irq => irq_map(CORE_GPIO_IRQ_LEVEL)(CORE_GPIO_IRQ_VECTOR);<br /> i_ilevel => conv_std_logic_vector(CORE_GPIO_IRQ_LEVEL, 2);<br /> i_ivector => conv_std_logic_vector(CORE_GPIO_IRQ_VECTOR, 4);<br /> i_io => "00",<br /> t_io => open,<br /> o_io => o_diode,--s_diode,--o_diode,<br /> i_initdir => "11",<br /> i_initoutval => "00" <br />);</p>
<p>DSP source</p>
<p>int main()
{<br /> tcDspFirmware::set_firmware_base((void*)FPGA_BASE_ADDR);</p>
<pre><code>MityDSP::tcDspFpgaGpio* mpGpio;<br /> mpGpio = new tcDspFpgaGpio((void*)0x66000080);</code></pre>
<pre><code>mpGpio->SetPinDirection(0,0,true,0);<br /> mpGpio->SetPinDirection(0,1,true,0);</code></pre>
<pre><code>mpGpio->SetPinValue(0,0,1);<br /> mpGpio->SetPinValue(0,1,1);</code></pre>
<pre><code>return 0;<br />}</code></pre>
<p>Is there anything strange about the above source?<br />Measured with a chipscope, there is no change.<br />(Attach photos.)</p>
<p>Is it true that the .out file was loaded in the u-boot environment as shown below, and the .out file was executed properly?<br />(I tried saving it to Nand flash and loading it, but the result is the same.)</p>
<p>Aside from this, FPGA GPIO control through fpga_ctrl.ko and fpga_gpio.ko on ARM works well.</p>
<p>I would appreciate your reply.</p>
Software Development: RE: DSP EMIF Example Code
http://support.criticallink.com/redmine/boards/10/topics/6567?r=6581#message-6581
2024-02-19T20:24:36Z
Jonathan Cormier
jcormier@criticallink.com
<p>Kyungguk Bok wrote in <a class="message" href="http://support.criticallink.com/redmine/boards/10/topics/6567?r=6580#message-6580">RE: DSP EMIF Example Code</a>:</p>
<blockquote>
<p>Thank you for answer.</p>
<p><em>It's not a bad idea to make sure you can control the gpio from Linux before operating it on your DSP.</em></p>
<p>I think that's a good thing to say. I think it's a good idea to solve problems one by one.</p>
<p><i>How did you calculate 144? It would be helpful if you posted additional details.</i></p>
<p>Rather than calculating gpiochip144 separately, it was checked in the FPGA GPIO Core Example section of the wiki below.<br /><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Core_Device_Drivers">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Core_Device_Drivers</a><br />Among the contents of the above wiki, there is the following. I don't understand this part.</p>
<p>“FPGA GPIO core pins start at pin #144Linux side.<br />So pin #144 is mapped to the first gpio of the first gpio core. The gpio core is then connected to a net name that maps to the fpga pin name in the .ucf file. For an example, see $MDK/examples/industrial_io/fpga/vhdl/IndustrialIO_rev_C.ucf."</p>
</blockquote>
<p>Yup, so you should be able to export gpio 144 and access the gpio<br /><pre>
cd /sys/class/gpio
export 144 > export
cd gpio144
cat value
cat direction
</pre></p>
<blockquote>
<p>I have one more additional question.<br />As far as I know, the above method seems to follow the DSP->ARM->FPGA format to control FPGA. Is it possible to control directly with DSP->FPGA?</p>
</blockquote>
<p>The tcDspFpgaGpio code, writes directly to the mapped EMIF register address space so the ARM isn't involved.</p>
Software Development: RE: DSP EMIF Example Code
http://support.criticallink.com/redmine/boards/10/topics/6567?r=6580#message-6580
2024-02-16T01:52:26Z
Kyungguk Bok
<p>Thank you for answer.</p>
<p><em>It's not a bad idea to make sure you can control the gpio from Linux before operating it on your DSP.</em></p>
<p>I think that's a good thing to say. I think it's a good idea to solve problems one by one.</p>
<p><i>How did you calculate 144? It would be helpful if you posted additional details.</i></p>
<p>Rather than calculating gpiochip144 separately, it was checked in the FPGA GPIO Core Example section of the wiki below.<br /><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Core_Device_Drivers">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Core_Device_Drivers</a><br />Among the contents of the above wiki, there is the following. I don't understand this part.</p>
<p>“FPGA GPIO core pins start at pin #144Linux side.<br />So pin #144 is mapped to the first gpio of the first gpio core. The gpio core is then connected to a net name that maps to the fpga pin name in the .ucf file. For an example, see $MDK/examples/industrial_io/fpga/vhdl/IndustrialIO_rev_C.ucf."</p>
<p>I have one more additional question.<br />As far as I know, the above method seems to follow the DSP->ARM->FPGA format to control FPGA. Is it possible to control directly with DSP->FPGA?</p>
Software Development: RE: DSP EMIF Example Code
http://support.criticallink.com/redmine/boards/10/topics/6567?r=6579#message-6579
2024-02-15T20:51:29Z
Jonathan Cormier
jcormier@criticallink.com
<p>Kyungguk Bok wrote in <a class="message" href="http://support.criticallink.com/redmine/boards/10/topics/6567?r=6578#message-6578">RE: DSP EMIF Example Code</a>:</p>
<blockquote>
<p>Thank you for answer.<br />(using MityDSP-L138F Devkit)<br />When using EMIFA to control the LED by controlling the FPGA's GPIO, I found out that EMIFA is set in the kernel when the fpga_ctrl.ko and fpga_gpio.ko module files are loaded.</p>
</blockquote>
<p>I'm pretty sure the EMIFA will get configured before fpga_ctrl.ko and fpga_gpio.ko module files are loaded. So they aren't strictly required as long as the fpga is loaded in u-boot. fpga_ctrl is needed to program the FPGA from linux.</p>
<blockquote>
<p>I also found out that I can control the FPGA's GPIO from the DSP through the DspFpgaGpio.cpp source.</p>
</blockquote>
<p>yes</p>
<blockquote>
<p>Then, next, I would like to randomly control pin C10 of the FPGA to turn the LED on/off.<br />(Pin C10 is connected to DISP A3 P.)<br />In this case, how should I set the Pin?<br />gpiochip144 does not exist in the /sys/class/gpio path.</p>
</blockquote>
<p>How did you calculate 144? Posting additional details would be helpful.<br />Read <a class="external" href="https://www.kernel.org/doc/Documentation/gpio/sysfs.txt">https://www.kernel.org/doc/Documentation/gpio/sysfs.txt</a>, for how to control gpios via /sys/class/gpio. Its not a bad idea to make sure you can control the gpio in linux before trying to get it working in the DSP.</p>
<blockquote>
<p>'int tcDspFpgaGpio::SetPinDirection(unsigned int Bank, unsigned int Offset,bool IsOutput, unsigned int Value)'<br />'int tcDspFpgaGpio::SetPinValue(unsigned int Bank, unsigned int Offset, unsigned int Value)'<br />I need to set it using a function such as Bank=0, etc. How should I input it into the variable?</p>
</blockquote>
Software Development: RE: DSP EMIF Example Code
http://support.criticallink.com/redmine/boards/10/topics/6567?r=6578#message-6578
2024-02-15T04:36:58Z
Kyungguk Bok
<p>Thank you for answer.<br />(using MityDSP-L138F Devkit)<br />When using EMIFA to control the LED by controlling the FPGA's GPIO, I found out that EMIFA is set in the kernel when the fpga_ctrl.ko and fpga_gpio.ko module files are loaded. I also found out that I can control the FPGA's GPIO from the DSP through the DspFpgaGpio.cpp source.<br />Is my understanding correct?<br />Then, next, I would like to randomly control pin C10 of the FPGA to turn the LED on/off.<br />(Pin C10 is connected to DISP A3 P.)<br />In this case, how should I set the Pin?<br />gpiochip144 does not exist in the /sys/class/gpio path.</p>
<p>'int tcDspFpgaGpio::SetPinDirection(unsigned int Bank, unsigned int Offset,bool IsOutput, unsigned int Value)'<br />'int tcDspFpgaGpio::SetPinValue(unsigned int Bank, unsigned int Offset, unsigned int Value)'<br />I need to set it using a function such as Bank=0, etc. How should I input it into the variable?</p>
Software Development: RE: DSP EMIF Example Code
http://support.criticallink.com/redmine/boards/10/topics/6567?r=6577#message-6577
2024-02-13T20:11:20Z
Jonathan Cormier
jcormier@criticallink.com
<blockquote>
<p>If you try to write code related to EMIF in CCS, you will need a header file called csl.emifa.h. How can EMIF be performed without the need for a header file? I would like some basic information about EMIF.</p>
</blockquote>
<p>The kernel sets up the emif bus for you, there should be no need to modify the configuration from the DSP.<br />Greg's explanation mentions that the EMIF is memory mapping the physical memory address 0x6000_0000 to the FPGA cores. So your code in the DSP can read/write directly to/from memory at that address and the EMIF will handle sending/receiving to the FPGA.</p>
<blockquote>
<p>In short, if you want to implement a custom FPGA core on the EMIF bus I would look at the source for i2c or any of the other cores supplied in the MDK. From the perspective of the DSP you just need to know that the FPAG EMIF space starts at physical address 0x6000_0000 and each core added properly in the FPGA will start on a multiple of 0x80.</p>
</blockquote>
<p>In MDK_2014-01-13, the camera demo sw interacts with a FPGA pwm and gpio core. The constructor for the tcDspFpgaGpio class takes a memory address to where the fpga core is mapped into memory as Greg described. Please review the gpio and other DspFpga* classes in MDK_2014-01-13/sw/DSP/lib/core/</p>
<p>MDK_2014-01-13/examples/industrial_io/cam_demo_sw/DSP/cam_demo/VideoApp.cpp:<br /><code>mpGpio = new tcDspFpgaGpio((void*)0x66000280);</code></p>
<p>The MDK can be downloaded on the following page: <a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Board_Support_Package">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Board_Support_Package</a></p>
Software Development: RE: DSP EMIF Example Code
http://support.criticallink.com/redmine/boards/10/topics/6567?r=6575#message-6575
2024-02-13T00:06:02Z
Kyungguk Bok
<p>Thank you for answer.<br />Currently working on MityDSP-L138F.<br />The kernel is loaded on ARM, and HelloworldDSP and FPGA from Wiki have been converted to .bin files so that they are automatically loaded upon booting.<br />If you try to write code related to EMIF in CCS, you will need a header file called csl.emifa.h. How can EMIF be performed without the need for a header file? I would like some basic information about EMIF.<br />I would be grateful if you could answer any questions I may have, even if they are incomplete.</p>
Software Development: RE: DSP EMIF Example Code
http://support.criticallink.com/redmine/boards/10/topics/6567?r=6571#message-6571
2024-02-08T15:31:20Z
Jonathan Cormier
jcormier@criticallink.com
<p>Could you provide an example of what you are trying? I don't believe you should need any special headers, assuming the kernel is loaded and configured the EMIF bus on the ARM.</p>
Software Development: RE: DSP EMIF Example Code
http://support.criticallink.com/redmine/boards/10/topics/6567?r=6570#message-6570
2024-02-08T00:19:51Z
Kyungguk Bok
<p>Thank you for answer.<br />The environment I am currently studying is Linux (Ubuntu).<br />(.ova file downloaded and installed from wiki)<br />I am using code composer studio 7.5.0. When I try to code EMIF with DSP in this environment, it says I need the csl_emifa.h file.<br />Is it difficult to code .ova for EMIF?<br />First of all, the necessary include files for CSL have been installed and attached.<br />Is there anything else you need?<br />More study is still needed, but information is limited.<br />Sorry for the beginner question. I would appreciate your reply.</p>
Software Development: RE: DSP EMIF Example Code
http://support.criticallink.com/redmine/boards/10/topics/6567?r=6569#message-6569
2024-02-08T00:18:03Z
Kyungguk Bok
<p>답변 감사합니다.<br />지금 제가 공부하고 있는 환경은 리눅스(우분투)입니다.<br />(wiki에서 다운 받아 설치한 .ova파일)<br />code composer studio 7.5.0을 사용하고 있습니다. 이 환경에서 DSP로 EMIF에 관해 코딩하려고하니, csl_emifa.h 파일이 필요하다고 합니다.<br />.ova에는 EMIF에 관해 코드를 진행하기 어려운 상황입니까? <br />우선 CSL에 관해 필요한 include파일을 설치하고 첨부한 상황이긴 합니다. <br />혹시 다른 필요한게 있을까요? <br />아직 공부가 더 필요하지만, 정보를 얻을 데가 한정적입니다. <br />초보적인 질문이라 죄송합니다. 답변 주시면 감사하겠습니다.</p>
Software Development: RE: DSP EMIF Example Code
http://support.criticallink.com/redmine/boards/10/topics/6567?r=6568#message-6568
2024-02-07T16:23:13Z
Gregory Gluszek
<p>Hello Kyungguk Bok,</p>
<p>From the FPGA perspective the base_module component handles the EMIF transactions and converts then to an internal bus format so that you can have multiple FPGA components (or Cores as we call them) that sit on the EMIF bus at regularly spaced intervals.</p>
<p>If we look at IndustialIO_top.vhd, first we have the base_module instantiation:<br /><pre>
bm : base_module
generic map (
CONFIG => "MityDSP_L138",
GEN_XADC_PORT => GEN_XADC_PORT
)
port map (
ema_clk => ema_clk,
i_cs => arm_cs5_r(CORE_BASE_MODULE),
i_ID => FPGA_APPLICATION_ID,
i_version_major => FPGA_VERSION_MAJOR,
i_version_minor => FPGA_VERSION_MINOR,
i_year => FPGA_YEAR,
i_month => FPGA_MONTH,
i_day => FPGA_DAY,
i_ABus => addr_r,
i_DBus => edi_r,
o_DBus => edo_arm(CORE_BASE_MODULE),
i_wr_en => wr_r,
i_rd_en => rd_r,
i_be_r => be_r,
o_dcm_reset => open,
i_dcm_status => dcm_status,
i_dcm_lock => dcm_lock,
i_irq_map => irq_map,
o_irq_output => o_int
);
</pre></p>
<p>Next we will focus on the i2c FPGA Core:</p>
<pre>
i2cctrl : i2c
Port Map (
clk => ema_clk,
i_ABus => addr_r,
i_DBus => edi_r,
o_DBus => edo_arm(CORE_I2C_MODULE),
i_wr_en => wr_r,
i_rd_en => rd_r,
i_cs => arm_cs5_r(CORE_I2C_MODULE),
o_irq => irq_map(CORE_I2C_IRQ_LEVEL)(CORE_I2C_IRQ_VECTOR),
i_ilevel => conv_std_logic_vector(CORE_I2C_IRQ_LEVEL, 2),
i_ivector => conv_std_logic_vector(CORE_I2C_IRQ_VECTOR, 4),
i_sda => io_sda,
o_sda => sda,
o_sdt => t_sda,
o_scl => o_scl
);
</pre>
<p>If we specifically focus on the ports relating to handle EMIF reads and writes:<br /><pre>
clk => ema_clk,
i_ABus => addr_r,
i_DBus => edi_r,
o_DBus => edo_arm(CORE_I2C_MODULE),
i_wr_en => wr_r,
i_rd_en => rd_r,
</pre></p>
<p>We have a clock, address, data in, data out, write enable and read enable. These signals translates EMIF reads and write specific to that core. When I say "specific to that core" the idea here is that the FPGA EMIF memory space starts at physical address 0x6000_0000 from the perspective of the ARM/DSP. Then each FPGA core starts its address space at an offset of 0x80. For example, CORE_I2C_MODULE is set to 2, meaning that EMIF reads/writes from 0x6000_0100 to 0x600_017C will correspond to read/writes to the i2c core.</p>
<p>In short, if you want to implement a custom FPGA core on the EMIF bus I would look at the source for i2c or any of the other cores supplied in the MDK. From the perspective of the DSP you just need to know that the FPAG EMIF space starts at physical address 0x6000_0000 and each core added properly in the FPGA will start on a multiple of 0x80.</p>
<p>Thanks,<br />Greg</p>
Software Development: DSP EMIF Example Code
http://support.criticallink.com/redmine/boards/10/topics/6567
2024-02-07T08:02:14Z
Kyungguk Bok
<p>hello everyone</p>
<p>I am a first time user of MityDSP-L138. Ultimately, I am studying with the goal of receiving ADC data from FPGA and processing it in DSP.<br />I solved the problem by running the DSP and ARM Eaxmple on the wiki page and loading the FPGA .bit file and .bin file.<br />The next step is to communicate with the FPGA and DSP. It seems that EMIF is used as a communication method. Can I get an example code for EMIF communication from DSP and an EMIF example code from FPGA?<br />We are loading and examining the IndustialIO_top.vhd file in the FPGA.<br />Can I find a page or resource where I can get the example code for EMIF?</p>
Software Development: RE: linux-v4.19 kernel
http://support.criticallink.com/redmine/boards/10/topics/6503?r=6510#message-6510
2023-10-03T17:49:22Z
Richard Miller-Smith
richard@darwin-innovation.com
<p>Thanks, any hints would be much appreciated.</p>
Software Development: RE: linux-v4.19 kernel
http://support.criticallink.com/redmine/boards/10/topics/6503?r=6509#message-6509
2023-10-03T17:39:00Z
Jonathan Cormier
jcormier@criticallink.com
<p>Okay looks like we didn't document our yocto build for the L138. I'll see if I can capture the steps if your interested.</p>
<p>The files section contains a sdcard image and filesystem for the 2018.04 release.<br /><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/files">https://support.criticallink.com/redmine/projects/arm9-platforms/files</a></p>
Software Development: RE: linux-v4.19 kernel
http://support.criticallink.com/redmine/boards/10/topics/6503?r=6508#message-6508
2023-10-03T17:26:39Z
Richard Miller-Smith
richard@darwin-innovation.com
<p>Indeed, I should have said, I don't need it for this project.</p>
Software Development: RE: linux-v4.19 kernel
http://support.criticallink.com/redmine/boards/10/topics/6503?r=6507#message-6507
2023-10-03T17:20:09Z
Jonathan Cormier
jcormier@criticallink.com
<p>Richard Miller-Smith wrote in <a class="message" href="http://support.criticallink.com/redmine/boards/10/topics/6503?r=6506#message-6506">RE: linux-v4.19 kernel</a>:</p>
<blockquote>
<p>Thanks Jonathan,</p>
<p>We were indeed using a v3.2 kernel built with the 2012 tools. However, I'll try using the newer MDK and research Yocto a bit more (it's rather passed me by so far).</p>
<p>I'll let you know how I get on.</p>
</blockquote>
<p>I assume your not using the DSP/dspbios then?</p>
Software Development: RE: linux-v4.19 kernel
http://support.criticallink.com/redmine/boards/10/topics/6503?r=6506#message-6506
2023-10-03T17:15:51Z
Richard Miller-Smith
richard@darwin-innovation.com
<p>Thanks Jonathan,</p>
<p>We were indeed using a v3.2 kernel built with the 2012 tools. However, I'll try using the newer MDK and research Yocto a bit more (it's rather passed me by so far).</p>
<p>I'll let you know how I get on.</p>
Software Development: RE: linux-v4.19 kernel
http://support.criticallink.com/redmine/boards/10/topics/6503?r=6505#message-6505
2023-10-03T17:01:15Z
Jonathan Cormier
jcormier@criticallink.com
<blockquote>
<p>I've seen that there are still commits going into your linux-davinci repository and even an updated linux-v4.19 kernel. I've given this a very quick try with a modern buildroot, but not getting very far (no kernel output).</p>
</blockquote>
<p>I'd recommend building u-boot and the kernel separate from buildroot. Ensure they are working then go back to trying to build them within buildroot.</p>
Software Development: RE: linux-v4.19 kernel
http://support.criticallink.com/redmine/boards/10/topics/6503?r=6504#message-6504
2023-10-03T17:00:01Z
Jonathan Cormier
jcormier@criticallink.com
<p>Thomas Catalino wrote:</p>
<blockquote>
<p>(posted on behalf of a customer)</p>
<p>I currently have a project with to revisit a system based on the MityDSP-L138 platform, mainly to update the system's self-test and calibration procedures.</p>
<p>I've started blowing the dust off our build environment, but are coming up against quite a few issues due to the age of it. For example, the version of buildroot we are using points to stale versions of most of the libraries it needs.</p>
<p>I've seen that there are still commits going into your linux-davinci repository and even an updated linux-v4.19 kernel. I've given this a very quick try with a modern buildroot, but not getting very far (no kernel output).</p>
</blockquote>
<p>What kernel are you moving from? Do you use dsplink/dspbios? The 3.2 kernel is the latest kernel which supports the older dsplink which is why I ask.<br />Any of the kernels should boot however.</p>
<blockquote>
<p>Could I ask what environment (e.g. gcc, u-boot, kernel and buildroot) you'd currently recommend I start from?</p>
</blockquote>
<p>For 3.2 and DSPlink, the 2012 toolchain should be used.</p>
<p>The build VM we provide should have the older toolchains needed to build the 3.2 kernel. <a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Linux_Build_VM">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Linux_Build_VM</a><br />or they can be downloaded from <a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/GCC_Toolchain">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/GCC_Toolchain</a></p>
<p>For the newer kernels, I believe you want to use the gcc included in the 2017 MDK.</p>
<p><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Linux_Kernel#For-MDK-from-or-newer-than-August-2017-Yocto-based">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Linux_Kernel#For-MDK-from-or-newer-than-August-2017-Yocto-based</a></p>
<p>Similarly for u-boot checkout the <a href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Das_U-Boot_Port" class="external">U-boot wiki page</a></p>
<p>I do not have a lot of experience with buildroot. We mostly use Yocto.</p>
Software Development: linux-v4.19 kernel
http://support.criticallink.com/redmine/boards/10/topics/6503
2023-10-03T15:40:06Z
Thomas Catalino
tom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>I currently have a project with to revisit a system based on the MityDSP-L138 platform, mainly to update the system's self-test and calibration procedures.</p>
<p>I've started blowing the dust off our build environment, but are coming up against quite a few issues due to the age of it. For example, the version of buildroot we are using points to stale versions of most of the libraries it needs.</p>
<p>I've seen that there are still commits going into your linux-davinci repository and even an updated linux-v4.19 kernel. I've given this a very quick try with a modern buildroot, but not getting very far (no kernel output).</p>
<p>Could I ask what environment (e.g. gcc, u-boot, kernel and buildroot) you'd currently recommend I start from?</p>
Software Development: RE: MityDSP-L138F I2C bus hang (SDA held low)
http://support.criticallink.com/redmine/boards/10/topics/6472?r=6476#message-6476
2023-09-08T18:40:06Z
Jonathan Cormier
jcormier@criticallink.com
<p>Saw the other post first so responded there. <a class="external" href="https://support.criticallink.com/redmine/boards/11/topics/6473?r=6475">https://support.criticallink.com/redmine/boards/11/topics/6473?r=6475</a></p>
Software Development: MityDSP-L138F I2C bus hang (SDA held low)
http://support.criticallink.com/redmine/boards/10/topics/6472
2023-09-08T17:38:09Z
Jon Cox
<p>Hello,</p>
<p>We are developing on the MityDSP-L138F platform and have noticed an intermittent issue with the I2C bus hanging due to SDA being held LOW. We are uncertain whether it is a slave or the OMAP I2C Module pulling SDA low.</p>
<p>We are using I2C0 (soon to switch everything to I2C1). The issue can be faithfully reproduced if we lower the pull-up resistors below ~1.2kOhm or above a large value (timing, VIH VIL issues). However, it does seem to still occur at random. Shorting SDA to HIGH (5V) resolves the issue and the bus continues operation.</p>
<p>Our question: is there a way to either soft reset the I2C Module via the ICMDR IRS bit == 0, or to manually send 9 CLK pulses on SCLK? We have perused the board support package but cannot see a clear way to directly command the I2C SCLK pin. Is there a simple way to MUX the pin to GPIO and toggle it 9 times? We have also found the ICMDR and ICIVR byte addresses (0x01C2 2024, 0x01C2 2028) but we're unsure how to directly read/write to these.</p>
<p>Thanks for the support, and let us know if we can provide any additional info regarding this issue.</p>
<p>Best,</p>
<p>Jon Cox<br />Genus IntelliGen</p>
Software Development: Modification of flashing program - sfh_OMAP-L138.exe
http://support.criticallink.com/redmine/boards/10/topics/6384
2023-06-06T13:01:18Z
Thomas Catalino
tom.catalino@criticallink.com
<p>(Posted by Tom on behalf of customer -- I am working to resolve the locked account issue)</p>
<p>in my work I use your L138-FX-325-RC chips, to which I added self-built base boards with peripherals.<br />Recently, I built a prototype of a measuring device that uses both processors at the same time: DSP for numerical calculations, ARM9 for peripherals and communication.<br />The whole system is managed by ARM9 (working without OS). I am using a 456MHz clock in my project. Using CCS of TI I obtained two files: dsp.out and arm9.out which I combined into one file Analyzer_1.bin using AISgen_d800k008.exe with accordingly changed the configuration file MITY_UART1_OMAPL138_LCDK_AISGen_Config.cfg (attached). I boot the device by uploading the Analyzer_1.bin program to RAM using the UartHost.exe program and UATR1 of the board, equipped with the FT232R chip (converting USB to serial UART interface). Everything works OK - the program starts on both processors right after booting (ARM9 starts DSP).<br />The next step was an attempt to upload the program to Flash NAND memory. For this purpose, using AISgen_d800k008.exe with the configuration file MITY_NAND_OMAPL138_LCDK_AISGen_Config.cfg (attached),<br />I created the file Analyzer_1_NAND.bin which I wanted to upload to the NAND memory. For this purpose, I used the sfh_OMAP-L138.exe program downloaded from the TI website.<br />First, to clear the NAND memory, I used the following command:</p>
<p>sfh_OMAP-L138.exe -flashType NAND -targetType OMAPL138 -erase -p COM4 -v</p>
<p>(also in simplified versions, e.g.: sfh_OMAP-L138.exe -flashType NAND -erase -p COM4)</p>
<p>After resetting the device, the program first successfully connects to the device and then stops after issuing the command:</p>
<p>Waiting for SFI on the OMAP-L138...</p>
<p>There are no progress bars showing memory erasing - the program is waiting!!! Why?</p>
<p>I get a similar effect when trying to upload the Analyzer_1_NAND.bin program to the NAND memory using the command:</p>
<p>sfh_OMAP-L138.exe -flash_noubl -flashType NAND -p COM4 Analyzer_1_NAND.bin</p>
<p>I use the -flash_noubl parameter because I don't need to upload the UBL file because my arm9.out program runs the dsp.out program.</p>
<p>On page</p>
<p><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Reprogramming_a_Dead_Board">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Reprogramming_a_Dead_Board</a></p>
<p>I found information that I should use the rebuilt sfh_OMAP-L138.exe program. For this purpose, I should download the package from the website</p>
<pre><code>"Dead Board Programming Files"</code></pre>
<p>But I can't do it because I can't log in because the old account has expired and I don't see the option to create a new account anywhere on the website?!?!</p>
<p>In turn on the page</p>
<p><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/User_Boot_Loader">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/User_Boot_Loader</a></p>
<p>I found information</p>
<p>"The user boot loader requires a couple of small modifications to support the Critical Link SoM, including:</p>
<pre><code>Setting the EMIFA clock rate to 100 MHz instead of 25 MHz for FPGA operation.<br /> Providing a 312 MHz CPU clock rate (optional) for Profibus support on the Industrial I/O Board.</code></pre>
<p>A tarball of the source code including the modifications made by Critical Link is included in the releases, below."</p>
<p>(due to not being logged in, I can't download the UBLandFLashUtils_2010_10_26.tgz software package either).</p>
<p>In my project, the speed of the DSP processor (TMS320C6748) is important, hence the clock frequency is 456 MHz and at the same time I do not use Profibus because I do not use the Industrial I/O Board!!<br />The L138-FX-325-RC system does not have an FPGA, so I do not have to change the DSP clock frequency.<br />On the other hand, in my system, the EMIFA port works at 38 MHz. For this frequency, I selected the time constants of the ADC converter that reads the parallel port.</p>
<p>Will I have to change it all??!!<br />Currently, when I boot the device via UART1, uploading the Analyzer_1.bin program to RAM with<br />UartHost.exe program, everything works OK!!!</p>
<p>Please help me, preferably by providing me with a properly reprogrammed sfh_OMAP-L138.exe program, which will allow me to upload the program to the Flash NAND memory in the current version. This version of the program best suits my needs. The second option is to allow me to re-create my account at <a class="external" href="https://support.criticallink.com">https://support.criticallink.com</a><br />I prefer the first variant!</p>
Software Development: RE: Changes on MityDSP-L138 L138-DM-336-RI-J
http://support.criticallink.com/redmine/boards/10/topics/6316?r=6321#message-6321
2023-04-28T10:11:54Z
Michael Williamson
<p>Hi Kim,</p>
<p>I am relieved you got your system loaded.</p>
<p>Have a nice weekend.</p>
<p>With regards,<br />Mike</p>
Software Development: RE: Changes on MityDSP-L138 L138-DM-336-RI-J
http://support.criticallink.com/redmine/boards/10/topics/6316?r=6320#message-6320
2023-04-28T08:57:06Z
Kim Nielsen
<p>Hi again,</p>
<p>We managed to fix our loading problem.<br />The bug was due to our FPGA binary, not the loader itself.</p>
<p>Regards,<br />Kim</p>
Software Development: RE: Changes on MityDSP-L138 L138-DM-336-RI-J
http://support.criticallink.com/redmine/boards/10/topics/6316?r=6319#message-6319
2023-04-28T07:28:57Z
Kim Nielsen
<p>Hi Mike,</p>
<p>I tried to build the fpga_ctrl.ko module, but nothing seems to happen when I try to program the FPGA.</p>
<p><strong>Loading the FPGA with fpga_ctrl.ko</strong><br />These are the commands I use:<br />$ insmod fpga_ctrl.ko<br />$ echo "1" > /sys/devices/fpga_ctrl/cmd<br />$ cat /sys/devices/fpga_ctrl/state --> 1 : RESET<br />$ echo "2" > /sys/devices/fpga_ctrl/cmd --> 2 : PROGRAMMING<br />$ cat fpga_som.bin > /sys/devices/fpga_ctrl/image<br />$ echo "3" > /sys/devices/fpga_ctrl/cmd --> 3 : PROGRAM_FAIL</p>
<p>I also noticed only one message from the fpga_ctrl module in dmesg right after "insmod fpga_ctrl.ko":<br />fpga fpga_ctrl: loading the fpga_ctrl module.</p>
<p><strong>Debugging fpga_ctrl.ko</strong><br />The fpga_ctrl.ko I build is from the "Jan-2014" MDK release ( <a href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Board_Support_Package#Releases" class="external">Release site I used</a> )</p>
<p>This is how I build the FPGA kernel modules:</p>
<pre><code class="shell syntaxhl">make <span class="nt">-C</span> ~/work/toolchains/linux-powercon-1.0.3/src/linux/ <span class="nv">M</span><span class="o">=</span><span class="sb">`</span><span class="nb">pwd</span><span class="sb">`</span> <span class="nv">ARCH</span><span class="o">=</span>arm <span class="nv">CROSS_COMPILE</span><span class="o">=</span>arm-926ejs-linux-gnueabi- modules
</code></pre>
<p>I get this output from building:<br /> CC [M] /home/anton/work/toolchains/fpga/fpga_ctrl.o<br /> CC [M] /home/anton/work/toolchains/fpga/ads7843.o<br /> CC [M] /home/anton/work/toolchains/fpga/fpga_i2c.o<br /> CC [M] /home/anton/work/toolchains/fpga/fpga_gpio.o<br /> CC [M] /home/anton/work/toolchains/fpga/fpga_spi.o<br /> CC [M] /home/anton/work/toolchains/fpga/fpga_uart.o<br /> CC [M] /home/anton/work/toolchains/fpga/fpga_lcdctlr.o<br /> CC [M] /home/anton/work/toolchains/fpga/fpga_dcmctlr.o<br /> CC [M] /home/anton/work/toolchains/fpga/fpga_hdlc.o<br /> CC [M] /home/anton/work/toolchains/fpga/fpga_pwm.o<br /> Building modules, stage 2.<br /> MODPOST 10 modules<br />WARNING: "set_irq_flags" [/home/anton/work/toolchains/fpga/fpga_gpio.ko] undefined!<br />WARNING: "irq_set_chip_and_handler_name" [/home/anton/work/toolchains/fpga/fpga_gpio.ko] undefined!<br />WARNING: "irq_desc" [/home/anton/work/toolchains/fpga/fpga_gpio.ko] undefined!<br /> CC /home/anton/work/toolchains/fpga/ads7843.mod.o<br /> LD [M] /home/anton/work/toolchains/fpga/ads7843.ko <br /> CC /home/anton/work/toolchains/fpga/fpga_ctrl.mod.o<br /> LD [M] /home/anton/work/toolchains/fpga/fpga_ctrl.ko<br /> CC /home/anton/work/toolchains/fpga/fpga_dcmctlr.mod.o<br /> LD [M] /home/anton/work/toolchains/fpga/fpga_dcmctlr.ko<br /> CC /home/anton/work/toolchains/fpga/fpga_gpio.mod.o<br /> LD [M] /home/anton/work/toolchains/fpga/fpga_gpio.ko<br /> CC /home/anton/work/toolchains/fpga/fpga_hdlc.mod.o<br /> LD [M] /home/anton/work/toolchains/fpga/fpga_hdlc.ko<br /> CC /home/anton/work/toolchains/fpga/fpga_i2c.mod.o<br /> LD [M] /home/anton/work/toolchains/fpga/fpga_i2c.ko<br /> CC /home/anton/work/toolchains/fpga/fpga_lcdctlr.mod.o<br /> LD [M] /home/anton/work/toolchains/fpga/fpga_lcdctlr.ko<br /> CC /home/anton/work/toolchains/fpga/fpga_pwm.mod.o<br /> LD [M] /home/anton/work/toolchains/fpga/fpga_pwm.ko<br /> CC /home/anton/work/toolchains/fpga/fpga_spi.mod.o<br /> LD [M] /home/anton/work/toolchains/fpga/fpga_spi.ko <br /> CC /home/anton/work/toolchains/fpga/fpga_uart.mod.o<br /> LD [M] /home/anton/work/toolchains/fpga/fpga_uart.ko<br />make: Leaving directory '/home/anton/work/toolchains/nor-flash-oe-lite/tmp/work/machine/arm-926ejs-linux-gnueabi/linux-powercon-1.0.3/src/linux'</p>
<p>Should I worry about the warnings for "fpga_gpio.ko" ?<br />If I only want to load the FPGA, do I need to use other modules apart from "fpga_ctrl.ko" ?</p>
<p>Regards,<br />Kim</p>
Software Development: RE: Changes on MityDSP-L138 L138-DM-336-RI-J
http://support.criticallink.com/redmine/boards/10/topics/6316?r=6318#message-6318
2023-04-26T12:52:10Z
Kim Nielsen
<p>Hi Mike,</p>
<p>Thank you very much for the fast response.</p>
<p>We are loading the FPGA from Linux, but not with the "fpga_ctrl.ko" kernel module mentioned in the "Programming the FPGA" wiki.<br />Unfortunately, that kernel module is not part of our 3.2.0 Linux.</p>
<p>We are loading the FPGA from a Linux application, which involves gpio configuration --> We use the "EMA_A_RW" pin to allow writing with EMIFA.<br />Just for curiosity, I have attached the cpp code.</p>
<p>Does "fpga_ctrl.ko" use the EMIFA to load the FPGA?</p>
<p>Regards,<br />Kim</p>
Software Development: RE: Changes on MityDSP-L138 L138-DM-336-RI-J
http://support.criticallink.com/redmine/boards/10/topics/6316?r=6317#message-6317
2023-04-26T10:13:07Z
Michael Williamson
<p>Have you reviewed the migration information (including the PCN) from this page?</p>
<p><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Migrating_to_the_MityDSP-L138F-A7">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Migrating_to_the_MityDSP-L138F-A7</a></p>
<p>uBoot was updated in 2022 primarily to support new factory configuration codes to indicate an Artix7 variant is present. That firmware should be installed in EEPROM on the module received unless you have overwritten it. Linux should not require modification. However, for loading the FPGA in uBoot you will need to pass the (optional) FPGA bitstream size argument to the loadfpga command as the default size is not large enough (the A7 bitstream is larger).</p>
<p>See this page for information for the Artix 7 sizes and commands to load the bitstream.</p>
<p><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA</a></p>
<p>Also, are you using the options for bitstream generation as the example project?</p>
<p>If these points do not help, please provide a dump of your load command and the error message, etc.</p>
<p>With regards,<br />Mike</p>
Software Development: Changes on MityDSP-L138 L138-DM-336-RI-J
http://support.criticallink.com/redmine/boards/10/topics/6316
2023-04-26T06:55:15Z
Kim Nielsen
<p>Hi,</p>
I have received a new MityDSP-L138 SoM board:
<ul>
<li>Model no: L138-DM-336-RI-J</li>
<li>Serial no: 22023557</li>
<li>Part no: 80-001541RI-2A</li>
</ul>
<p>The new SoM includes an Artix 7 FPGA and I am curious to know if there are any software changes (U-Boot, Linux etc.) in this regard?</p>
<p>I am asking, since we are experiencing some issues when loading a binary into the FPGA.<br />We didn't experience any issues with the old SPARTAN-6 FPGA and have not changed the way we load the FPGA.</p>
<p>Regards,<br />Kim</p>
Software Development: RE: Cannot establish an ethernet connection
http://support.criticallink.com/redmine/boards/10/topics/6256?r=6311#message-6311
2023-04-10T14:16:45Z
Jonathan Cormier
jcormier@criticallink.com
<p>Great, note that at least for this boot. The ethernet phy came up as address 3 so it would have worked with the original kernel as well.</p>
<pre>
PHY: 0:03 - Link is Up - 100/Full
</pre>
Software Development: RE: Cannot establish an ethernet connection
http://support.criticallink.com/redmine/boards/10/topics/6256?r=6310#message-6310
2023-04-10T14:05:23Z
Vadym Kolesnyk
<p>With new image:</p>
<pre><code class="shell syntaxhl">OMAP-L138/AM-1808/AM-1810 initialization passed!
Configuring 256MB mDDR
Booting TI User Boot Loader
UBL Version: 1.65:2.28.1 BuiltJul 11 2011 12:49:53
UBL Flashtype: SPI
Starting SPI Memory Copy...
Valid magicnum, 0x55424CBB, found at offset 0x00010000.
DONE
Jumping to entry point at 0xC1080000.
U-Boot 2009.11-00004-gabfcd79 <span class="o">(</span>Jan 03 2018 - 11:30:43<span class="o">)</span>
I2C: ready
DRAM: 256 MB
NAND: 512 MiB
MMC: davinci: 0
In: serial
Out: serial
Err: serial
ARM Clock : 300000000 Hz
DDR Clock : 150000000 Hz
EMIFA CLock : 100000000 Hz
DSP Clock : 300000000 Hz
ASYNC3 Clock : 150000000 Hz
Enet config : 2
MMC 0 Enable : 1
Resetting ethernet phy
Net: Ethernet PHY: GENERIC @ 0x03 <span class="o">[</span>0x8]
Hit any key to stop autoboot: 0
Device: davinci
Manufacturer ID: 27
OEM: 5048
Name: SD16G
Tran Speed: 25000000
Rd Block Len: 512
SD version 2.0
High Capacity: Yes
Capacity: 15502147584
Bus Width: 4-bit
Loading file <span class="s2">"/boot/uImage"</span> from mmc device 0:1 <span class="o">(</span>xxa1<span class="o">)</span>
2540784 bytes <span class="nb">read</span>
<span class="c">## Booting kernel from Legacy Image at c0700000 ...</span>
Image Name: Linux-3.2.0+
Image Type: ARM Linux Kernel Image <span class="o">(</span>uncompressed<span class="o">)</span>
Data Size: 2540720 Bytes <span class="o">=</span> 2.4 MB
Load Address: c0008000
Entry Point: c0008000
Verifying Checksum ... OK
Loading Kernel Image ... OK
OK
Starting kernel ...
Uncompressing Linux... <span class="k">done</span>, booting the kernel.
Linux version 3.2.0+ <span class="o">(</span>jcormier@jcormier-MS-7A93<span class="o">)</span> <span class="o">(</span>gcc version 4.8.3 20140401 <span class="o">(</span>prerelease<span class="o">)</span> <span class="o">(</span>Linaro GCC 4.8-2014.04<span class="o">)</span> <span class="o">)</span> <span class="c">#2 PREEMPT Fri Apr 7 17:44:46 EDT 2023</span>
CPU: ARM926EJ-S <span class="o">[</span>41069265] revision 5 <span class="o">(</span>ARMv5TEJ<span class="o">)</span>, <span class="nv">cr</span><span class="o">=</span>00053177
CPU: VIVT data cache, VIVT instruction cache
Machine: MityDSP-L138/MityARM-1808
Ignoring unrecognised tag 0x42000101
Memory policy: ECC disabled, Data cache writethrough
DaVinci da850/omap-l138/am18x variant 0x1
Built 1 zonelists <span class="k">in </span>Zone order, mobility grouping on. Total pages: 24384
Kernel <span class="nb">command </span>line: <span class="nv">mem</span><span class="o">=</span>96M <span class="nv">console</span><span class="o">=</span>ttyS1,115200n8 <span class="nv">mtdparts</span><span class="o">=</span>nand:128M<span class="o">(</span>rootfs<span class="o">)</span>,-<span class="o">(</span>userfs<span class="o">)</span> <span class="nv">root</span><span class="o">=</span>/dev/mmcblk0p1 rw rootwait <span class="nv">ip</span><span class="o">=</span>none
PID <span class="nb">hash </span>table entries: 512 <span class="o">(</span>order: <span class="nt">-1</span>, 2048 bytes<span class="o">)</span>
Dentry cache <span class="nb">hash </span>table entries: 16384 <span class="o">(</span>order: 4, 65536 bytes<span class="o">)</span>
Inode-cache <span class="nb">hash </span>table entries: 8192 <span class="o">(</span>order: 3, 32768 bytes<span class="o">)</span>
Memory: 96MB <span class="o">=</span> 96MB total
Memory: 91368k/91368k available, 6936k reserved, 0K highmem
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 <span class="o">(</span> 4 kB<span class="o">)</span>
fixmap : 0xfff00000 - 0xfffe0000 <span class="o">(</span> 896 kB<span class="o">)</span>
vmalloc : 0xc6800000 - 0xfea00000 <span class="o">(</span> 898 MB<span class="o">)</span>
lowmem : 0xc0000000 - 0xc6000000 <span class="o">(</span> 96 MB<span class="o">)</span>
modules : 0xbf000000 - 0xc0000000 <span class="o">(</span> 16 MB<span class="o">)</span>
.text : 0xc0008000 - 0xc0527f94 <span class="o">(</span>5248 kB<span class="o">)</span>
.init : 0xc0528000 - 0xc0550000 <span class="o">(</span> 160 kB<span class="o">)</span>
.data : 0xc0550000 - 0xc05b57e0 <span class="o">(</span> 406 kB<span class="o">)</span>
.bss : 0xc05b5804 - 0xc05e2e50 <span class="o">(</span> 182 kB<span class="o">)</span>
NR_IRQS:445
Console: colour dummy device 80x30
Calibrating delay loop... 148.88 BogoMIPS <span class="o">(</span><span class="nv">lpj</span><span class="o">=</span>744448<span class="o">)</span>
pid_max: default: 32768 minimum: 301
Mount-cache <span class="nb">hash </span>table entries: 512
CPU: Testing write buffer coherency: ok
devtmpfs: initialized
DaVinci: 144 gpio irqs
print_constraints: dummy:
NET: Registered protocol family 16
baseboard_pre_init: Entered
mityomapl138_setup_nand: using 8 bit data
baseboard_init <span class="o">[</span>IndustrialIO]...
bio: create slab <bio-0> at 0
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
print_constraints: VDCDC1: 1150 <<span class="nt">--</span><span class="o">></span> 1350 mV at 1200 mV
print_constraints: VDCDC2: 1800 mV
print_constraints: VDCDC3: 1200 mV
print_constraints: LDO1: 1800 mV
print_constraints: LDO2: 2500 <<span class="nt">--</span><span class="o">></span> 3300 mV at 3300 mV
Advanced Linux Sound Architecture Driver Version 1.0.24.
Switching to clocksource timer0_1
musb-hdrc: version 6.0, ?dma?, otg <span class="o">(</span>peripheral+host<span class="o">)</span>
Waiting <span class="k">for </span>USB PHY clock good...
musb-hdrc musb-hdrc: USB OTG mode controller at fee00000 using PIO, IRQ 58
NET: Registered protocol family 2
IP route cache <span class="nb">hash </span>table entries: 1024 <span class="o">(</span>order: 0, 4096 bytes<span class="o">)</span>
TCP established <span class="nb">hash </span>table entries: 4096 <span class="o">(</span>order: 3, 32768 bytes<span class="o">)</span>
TCP <span class="nb">bind hash </span>table entries: 4096 <span class="o">(</span>order: 2, 16384 bytes<span class="o">)</span>
TCP: Hash tables configured <span class="o">(</span>established 4096 <span class="nb">bind </span>4096<span class="o">)</span>
TCP reno registered
UDP <span class="nb">hash </span>table entries: 256 <span class="o">(</span>order: 0, 4096 bytes<span class="o">)</span>
UDP-Lite <span class="nb">hash </span>table entries: 256 <span class="o">(</span>order: 0, 4096 bytes<span class="o">)</span>
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
JFFS2 version 2.2. <span class="o">(</span>NAND<span class="o">)</span> © 2001-2006 Red Hat, Inc.
msgmni has been <span class="nb">set </span>to 178
io scheduler noop registered <span class="o">(</span>default<span class="o">)</span>
start plist <span class="nb">test
</span>end plist <span class="nb">test
</span>Serial: 8250/16550 driver, 3 ports, IRQ sharing disabled
serial8250.0: ttyS0 at MMIO 0x1c42000 <span class="o">(</span>irq <span class="o">=</span> 25<span class="o">)</span> is a 16550A
serial8250.0: ttyS1 at MMIO 0x1d0c000 <span class="o">(</span>irq <span class="o">=</span> 53<span class="o">)</span> is a 16550A
console <span class="o">[</span>ttyS1] enabled
serial8250.0: ttyS2 at MMIO 0x1d0d000 <span class="o">(</span>irq <span class="o">=</span> 61<span class="o">)</span> is a 16550A
brd: module loaded
at24 1-0050: 256 byte 24c02 EEPROM, read-only, 0 bytes/write
MityOMAPL138: Found MAC <span class="o">=</span> 70:b3:d5:af:99:93
MityOMAPL138: Part Number <span class="o">=</span> L138-FI-236-RL
ahci ahci: forcing PORTS_IMPL to 0x1
ahci ahci: AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl platform mode
ahci ahci: flags: ncq sntf pm led clo only pmp pio slum part ccc
scsi0 : ahci_platform
ata1: SATA max UDMA/133 mmio <span class="o">[</span>mem 0x01e18000-0x01e19fff] port 0x100 irq 67
ONFI flash detected
ONFI param page 0 valid
NAND device: Manufacturer ID: 0x2c, Chip ID: 0xdc <span class="o">(</span>Micron MT29F4G08ABADAWP<span class="o">)</span>
Bad block table found at page 262080, version 0x01
Bad block table found at page 262016, version 0x01
Creating 2 MTD partitions on <span class="s2">"davinci_nand.1"</span>:
0x000000000000-0x000008000000 : <span class="s2">"rootfs"</span>
0x000008000000-0x000020000000 : <span class="s2">"homefs"</span>
davinci_nand davinci_nand.1: controller rev. 2.5
spi_davinci spi_davinci.1: DMA: supported
spi_davinci spi_davinci.1: DMA: RX channel: 18, TX channel: 19, event queue: 0
m25p80 spi1.0: found m25p64, expected m25p80
m25p80 spi1.0: m25p64 <span class="o">(</span>8192 Kbytes<span class="o">)</span>
Creating 8 MTD partitions on <span class="s2">"m25p80"</span>:
0x000000000000-0x000000010000 : <span class="s2">"ubl"</span>
0x000000010000-0x000000090000 : <span class="s2">"u-boot"</span>
0x000000090000-0x0000000a0000 : <span class="s2">"u-boot-env"</span>
0x0000000a0000-0x0000000b0000 : <span class="s2">"periph-config"</span>
No LCD configured
MII PHY configured
0x0000000b0000-0x000000100000 : <span class="s2">"reserved"</span>
0x000000100000-0x000000400000 : <span class="s2">"kernel"</span>
0x000000400000-0x000000600000 : <span class="s2">"fpga"</span>
0x000000600000-0x000000800000 : <span class="s2">"spare"</span>
spi_davinci spi_davinci.1: Controller at 0xfef0e000
CAN device driver interface
mcp251x spi1.1: probed
davinci_mdio davinci_mdio.0: davinci mdio revision 1.5
davinci_mdio davinci_mdio.0: detected phy mask fffffff7
davinci_mdio.0: probed
davinci_mdio davinci_mdio.0: phy[3]: device 0:03, driver unknown
ohci_hcd: USB 1.1 <span class="s1">'Open'</span> Host Controller <span class="o">(</span>OHCI<span class="o">)</span> Driver
ohci ohci.0: DA8xx OHCI
ohci ohci.0: new USB bus registered, assigned bus number 1
Waiting <span class="k">for </span>USB PHY clock good...
ohci ohci.0: irq 59, io mem 0x01e25000
ata1: SATA <span class="nb">link </span>down <span class="o">(</span>SStatus 0 SControl 300<span class="o">)</span>
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
Initializing USB Mass Storage driver...
usbcore: registered new interface driver usb-storage
USB Mass Storage support registered.
mousedev: PS/2 mouse device common <span class="k">for </span>all mice
omap_rtc omap_rtc: rtc core: registered omap_rtc as rtc0
omap_rtc: RTC power up reset detected
i2c /dev entries driver
cpuidle: using governor ladder
cpuidle: using governor menu
davinci_mmc davinci_mmc.0: Using DMA, 4-bit mode
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
mmc0: new high speed SDHC card at address 0007
mmcblk0: mmc0:0007 SD16G 14.4 GiB
mmcblk0: p1
dsd1791 spi1.2: Failed to add route LLOUT->Line Out
asoc: dsd1791 <-> davinci-mcasp.0 mapping ok
ALSA device list:
<span class="c">#0: MityDSP-L138 INDIO</span>
TCP cubic registered
NET: Registered protocol family 17
can: controller area network core <span class="o">(</span>rev 20090105 abi 8<span class="o">)</span>
NET: Registered protocol family 29
can: raw protocol <span class="o">(</span>rev 20090105<span class="o">)</span>
regulator_init_complete: LDO2: incomplete constraints, leaving on
regulator_init_complete: LDO1: incomplete constraints, leaving on
regulator_init_complete: VDCDC3: incomplete constraints, leaving on
regulator_init_complete: VDCDC2: incomplete constraints, leaving on
regulator_init_complete: VDCDC1: incomplete constraints, leaving on
console <span class="o">[</span>netcon0] enabled
netconsole: network logging started
omap_rtc omap_rtc: setting system clock to 2000-01-01 00:00:00 UTC <span class="o">(</span>946684800<span class="o">)</span>
kjournald starting. Commit interval 5 seconds
EXT3-fs <span class="o">(</span>mmcblk0p1<span class="o">)</span>: using internal journal
EXT3-fs <span class="o">(</span>mmcblk0p1<span class="o">)</span>: 1 orphan inode deleted
EXT3-fs <span class="o">(</span>mmcblk0p1<span class="o">)</span>: recovery <span class="nb">complete
</span>EXT3-fs <span class="o">(</span>mmcblk0p1<span class="o">)</span>: mounted filesystem with writeback data mode
VFS: Mounted root <span class="o">(</span>ext3 filesystem<span class="o">)</span> on device 179:1.
devtmpfs: mounted
Freeing init memory: 160K
Failed to mount /sys/kernel/security: No such file or directory
Welcome to The Ångström Distribution!
Starting LSB: The RPC portmapper...
Starting udev Coldplug all Devices...
Starting Remount API VFS...
Starting Temporary Directory...
Starting Debug File System...
Starting Load Kernel Modules...
Starting Apply Kernel Variables...
Starting POSIX Message Queue File System...
Started Set Up Additional Binary Formats <span class="o">[</span> OK <span class="o">]</span>
Started Huge Pages File System <span class="o">[</span> OK <span class="o">]</span>
Starting Journal Service...
Started Journal Service <span class="o">[</span> OK <span class="o">]</span>
Starting udev Kernel Device Manager...
Starting File System Check on Root Device...
Started LSB: The RPC portmapper <span class="o">[</span> OK <span class="o">]</span>
udevd[633]: starting version 182
Started udev Kernel Device Manager <span class="o">[</span> OK <span class="o">]</span>
Started Remount API VFS <span class="o">[</span> OK <span class="o">]</span>
Started Temporary Directory <span class="o">[</span> OK <span class="o">]</span>
Started Debug File System <span class="o">[</span> OK <span class="o">]</span>
Failed to start Load Kernel Modules <span class="o">[</span>FAILED]
See <span class="s1">'systemctl status systemd-modules-load.service'</span> <span class="k">for </span>details.
Started Apply Kernel Variables <span class="o">[</span> OK <span class="o">]</span>
Started POSIX Message Queue File System <span class="o">[</span> OK <span class="o">]</span>
Started File System Check on Root Device <span class="o">[</span> OK <span class="o">]</span>
Starting Remount Root FS...
Started Configuration File System <span class="o">[</span> OK <span class="o">]</span>
Started FUSE Control File System <span class="o">[</span> OK <span class="o">]</span>
Started Remount Root FS <span class="o">[</span> OK <span class="o">]</span>
Started Machine ID first boot configure <span class="o">[</span> OK <span class="o">]</span>
Starting Load Random Seed...
Starting Recreate Volatile Files and Directories...
Started Run pending postinsts <span class="o">[</span> OK <span class="o">]</span>
Started Load Random Seed <span class="o">[</span> OK <span class="o">]</span>
Started Recreate Volatile Files and Directories <span class="o">[</span> OK <span class="o">]</span>
Starting Restore Sound Card State...
Starting Timestamping service...
Started Timestamping service <span class="o">[</span> OK <span class="o">]</span>
Started SSH Key Generation <span class="o">[</span> OK <span class="o">]</span>
Starting Permit User Sessions...
portmap[599]: Starting portmap daemon...
Started Permit User Sessions <span class="o">[</span> OK <span class="o">]</span>
Started Restore Sound Card State <span class="o">[</span> OK <span class="o">]</span>
Starting Serial Getty on ttyS1...
Started Serial Getty on ttyS1 <span class="o">[</span> OK <span class="o">]</span>
Started udev Coldplug all Devices <span class="o">[</span> OK <span class="o">]</span>
.---O---.
| | .-. o o
| | |-----.-----.-----.| | .----..-----.-----.
| | | __ | <span class="nt">---</span><span class="s1">'| '</span><span class="nt">--</span>.| .-<span class="s1">'| | |
| | | | | |--- || --'</span>| | | <span class="s1">' | | | |
'</span><span class="nt">---</span><span class="s1">'---'</span><span class="nt">--</span><span class="s1">'--'</span><span class="nt">--</span><span class="nb">.</span> |-----<span class="s1">''</span><span class="nt">----</span><span class="s1">''</span><span class="nt">--</span><span class="s1">' '</span><span class="nt">-----</span><span class="s1">'-'</span>-<span class="s1">'-'</span>
-<span class="s1">' |
'</span><span class="nt">---</span><span class="s1">'
The Angstrom Distribution mityomapl138 ttyS1
Angstrom v2012.05 - Kernel 3.2.0+
mityomapl138 login: Starting Networking...
davinci_mdio davinci_mdio.0: resetting idled controller
net eth0: attached PHY driver [Generic PHY] (mii_bus:phy_addr=0:03, id=40005201)
PHY: 0:03 - Link is Up - 100/Full
Started Networking [ OK ]
Starting DropBear SSH Server...
Started DropBear SSH Server [ OK ]
Starting Getty on tty1...
Started Getty on tty1 [ OK ]
.---O---.
| | .-. o o
| | |-----.-----.-----.| | .----..-----.-----.
| | | __ | ---'</span>| <span class="s1">'--.| .-'</span>| | |
| | | | | |--- <span class="o">||</span> <span class="nt">--</span><span class="s1">'| | | '</span> | | | |
<span class="s1">'---'</span><span class="nt">---</span><span class="s1">'--'</span><span class="nt">--</span><span class="s1">'--. |-----''----''--'</span> <span class="s1">'-----'</span>-<span class="s1">'-'</span>-<span class="s1">'
-'</span> |
<span class="s1">'---'</span>
The Angstrom Distribution mityomapl138 ttyS1
Angstrom v2012.05 - Kernel 3.2.0+
mityomapl138 login: root
Last login: Sat Jan 1 00:00:28 UTC 2000 on ttyS1
root@mityomapl138:~# ping 8.8.8.8
PING 8.8.8.8 <span class="o">(</span>8.8.8.8<span class="o">)</span>: 56 data bytes
64 bytes from 8.8.8.8: <span class="nb">seq</span><span class="o">=</span>0 <span class="nv">ttl</span><span class="o">=</span>119 <span class="nb">time</span><span class="o">=</span>24.743 ms
64 bytes from 8.8.8.8: <span class="nb">seq</span><span class="o">=</span>1 <span class="nv">ttl</span><span class="o">=</span>119 <span class="nb">time</span><span class="o">=</span>24.131 ms
64 bytes from 8.8.8.8: <span class="nb">seq</span><span class="o">=</span>2 <span class="nv">ttl</span><span class="o">=</span>119 <span class="nb">time</span><span class="o">=</span>24.158 ms
64 bytes from 8.8.8.8: <span class="nb">seq</span><span class="o">=</span>3 <span class="nv">ttl</span><span class="o">=</span>119 <span class="nb">time</span><span class="o">=</span>24.154 ms
64 bytes from 8.8.8.8: <span class="nb">seq</span><span class="o">=</span>4 <span class="nv">ttl</span><span class="o">=</span>119 <span class="nb">time</span><span class="o">=</span>24.247 ms
64 bytes from 8.8.8.8: <span class="nb">seq</span><span class="o">=</span>5 <span class="nv">ttl</span><span class="o">=</span>119 <span class="nb">time</span><span class="o">=</span>24.176 ms
64 bytes from 8.8.8.8: <span class="nb">seq</span><span class="o">=</span>6 <span class="nv">ttl</span><span class="o">=</span>119 <span class="nb">time</span><span class="o">=</span>24.221 ms
^C
<span class="nt">---</span> 8.8.8.8 ping statistics <span class="nt">---</span>
7 packets transmitted, 7 packets received, 0% packet loss
round-trip min/avg/max <span class="o">=</span> 24.131/24.261/24.743 ms
root@mityomapl138:~#
</code></pre>
Software Development: RE: Cannot establish an ethernet connection
http://support.criticallink.com/redmine/boards/10/topics/6256?r=6309#message-6309
2023-04-07T21:46:14Z
Jonathan Cormier
jcormier@criticallink.com
<p>Thanks.</p>
<pre>
Resetting ethernet phy
Net: Ethernet PHY: GENERIC @ 0x03 [0x8]
</pre><br />So this boot, your phy was found at address 0x03. Which is what the kernel expects so I would assume it would have worked. But according to your logs sometimes the phy address is 0x01 which causes the kernel to not find the phy.
<p>In baseboard_pre_init() if I set the phy_id to NULL, the kernel should search for the first phy it can find. Which should solve your issue, though i'm not sure why it keeps changing on your hardware.</p>
<p>baseboard-industrialio.c<br /><pre>
static int __init baseboard_pre_init(void)
{
pr_info("%s: Entered\n", __func__);
da8xx_spi_pdata[1].chip_sel = spi1_cs;
da8xx_spi_pdata[1].num_chipselect = ARRAY_SIZE(spi1_cs);
davinci_soc_info.emac_pdata->phy_id = NULL;
return 0;
}
</pre></p>
Software Development: RE: Cannot establish an ethernet connection
http://support.criticallink.com/redmine/boards/10/topics/6256?r=6308#message-6308
2023-04-07T20:35:08Z
Vadym Kolesnyk
<p>80-000268RI-3 B<br />14012628<br />14-11-05</p>
<pre><code>
OMAP-L138/AM-1808/AM-1810 initialization passed!
Configuring 256MB mDDR
Booting TI User Boot Loader
UBL Version: 1.65:2.28.1 BuiltJul 11 2011 12:49:53
UBL Flashtype: SPI
Starting SPI Memory Copy...
Valid magicnum, 0x55424CBB, found at offset 0x00010000.
DONE
Jumping to entry point at 0xC1080000.
U-Boot 2009.11-00004-gabfcd79 (Jan 03 2018 - 11:30:43)
I2C: ready
DRAM: 256 MB
NAND: 512 MiB
MMC: davinci: 0
In: serial
Out: serial
Err: serial
ARM Clock : 300000000 Hz
DDR Clock : 150000000 Hz
EMIFA CLock : 100000000 Hz
DSP Clock : 300000000 Hz
ASYNC3 Clock : 150000000 Hz
Enet config : 2
MMC 0 Enable : 1
Resetting ethernet phy
Net: Ethernet PHY: GENERIC @ 0x03 [0x8]
Hit any key to stop autoboot: 0
U-Boot > dhcp
BOOTP broadcast 1
DHCP client bound to address 192.168.0.111
U-Boot > config
MityDSP-L138 Configuration:
Config Version : 1.0
Config Size : 264
Manufacturer : Critical Link
Ethernet Config : 2
Ethernet Name : GENERIC @ 0x03
Ethernet PHYMask: 8
LCD Config : 0
MMC0 Config : 1
MMC1 Config : 0
</code></pre>
Software Development: RE: Cannot establish an ethernet connection
http://support.criticallink.com/redmine/boards/10/topics/6256?r=6307#message-6307
2023-04-07T20:02:46Z
Jonathan Cormier
jcormier@criticallink.com
<p>Can you provide your 80- number and serial number from the barcode on your devkit?</p>
<p>If you stop at u-boot, does the dhcp command work?<br />And can you run the config command and give me the output</p>
<pre>
OMAP-L138/AM-1808/AM-1810 initialization passed!
Configuring 128MB mDDR
Booting TI User Boot Loader
UBL Version: 1.65:2.28.1 BuiltJul 11 2011 12:49:53
UBL Flashtype: SPI
Starting SPI Memory Copy...
Valid magicnum, 0x55424CBB, found at offset 0x00010000.
DONE
Jumping to entry point at 0xC1080000.
U-Boot 2009.11-00023-gfca022b96949 (Jun 29 2022 - 17:21:16)
I2C: ready
DRAM: 128 MB
NAND: 256 MiB
MMC: davinci: 0
In: serial
Out: serial
Err: serial
Info - Didn't find block
MityDSP-L138 - Model No: L138-DG-225-RI Serial No: 122098 Part Number:
ARM Clock : 300000000 Hz
DDR Clock : 150000000 Hz
EMIFA CLock : 100000000 Hz
DSP Clock : 300000000 Hz
ASYNC3 Clock : 150000000 Hz
Enet config : 2
MMC 0 Enable : 1
Resetting ethernet phy
Net: Ethernet PHY: GENERIC @ 0x03 [0x8]
Hit any key to stop autoboot: 0
U-Boot > dhcp
BOOTP broadcast 1
DHCP client bound to address 10.0.100.101
U-Boot > config
MityDSP-L138 Configuration:
Config Version : 1.0
Config Size : 264
Manufacturer : Critical Link
Ethernet Config : 2
Ethernet Name : GENERIC @ 0x03
Ethernet PHYMask: 8
LCD Config : 0
MMC0 Config : 1
MMC1 Config : 0
</pre>
Software Development: RE: Cannot establish an ethernet connection
http://support.criticallink.com/redmine/boards/10/topics/6256?r=6306#message-6306
2023-04-07T19:21:34Z
Vadym Kolesnyk
<p>I use critical link industrial io baseboard</p>
Software Development: RE: Cannot establish an ethernet connection
http://support.criticallink.com/redmine/boards/10/topics/6256?r=6305#message-6305
2023-04-07T18:52:22Z
Vadym Kolesnyk
<p>Initially, I could connect via a local network, i.e., I just connected the devkit to the router (without changing anything in /etc/network/interfaces or other manipulations). The connection was established without problems. I didn’t even pay much attention to the output when starting the devkit, it just worked, and that’s it. After a while (half a year), when I returned to work with this board again, connecting in the same way was no longer possible. The first assumption was that the router impacts. So I tried to connect directly (i.e., plug the ethernet cable from the devkit to the PC). I did not find a guide on doing this correctly, so I tried it by analogy with raspberry pi. Nothing worked.</p>
<p>Ideally, I need to work on a local network, but it would also be nice to do it through a direct connection.</p>
Software Development: RE: Cannot establish an ethernet connection
http://support.criticallink.com/redmine/boards/10/topics/6256?r=6304#message-6304
2023-04-07T17:35:41Z
Jonathan Cormier
jcormier@criticallink.com
<p>I'm sorry, but you need to answer my questions if we are going to get to the bottom of this.</p>
Software Development: RE: Cannot establish an ethernet connection
http://support.criticallink.com/redmine/boards/10/topics/6256?r=6303#message-6303
2023-04-07T16:49:30Z
Vadym Kolesnyk
<p>The output I obtained now is in the attached file. Now I want to connect directly to the PC to eliminate router influence. May I do any specific actions? I have tried to do it (like I did with raspberry pi before, for example) but achieved nothing. I understand that it is a natural result of the fact that the eth0 is essentially not initialized, but what else can be done? The previous time this bug disappeared randomly.</p>
Software Development: RE: Discussion: Kernel hangs on "Waiting for root device /dev/mmcblk0p1..."
http://support.criticallink.com/redmine/boards/10/topics/6291?r=6302#message-6302
2023-04-07T15:39:27Z
Vadym Kolesnyk
<p>Hello, I'm sorry for the delay. I have reprogrammed u-boot as you advised. Loading from a "guilty" SD card is as fast as before, with no freezes. The only problem that returns is that I cannot establish an ethernet connection again (for ssh and package installation/updates). It is quite similar to <a class="external" href="https://support.criticallink.com/redmine/boards/10/topics/6256">https://support.criticallink.com/redmine/boards/10/topics/6256</a>, so it may be better to discuss it there.</p>
<pre><code>
ADDRCONF(NETDEV_UP): eth0: link is not ready
</code></pre>
Software Development: RE: Discussion: Kernel hangs on "Waiting for root device /dev/mmcblk0p1..."
http://support.criticallink.com/redmine/boards/10/topics/6291?r=6301#message-6301
2023-04-04T13:22:40Z
Jonathan Cormier
jcormier@criticallink.com
<p>Vadym Kolesnyk wrote in <a class="message" href="http://support.criticallink.com/redmine/boards/10/topics/6291?r=6300#message-6300">RE: Discussion: Kernel hangs on "Waiting for root device ...</a>:</p>
<blockquote>
<p>Yes, the md5 sum and all installation process outputs are equal.</p>
</blockquote>
<p>Okay that is good</p>
<blockquote>
<p>So, I tried to set up a newly-bought SD card today. Kernel initialization hung again, but this time, I did not turn it off after that and left it for a while (not intentionally). After about half an hour, I discovered this, and it turned out that <strong>the kernel was loaded successfully</strong>! I don’t know what affected this time: the fact that the card was totally new or that I had waited long enough. I didn’t seem to be in a hurry to turn it off before and waited about five minutes each time. Also, I should point out that now repetitive launches are complete in a habitual span.</p>
</blockquote>
<p>The next thing we should try is reprogramming u-boot and the ubl. Since we've tried several SD cards and they all act the same, we should make sure that u-boot on the SOM nor isn't the problem. Follow the steps in the below link using the 2018 dead programming files linked in the guide. Make sure also to do the config set steps at the end.</p>
<p>Note: If you want to skip to trying the config set steps just as a quick test, there is a chance it could help.</p>
<p><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Reprogramming_the_Bootloader">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Reprogramming_the_Bootloader</a></p>
<blockquote>
<p>Sorry that puzzled you.</p>
</blockquote>
<p>Haha no, that's alright. I meant to reassure you that this is not expected behavior.</p>
Software Development: RE: Discussion: Kernel hangs on "Waiting for root device /dev/mmcblk0p1..."
http://support.criticallink.com/redmine/boards/10/topics/6291?r=6300#message-6300
2023-04-04T11:45:12Z
Vadym Kolesnyk
<p>Yes, the md5 sum and all installation process outputs are equal.</p>
<p>So, I tried to set up a newly-bought SD card today. Kernel initialization hung again, but this time, I did not turn it off after that and left it for a while (not intentionally). After about half an hour, I discovered this, and it turned out that <strong>the kernel was loaded successfully</strong>! I don’t know what affected this time: the fact that the card was totally new or that I had waited long enough. I didn’t seem to be in a hurry to turn it off before and waited about five minutes each time. Also, I should point out that now repetitive launches are complete in a habitual span.</p>
<p>Sorry that puzzled you.</p>
Software Development: RE: Discussion: Kernel hangs on "Waiting for root device /dev/mmcblk0p1..."
http://support.criticallink.com/redmine/boards/10/topics/6291?r=6299#message-6299
2023-04-03T21:15:01Z
Jonathan Cormier
jcormier@criticallink.com
<blockquote>
<p>I understand the only possible solution is to reset radically devkit somehow, but why this strange bug may have happened? There was no outside interference. The devkit just wasn't turned on for a month.</p>
</blockquote>
<p>Yeah, this is unexpected.</p>
Software Development: RE: Discussion: Kernel hangs on "Waiting for root device /dev/mmcblk0p1..."
http://support.criticallink.com/redmine/boards/10/topics/6291?r=6298#message-6298
2023-04-03T20:06:45Z
Jonathan Cormier
jcormier@criticallink.com
<blockquote>
<p>Did you grab the mityomap-full.tgz file from MDK_2014-01-13? I just want to follow the same steps and make sure it still works on my end.</p>
</blockquote>
<p>Looking at your log, your kernel build date matches the 2014 MDK so I'm going to assume yes.</p>
<p>Can you md5sum the mityomap-full.tgz and make sure it matches "38903bff19adc905ca8a07f8c44bb5c6"?</p>
<p>I attached my boot log and the instructions I ran from the wiki for reference. I'm pretty sure you got the instructions correct otherwise u-boot wouldn't have been able to load the kernel image.<br /><pre>
$ md5sum /home/tools/mitydsp-l138/MDK_2014-01-13/fs/mityomap-full.tgz
38903bff19adc905ca8a07f8c44bb5c6 /home/tools/mitydsp-l138/MDK_2014-01-13/fs/mityomap-full.tgz
$ sudo mkfs.ext3 -L "rootfs" /dev/sdd1
mke2fs 1.45.5 (07-Jan-2020)
/dev/sdd1 contains a vfat file system labelled 'boot'
Proceed anyway? (y,N) y
Creating filesystem with 1940224 4k blocks and 485760 inodes
Filesystem UUID: c60609c2-4475-4246-a75c-47784717f194
Superblock backups stored on blocks:
32768, 98304, 163840, 229376, 294912, 819200, 884736, 1605632
Allocating group tables: done
Writing inode tables: done
Creating journal (16384 blocks): done
Writing superblocks and filesystem accounting information: done
sudo mount /dev/sdd1 /mnt
cd /mnt
$ sudo tar xzvf /home/tools/mitydsp-l138/MDK_2014-01-13/fs/mityomap-full.tgz
...
$ ll
total 80
drwxr-sr-x 18 root root 4096 Aug 9 2012 ./
drwxr-sr-x 1 root root 310 Oct 14 13:56 ../
drwxr-xr-x 2 root root 4096 Aug 9 2012 bin/
drwxr-sr-x 2 root root 4096 Aug 9 2012 boot/
drwxr-sr-x 3 root root 4096 Jun 6 2012 dev/
drwxr-xr-x 34 root root 4096 Aug 9 2012 etc/
drwxr-sr-x 3 root root 4096 Aug 9 2012 home/
drwxr-xr-x 6 root root 4096 Aug 9 2012 lib/
drwx------ 2 root root 16384 Apr 3 15:56 lost+found/
drwxr-sr-x 10 root root 4096 Aug 9 2012 media/
drwxr-sr-x 3 root root 4096 Aug 9 2012 mnt/
drwxr-sr-x 2 root root 4096 Jun 6 2012 proc/
drwxr-sr-x 2 root root 4096 Jun 6 2012 run/
drwxr-xr-x 2 root root 4096 Aug 9 2012 sbin/
drwxr-sr-x 2 root root 4096 Jun 6 2012 sys/
drwxrwsrwt 2 root root 4096 Jun 6 2012 tmp/
drwx--S--- 10 root root 4096 Jun 6 2012 usr/
drwxr-xr-x 12 root root 4096 Aug 9 2012 var/
$ cd /
$ sudo umount /mnt
</pre></p>
Software Development: RE: Discussion: Kernel hangs on "Waiting for root device /dev/mmcblk0p1..."
http://support.criticallink.com/redmine/boards/10/topics/6291?r=6297#message-6297
2023-04-03T19:51:29Z
Jonathan Cormier
jcormier@criticallink.com
<p>Thanks for the update.</p>
<p>Did you grab the mityomap-full.tgz file from MDK_2014-01-13? I just want to follow the same steps and make sure it still works on my end.</p>
Software Development: RE: Discussion: Kernel hangs on "Waiting for root device /dev/mmcblk0p1..."
http://support.criticallink.com/redmine/boards/10/topics/6291?r=6296#message-6296
2023-04-03T18:02:30Z
Vadym Kolesnyk
<p>Sorry if I have described my problem not clearly. Yes, I booted this devkit successfully with my sd card before (about a month ago). Nobody except me worked with this devkit. The kernel is without any changes from my side. I use the default mityomap-full.tgz version from the MDK folder. Uboot also did not reconfigure in any way.</p>
<p>Today I've tried to set up another two SD cards to exclude possible card-relief problems. I did all strongly according to the wiki manual mentioned before. But still no effect.</p>
<p>I understand the only possible solution is to reset radically devkit somehow, but why this strange bug may have happened? There was no outside interference. The devkit just wasn't turned on for a month.</p>
Software Development: RE: Discussion: Kernel hangs on "Waiting for root device /dev/mmcblk0p1..."
http://support.criticallink.com/redmine/boards/10/topics/6291?r=6295#message-6295
2023-04-03T13:11:45Z
Jonathan Cormier
jcormier@criticallink.com
<p>Vadym Kolesnyk wrote in <a class="message" href="http://support.criticallink.com/redmine/boards/10/topics/6291?r=6294#message-6294">RE: Discussion: Kernel hangs on "Waiting for root device ...</a>:</p>
<blockquote>
<p>I use the standard devkit. When I had problems with the SD card (for example, bad partition), I got these messages:<br />[...]<br />I get the same when the card is not connected at all.</p>
</blockquote>
<p>Okay, so the above message is what you get if u-boot can't find the sdcard and/or the kernel image on the sdcard. According to your log, u-boot finds the sdcard and loads the kernel. Then when the kernel starts booting, it cannot find the sdcard. Have you modified the kernel?</p>
<p>Have you successfully booted this devkit before? If so what changed since then?</p>
Software Development: RE: Discussion: Kernel hangs on "Waiting for root device /dev/mmcblk0p1..."
http://support.criticallink.com/redmine/boards/10/topics/6291?r=6294#message-6294
2023-04-01T05:50:14Z
Vadym Kolesnyk
<p>I use the standard devkit. When I had problems with the SD card (for example, bad partition), I got these messages:<br /><pre><code>** Bad partition 1 **
Wrong Image Format for bootm command
ERROR: can't get kernel image!
</code></pre><br />I get the same when the card is not connected at all.</p>
Software Development: RE: Discussion: Kernel hangs on "Waiting for root device /dev/mmcblk0p1..."
http://support.criticallink.com/redmine/boards/10/topics/6291?r=6293#message-6293
2023-03-31T21:30:47Z
Jonathan Cormier
jcormier@criticallink.com
<p>If this is a custom baseboard without the card detect hooked up. Then this could also happen.</p>
<p>For an example of disabling card detect and/or the read-only pin see baseboard_hfm.c:<br />baseboard_hfm.c:<br /><pre>
static int baseboard_mmc_get_ro(int index)
{
// Assume always rw
return 0;
}
static int baseboard_mmc_get_cd(int index)
{
// Assume always present
return true;
}
</pre></p>
Software Development: RE: Discussion: Kernel hangs on "Waiting for root device /dev/mmcblk0p1..."
http://support.criticallink.com/redmine/boards/10/topics/6291?r=6292#message-6292
2023-03-31T21:24:53Z
Jonathan Cormier
jcormier@criticallink.com
<p>That is unexpected. Your boot log looks like everything is correct. It looks similar to if you had no sdcard plugged in at all. Even if you flashed the sdcard incorrectly, I would still expect to see the mmc show up.</p>
<p>Example of successfully probed sdcard<br /><pre>
mmc0: new high speed SDHC card at address aaaa
mmcblk0: mmc0:aaaa SU04G 3.69 GiB
mmcblk0: p1
</pre></p>
<p>Based on your log, I'd say most likely either the sdcard is broken somehow or there is a hardware issue.</p>
Software Development: Discussion: Kernel hangs on "Waiting for root device /dev/mmcblk0p1..."
http://support.criticallink.com/redmine/boards/10/topics/6291
2023-03-31T16:01:36Z
Vadym Kolesnyk
<p>I made rootfs on an SD card according to this wiki page (<a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Linux_Root_File_System">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Linux_Root_File_System</a>), but every time kernel hanging on "Waiting for root device /dev/mmcblk0p1...". The full log of boot loading is in the attached file.</p>
Software Development: RE: Increasing CPU clock OMAPL138
http://support.criticallink.com/redmine/boards/10/topics/6278?r=6290#message-6290
2023-03-31T11:14:44Z
Kim Nielsen
<p>Hi Mike,</p>
<p>Ah, makes sense.<br />For the time being I'll stick with controlling the clock frequency with Linux.</p>
<p>Thank you for your time.</p>
<p>Regards,<br />Kim</p>
Software Development: RE: Increasing CPU clock OMAPL138
http://support.criticallink.com/redmine/boards/10/topics/6278?r=6289#message-6289
2023-03-29T19:03:06Z
Michael Williamson
<p>Hi Kim,</p>
<p>I think the reason why the uBoot Critical Link publishes is using 300 MHz is because the Revision 1 silicon was only rated to 300 MHz for 1.2V operation. See Note (7) of section 5.3 of the datasheet. For Revision 1 silicon, 372 MHz was not allowed.</p>
<p>I think we may have revision 1.x silicon SOMs in the field, so we've not changed it. Generally, customers have been OK with boosting it to higher frequencies immediately following linux boot with an init V or systemd script.</p>
<p>It is certainly possible to modify uBoot to alter the PLL settings for speed the system up to 372 Mhz and/or send the I2C command to the PMIC to bump the voltage. If you need help altering the code, we can look into it, but we would have to provide it on an alternative / custom branch due to the issues mentioned above.</p>
<p>With regards,<br />Mike</p>
Software Development: RE: Increasing CPU clock OMAPL138
http://support.criticallink.com/redmine/boards/10/topics/6278?r=6288#message-6288
2023-03-27T14:12:13Z
Kim Nielsen
<p>Alright.</p>
<p>Is there is no way to change the default frequency from 300Mhz to e.g. 372MHz with U-Boot?<br />As far as I can see, according to <strong>Table 6-5. Maximum Internal Clock Frequencies at Each Voltage Operating Point</strong> in <strong>OMAP-L138 C6000 DSP+ARM Processor datasheet (Rev. J)</strong> <br />voltage of 1.2V should be ok for 300MHz and 372MHz, but 300MHz seems to be selected at boot.</p>
<p><a href="https://www.ti.com/lit/gpn/omap-l138" class="external">Link to OMAP-L138 datasheet</a></p>
Software Development: RE: Increasing CPU clock OMAPL138
http://support.criticallink.com/redmine/boards/10/topics/6278?r=6287#message-6287
2023-03-27T14:01:05Z
Michael Williamson
<p>Hi Kim,</p>
<p>I think the issue is that the voltage scaling needs to be done to default<br />to a higher frequency.</p>
<p>The PMIC defaults the core voltage to support 300 MHz and I don't think<br />uBoot adjusts it -- it starts all the PLLs, etc., at 300 MHz.</p>
<p>So the kernel probably starts at 300MHz to be safe. Not sure if you can<br />force it to adjust with a kernel command line or not.</p>
<p>-Mike</p>
Software Development: RE: Increasing CPU clock OMAPL138
http://support.criticallink.com/redmine/boards/10/topics/6278?r=6286#message-6286
2023-03-27T14:00:51Z
Jonathan Cormier
jcormier@criticallink.com
<p>I don't see an obvious default frequency config in the kernel, I'd guess that it stays with whatever frequency was setup by u-boot. But that would need to be tested.</p>
<p>You could use the ONDEMAND governor as default if you want it to scale up/down depending on load. Or the PERFORMANCE governor if you just want max frequency all the time.</p>
Software Development: RE: Increasing CPU clock OMAPL138
http://support.criticallink.com/redmine/boards/10/topics/6278?r=6285#message-6285
2023-03-27T13:44:32Z
Kim Nielsen
<p>I actually got another question.</p>
<p>By default, the cpu frequency seems to always be 300 MHz.</p>
<p>Is this value hardcoded in the kernel somewhere?<br />Can't seem to find it.</p>
<p>/Kim</p>
Software Development: RE: Increasing CPU clock OMAPL138
http://support.criticallink.com/redmine/boards/10/topics/6278?r=6284#message-6284
2023-03-24T17:24:03Z
Jonathan Cormier
jcormier@criticallink.com
<p>Kim Nielsen wrote in <a class="message" href="http://support.criticallink.com/redmine/boards/10/topics/6278?r=6283#message-6283">RE: Increasing CPU clock OMAPL138</a>:</p>
<blockquote>
<p>It's our own "experimental" kernel.<br />It seems to be working now. The issue was that the pll0 registers were apparently locked by CFGCHIP0.</p>
<p>Thank you for your time.<br />/Kim</p>
</blockquote>
<p>Gotcha, just curious if your based off of 4.19 from mainline or if you started from a TI kernel. Glad you got it working though.</p>
Software Development: RE: Increasing CPU clock OMAPL138
http://support.criticallink.com/redmine/boards/10/topics/6278?r=6283#message-6283
2023-03-24T12:21:04Z
Kim Nielsen
<p>It's our own "experimental" kernel.<br />It seems to be working now. The issue was that the pll0 registers were apparently locked by CFGCHIP0.</p>
<p>Thank you for your time.<br />/Kim</p>
Software Development: RE: Increasing CPU clock OMAPL138
http://support.criticallink.com/redmine/boards/10/topics/6278?r=6282#message-6282
2023-03-23T13:37:15Z
Jonathan Cormier
jcormier@criticallink.com
<p>Where is the 4.19 kernel based from? It doesn't appear to have working cpufreq.</p>
Software Development: RE: Increasing CPU clock OMAPL138
http://support.criticallink.com/redmine/boards/10/topics/6278?r=6281#message-6281
2023-03-23T07:17:15Z
Kim Nielsen
<p>Hi Mike & Jonathan,</p>
<p>Thank you for the fast reply :-)</p>
<p>I have the following frequencies available according to the "scaling_available_frequencies" file.<br />456000 408000 372000 300000 200000 96000</p>
<p>We are actually using a newer kernel (4.19), but it is still under testing.</p>
<p>/Kim</p>
Software Development: RE: Increasing CPU clock OMAPL138
http://support.criticallink.com/redmine/boards/10/topics/6278?r=6280#message-6280
2023-03-22T21:25:30Z
Jonathan Cormier
jcormier@criticallink.com
<p>Hi Kim, What kernel version are you using? Testing this on our released 3.2 kernel appears to be working for me.</p>
<p>Note my module tested is only rated up to 372000khz. I can try to find a L138-F... module which should be good up to 456000khz, but 372000khz should still be a valid step.</p>
<pre>
root@mityomapl138:~# uname -a
Linux mityomapl138 3.2.0 #1 PREEMPT Mon Jan 13 11:06:16 EST 2014 armv5tejl GNU/Linux
root@mityomapl138:~# factoryconfig dump
Part Number : L138-DG-225-RI
...
root@mityomapl138:~# tail /sys/devices/system/cpu/cpu0/cpufreq/*
==> /sys/devices/system/cpu/cpu0/cpufreq/affected_cpus <==
0
==> /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq <==
300000
==> /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq <==
372000
==> /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_min_freq <==
96000
==> /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_transition_latency <==
2000000
==> /sys/devices/system/cpu/cpu0/cpufreq/related_cpus <==
0
==> /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies <==
372000 300000 200000 96000
==> /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors <==
userspace
==> /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq <==
300000
==> /sys/devices/system/cpu/cpu0/cpufreq/scaling_driver <==
davinci
==> /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor <==
userspace
==> /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq <==
372000
==> /sys/devices/system/cpu/cpu0/cpufreq/scaling_min_freq <==
96000
==> /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed <==
300000
==> /sys/devices/system/cpu/cpu0/cpufreq/stats <==
tail: read error: Is a directory
root@mityomapl138:~# echo 372000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_
setspeed
root@mityomapl138:~# tail /sys/devices/system/cpu/cpu0/cpufreq/*
==> /sys/devices/system/cpu/cpu0/cpufreq/affected_cpus <==
0
==> /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq <==
372000
==> /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq <==
372000
==> /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_min_freq <==
96000
==> /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_transition_latency <==
2000000
==> /sys/devices/system/cpu/cpu0/cpufreq/related_cpus <==
0
==> /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies <==
372000 300000 200000 96000
==> /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors <==
userspace
==> /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq <==
372000
==> /sys/devices/system/cpu/cpu0/cpufreq/scaling_driver <==
davinci
==> /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor <==
userspace
==> /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq <==
372000
==> /sys/devices/system/cpu/cpu0/cpufreq/scaling_min_freq <==
96000
==> /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed <==
372000
==> /sys/devices/system/cpu/cpu0/cpufreq/stats <==
tail: read error: Is a directory
root@mityomapl138:~#
</pre>
Software Development: RE: Increasing CPU clock OMAPL138
http://support.criticallink.com/redmine/boards/10/topics/6278?r=6279#message-6279
2023-03-22T17:23:20Z
Michael Williamson
<p>Hi Kim,</p>
<p>What do you get when you dump out the scaling_available_frequencies (I don't remember the exact name off the top of my head, but the file that lists the available frequencies that may be selected)?</p>
<p>-Mike</p>
Software Development: Increasing CPU clock OMAPL138
http://support.criticallink.com/redmine/boards/10/topics/6278
2023-03-22T15:14:30Z
Kim Nielsen
<p>Hi,</p>
<p>I'm using a "L138-FI-236-RL" SOM board with SYS/BIOS running on the DSP and Linux on the ARM.<br />The Linux is built by ourselves, but it is based on davinci Linux.<br />I have attached the config file I use and dmesg log.</p>
<p>Issue:<br />I would like to increase the CPU clock speed via Linux with "cpufreq".<br />These are the steps I use:<br />$ cd /sys/devices/system/cpu/cpu0/cpufreq/policy0<br />$ echo userspace > scaling_governor<br />$ echo 372000 > scaling_setspeed</p>
<p>But when I do this, the "cpuinfo_cur_freq" file still displays 300000.<br />I also see this warning in dmesg<br />"Warning: CPU frequency out of sync: cpufreq and timing core thinks of 456000, is 300000 kHz"</p>
<p>I had similar issues like this post: <a class="external" href="https://support.criticallink.com/redmine/boards/10/topics/3893?r=3895#message-3895">https://support.criticallink.com/redmine/boards/10/topics/3893?r=3895#message-3895</a><br />I have added "CONFIG_REGULATOR_TPS65023" and "CONFIG_REGULATOR" and also the patch for "board-mityomapl138.c".</p>
<p>Thanks,<br />Kim</p>
Software Development: RE: Autoboot Linux in terminal
http://support.criticallink.com/redmine/boards/10/topics/5692?r=6273#message-6273
2023-01-04T22:18:52Z
Jonathan Cormier
jcormier@criticallink.com
<p>Hi Demon, Just noticed you posted in an old thread. Could you create a new one describing what your trying to accomplish so it doesn't get mixed up with this one? It's fine to link to this one.</p>
Software Development: RE: Autoboot Linux in terminal
http://support.criticallink.com/redmine/boards/10/topics/5692?r=6272#message-6272
2023-01-04T22:16:50Z
Jonathan Cormier
jcormier@criticallink.com
<p>Demon Demonof wrote in <a class="message" href="http://support.criticallink.com/redmine/boards/10/topics/5692?r=6267#message-6267">RE: Autoboot Linux in terminal</a>:</p>
<blockquote>
<p>Hello!</p>
<p>I have a service "myApp.service". I want to autostart Linux myApp in terminal without background mode.</p>
<p>@<br />[Unit]<br />Description=myApp<br />After=network.service</p>
<p>[Service]<br />Type=simple<br />WorkingDirectory=/home/root<br />ExecStart={terminal} -e /home/root/myApp</p>
<p>[Install]<br />WantedBy=multi-user.target</p>
<p>@</p>
<p>What should be instead {terminal}?</p>
<p>Example: <code>ExecStart=-/sbin/getty -e /home/root/myApp</code></p>
</blockquote>
<p>Hi sorry for the late response. What you are asking for is pretty unusual. Why do you want your app to auto-run in the terminal on boot? Maybe we can find a better solution</p>
Software Development: RE: Autoboot Linux in terminal
http://support.criticallink.com/redmine/boards/10/topics/5692?r=6267#message-6267
2022-12-23T06:25:51Z
Demon Demonof
<p>Hello!</p>
<p>I have a service "myApp.service". I want to autostart Linux myApp in terminal without background mode.</p>
<p>@<br />[Unit]<br /> Description=myApp<br /> After=network.service</p>
<p>[Service]<br /> Type=simple<br /> WorkingDirectory=/home/root<br /> ExecStart={terminal} -e /home/root/myApp</p>
<p>[Install]<br /> WantedBy=multi-user.target</p>
<p>@</p>
<p>What should be instead {terminal}?</p>
<p>Example: <code>ExecStart=-/sbin/getty -e /home/root/myApp</code></p>
Software Development: RE: L138 dsplink problem - schedule while atomic bug
http://support.criticallink.com/redmine/boards/10/topics/4931?r=6266#message-6266
2022-12-22T13:04:24Z
Demon Demonof
<p>Demon Demonof wrote in <a class="message" href="http://support.criticallink.com/redmine/boards/10/topics/4931?r=6265#message-6265">RE: L138 dsplink problem - schedule while atomic bug</a>:</p>
<blockquote>
<p>Hello!</p>
<p>I have the same problem as the author of the topic.</p>
<p><code>Unable to handle kernel paging request at virtual address c6ce600c<br />pgd = c34d0000<br />[c6ce600c] *pgd=c3458811, *pte=00000000, *ppte=00000000<br />Internal error: Oops: 807 [#3] PREEMPT<br />Modules linked in: minix fpga_gpio(O) fpga_spi(O) fpga_uart(O) fpga_ctrl(O) dsplinkk(O) ipv6<br />CPU: 0 Tainted: G D O (3.2.0 #2)<br />PC is at remove_wait_queue+0x24/0x70<br />LR is at remove_wait_queue+0x1c/0x70<br />pc : [<c00366bc>] lr : [<c00366b4>] psr: 20000093<br />sp : c3561e50 ip : c356e044 fp : 00000000<br />r10: 80008051 r9 : 80040800 r8 : 00000001<br />r7 : c6ce6008 r6 : c3560000 r5 : 20000013 r4 : c3561e64<br />r3 : c6ce6008 r2 : c6ce6008 r1 : 00000000 r0 : 00000001<br />Flags: nzCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user<br />Control: 0005317f Table: c34d0000 DAC: 00000015<br />Process runAppX (pid: 2480, stack limit = 0xc3560270)<br />Stack: (0xc3561e50 to 0xc3562000)<br />1e40: c6ce6000 fffffe00 c3560000 bf0a6ffc<br />1e60: 80000013 00000001 c52e4f20 c0016fa0 c6ce6008 c6ce6008 00000004 ffffffff<br />1e80: 00008000 c3561f04 c6ce2000 bf0ad600 80008051 bf09d668 00000029 42d96d6c<br />1ea0: c018e03a 42d96d6c c5209928 c0009524 c3560000 00000000 42d96d54 bf0a9d38<br />1ec0: c3566400 c5271840 c35664cc c00366e0 c3566400 00000000 00000000 60000013<br />1ee0: c3560000 c05caed0 00000000 00008000 c802c800 00010002 ffffffff 00000000<br />1f00: 0000d06c 00000000 a0000093 c527a660 42d96d6c 42d96d6c c5209928 c0009524<br />1f20: 00000000 c0091300 c537a9e0 00000000 00000000 00000000 0000ffff 00000021<br />1f40: c5271848 00000002 c5a66b68 00000000 c3560000 00000000 00000001 c527a660<br />1f60: 00000000 c3412e00 c3561f8c c527a660 42d96d6c c018e03a 00000003 c0009524<br />1f80: c3560000 c00913b8 00000003 00000001 42d96d6c 000303cc 40caa814 000303d4<br />1fa0: 00000036 c00093a0 000303cc 40caa814 00000003 c018e03a 42d96d6c 00000003<br />1fc0: 000303cc 40caa814 000303d4 00000036 000303c8 42d96fa0 80008017 42d96d54<br />1fe0: 000303cc 42d96c38 0001052c 403c419c 80000010 00000003 0400287e 531403c6<br />[<c00366bc>] (remove_wait_queue+0x24/0x70) from [<bf0a6ffc>] (SYNC_WaitSEM+0x254/0x290 [dsplinkk])<br />[<bf0a6ffc>] (SYNC_WaitSEM+0x254/0x290 [dsplinkk]) from [<bf09d668>] (LDRV_MSGQ_get+0x84/0xc0 [dsplinkk])<br />[<bf09d668>] (LDRV_MSGQ_get+0x84/0xc0 [dsplinkk]) from [<bf0a9d38>] (DRV_Ioctl+0x1d0/0x778 [dsplinkk])<br />[<bf0a9d38>] (DRV_Ioctl+0x1d0/0x778 [dsplinkk]) from [<c0091300>] (do_vfs_ioctl+0x500/0x584)<br />[<c0091300>] (do_vfs_ioctl+0x500/0x584) from [<c00913b8>] (sys_ioctl+0x34/0x54)<br />[<c00913b8>] (sys_ioctl+0x34/0x54) from [<c00093a0>] (ret_fast_syscall+0x0/0x2c)<br />Code: e3a00001 ebff7d25 e5943010 e594200c (e5823004)<br />---[ end trace a91b929903800775 ]---<br />note: runAppX[2480] exited with preempt_count 1</code></p>
<p>Has anyone solved the problem?</p>
</blockquote>
<p>I use MDK_2014-01-12 and dsplink_linux_1_65_00_03.</p>
Software Development: RE: L138 dsplink problem - schedule while atomic bug
http://support.criticallink.com/redmine/boards/10/topics/4931?r=6265#message-6265
2022-12-22T12:59:08Z
Demon Demonof
<p>Hello!</p>
<p>I have the same problem as the author of the topic.</p>
<p><code>Unable to handle kernel paging request at virtual address c6ce600c<br />pgd = c34d0000<br />[c6ce600c] *pgd=c3458811, *pte=00000000, *ppte=00000000<br />Internal error: Oops: 807 [#3] PREEMPT<br />Modules linked in: minix fpga_gpio(O) fpga_spi(O) fpga_uart(O) fpga_ctrl(O) dsplinkk(O) ipv6<br />CPU: 0 Tainted: G D O (3.2.0 #2)<br />PC is at remove_wait_queue+0x24/0x70<br />LR is at remove_wait_queue+0x1c/0x70<br />pc : [<c00366bc>] lr : [<c00366b4>] psr: 20000093<br />sp : c3561e50 ip : c356e044 fp : 00000000<br />r10: 80008051 r9 : 80040800 r8 : 00000001<br />r7 : c6ce6008 r6 : c3560000 r5 : 20000013 r4 : c3561e64<br />r3 : c6ce6008 r2 : c6ce6008 r1 : 00000000 r0 : 00000001<br />Flags: nzCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user<br />Control: 0005317f Table: c34d0000 DAC: 00000015<br />Process runAppX (pid: 2480, stack limit = 0xc3560270)<br />Stack: (0xc3561e50 to 0xc3562000)<br />1e40: c6ce6000 fffffe00 c3560000 bf0a6ffc<br />1e60: 80000013 00000001 c52e4f20 c0016fa0 c6ce6008 c6ce6008 00000004 ffffffff<br />1e80: 00008000 c3561f04 c6ce2000 bf0ad600 80008051 bf09d668 00000029 42d96d6c<br />1ea0: c018e03a 42d96d6c c5209928 c0009524 c3560000 00000000 42d96d54 bf0a9d38<br />1ec0: c3566400 c5271840 c35664cc c00366e0 c3566400 00000000 00000000 60000013<br />1ee0: c3560000 c05caed0 00000000 00008000 c802c800 00010002 ffffffff 00000000<br />1f00: 0000d06c 00000000 a0000093 c527a660 42d96d6c 42d96d6c c5209928 c0009524<br />1f20: 00000000 c0091300 c537a9e0 00000000 00000000 00000000 0000ffff 00000021<br />1f40: c5271848 00000002 c5a66b68 00000000 c3560000 00000000 00000001 c527a660<br />1f60: 00000000 c3412e00 c3561f8c c527a660 42d96d6c c018e03a 00000003 c0009524<br />1f80: c3560000 c00913b8 00000003 00000001 42d96d6c 000303cc 40caa814 000303d4<br />1fa0: 00000036 c00093a0 000303cc 40caa814 00000003 c018e03a 42d96d6c 00000003<br />1fc0: 000303cc 40caa814 000303d4 00000036 000303c8 42d96fa0 80008017 42d96d54<br />1fe0: 000303cc 42d96c38 0001052c 403c419c 80000010 00000003 0400287e 531403c6<br />[<c00366bc>] (remove_wait_queue+0x24/0x70) from [<bf0a6ffc>] (SYNC_WaitSEM+0x254/0x290 [dsplinkk])<br />[<bf0a6ffc>] (SYNC_WaitSEM+0x254/0x290 [dsplinkk]) from [<bf09d668>] (LDRV_MSGQ_get+0x84/0xc0 [dsplinkk])<br />[<bf09d668>] (LDRV_MSGQ_get+0x84/0xc0 [dsplinkk]) from [<bf0a9d38>] (DRV_Ioctl+0x1d0/0x778 [dsplinkk])<br />[<bf0a9d38>] (DRV_Ioctl+0x1d0/0x778 [dsplinkk]) from [<c0091300>] (do_vfs_ioctl+0x500/0x584)<br />[<c0091300>] (do_vfs_ioctl+0x500/0x584) from [<c00913b8>] (sys_ioctl+0x34/0x54)<br />[<c00913b8>] (sys_ioctl+0x34/0x54) from [<c00093a0>] (ret_fast_syscall+0x0/0x2c)<br />Code: e3a00001 ebff7d25 e5943010 e594200c (e5823004)<br />---[ end trace a91b929903800775 ]---<br />note: runAppX[2480] exited with preempt_count 1</code></p>
<p>Has anyone solved the problem?</p>
Software Development: RE: Cannot establish an ethernet connection
http://support.criticallink.com/redmine/boards/10/topics/6256?r=6264#message-6264
2022-12-12T20:15:01Z
Jonathan Cormier
jcormier@criticallink.com
<p>You didn't answer any of my questions.<br />Are you connecting directly to your PC, and not connected to your normal network? I.E. a direct connection?</p>
<blockquote>
<p>Still not working.</p>
</blockquote>
<p>What exactly did you do?</p>
<blockquote>
<p>I notice that get this during load:</p>
</blockquote>
<p>I don't see the phy not found error in your boot log from post 3. Phy 3 looks to be correct since it was working so I don't know why you'd suddenly start getting errors where it is not found.</p>
<p>Are you using the criticallink industrial io baseboard? Or a custom-designed baseboard?</p>
Software Development: RE: Cannot establish an ethernet connection
http://support.criticallink.com/redmine/boards/10/topics/6256?r=6263#message-6263
2022-12-10T22:47:12Z
Vadym Kolesnyk
<p>Still not working. I notice that get this during load:<br /><pre><code class="shell syntaxhl">PHY 0:03 not found
net eth0: could not connect to phy 0:03
ADDRCONF<span class="o">(</span>NETDEV_UP<span class="o">)</span>: eth0: <span class="nb">link </span>is not ready
</code></pre></p>
Software Development: RE: Cannot establish an ethernet connection
http://support.criticallink.com/redmine/boards/10/topics/6256?r=6262#message-6262
2022-12-06T16:40:01Z
Jonathan Cormier
jcormier@criticallink.com
<blockquote>
<p>changing the ip value from none to dhcp</p>
</blockquote>
<p>Don't set dhcp in the kernel bootargs, this will cause boot to fail if it can't get an address and the kernel has no need to get a network connection on boot when you are booting from an sd card.</p>
<blockquote>
<p>So I want to try a peer-to-peer connection with a PC. How to configure it?</p>
</blockquote>
<p>Are you connecting directly to your PC, and not connected to your normal network? I.E. a direct connection?</p>
<p>This should work fine but you wont have a DHCP server so dhcp won't work. You'll need to set static IP addresses on your computer and on the devkit.<br /><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Setting_a_Static_IP_Address#MMCSD-Card-or-NAND-File-System">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Setting_a_Static_IP_Address#MMCSD-Card-or-NAND-File-System</a></p>
Software Development: RE: Cannot establish an ethernet connection
http://support.criticallink.com/redmine/boards/10/topics/6256?r=6261#message-6261
2022-12-06T09:15:14Z
Vadym Kolesnyk
<p>The problem has returned. And also, I noticed that the boot process stucks at this moment:</p>
<pre><code class="shell syntaxhl">PHY 0:03 not found
net eth0: could not connect to phy 0:03
Sending DHCP requests ...... timed out!
IP-Config: Reopening network devices...
PHY 0:03 not found
net eth0: could not connect to phy 0:03
Sending DHCP requests ...... timed out!
IP-Config: Auto-configuration of network failed.
</code></pre>
<p>So I want to try a peer-to-peer connection with a PC. How to configure it?</p>
Software Development: RE: Cannot establish an ethernet connection
http://support.criticallink.com/redmine/boards/10/topics/6256?r=6260#message-6260
2022-12-05T18:36:14Z
Jonathan Cormier
jcormier@criticallink.com
<p>Glad to hear it</p>
Software Development: RE: Cannot establish an ethernet connection
http://support.criticallink.com/redmine/boards/10/topics/6256?r=6259#message-6259
2022-12-05T18:03:16Z
Vadym Kolesnyk
<p>Suddenly it began to work correctly. I understand nothing;-) I suppose that router was the problem cause.</p>
Software Development: RE: Cannot establish an ethernet connection
http://support.criticallink.com/redmine/boards/10/topics/6256?r=6258#message-6258
2022-12-05T17:18:20Z
Vadym Kolesnyk
<p>Hi Jonathan, thank you for your reply!<br />Previously I have just connected the board to the router. I did not see the board in my LAN, and ifconfig output contained no IP except localhost. Then I tried to override boot command like this:</p>
<pre><code class="shell syntaxhl">U-Boot> setenv bootcmd <span class="s2">"mmcinfo; setenv bootargs mem = 96M console = ttyS1,115200n8 mtdparts = nand: 128M (rootfs), - (userfs) root = / dev / mmcblk0p1 rw rootwait ip = none; ext2load mmc 0: 1 c0700000 / boot / uImage; bootm "</span>
U-Boot> saveenv
</code></pre>
<p>I also tried to edit this configuration by changing the ip value from none to dhcp but still no result. I have made a lot of failed attempts yet. But today, when I saw your reply and decided to record the output log, I turned on board again, and now I see it in LAN but still cannot connect to it over ssh - connection timed out. I also cannot update packages, for example (but maybe this is quite another problem):</p>
<pre><code class="shell syntaxhl">root@mityomapl138:~# opkg update
Downloading http://feeds.angstrom-distribution.org/feeds/v2014.06/ipk/eglibc/armv5te/base/Packages.gz.
wget: bad address <span class="s1">'feeds.angstrom-distribution.org'</span>
Downloading http://feeds.angstrom-distribution.org/feeds/v2014.06/ipk/eglibc/armv5te/gstreamer/Packages.gz.
wget: bad address <span class="s1">'feeds.angstrom-distribution.org'</span>
Downloading http://feeds.angstrom-distribution.org/feeds/v2014.06/ipk/eglibc/armv5te/perl/Packages.gz.
wget: bad address <span class="s1">'feeds.angstrom-distribution.org'</span>
Downloading http://feeds.angstrom-distribution.org/feeds/v2014.06/ipk/eglibc/armv5te/python/Packages.gz.
wget: bad address <span class="s1">'feeds.angstrom-distribution.org'</span>
Downloading http://10.0.63.50/all/Packages.gz.
wget: can<span class="s1">'t connect to remote host (10.0.63.50): Network is unreachable
Downloading http://10.0.63.50/arm926ejste/Packages.gz.
wget: can'</span>t connect to remote host <span class="o">(</span>10.0.63.50<span class="o">)</span>: Network is unreachable
Downloading http://10.0.63.50/mityomapl138/Packages.gz.
wget: can<span class="s1">'t connect to remote host (10.0.63.50): Network is unreachable
Collected errors:
* opkg_download: Failed to download http://feeds.angstrom-distribution.org/feeds/v2014.06/ipk/eglibc/armv5te/base/Packages.gz, wget returned 1.
* opkg_download: Failed to download http://feeds.angstrom-distribution.org/feeds/v2014.06/ipk/eglibc/armv5te/gstreamer/Packages.gz, wget returned 1.
* opkg_download: Failed to download http://feeds.angstrom-distribution.org/feeds/v2014.06/ipk/eglibc/armv5te/perl/Packages.gz, wget returned 1.
* opkg_download: Failed to download http://feeds.angstrom-distribution.org/feeds/v2014.06/ipk/eglibc/armv5te/python/Packages.gz, wget returned 1.
* opkg_download: Failed to download http://10.0.63.50/all/Packages.gz, wget returned 1.
* opkg_download: Failed to download http://10.0.63.50/arm926ejste/Packages.gz, wget returned 1.
* opkg_download: Failed to download http://10.0.63.50/mityomapl138/Packages.gz, wget returned 1.
</span></code></pre>
<p>The boot log is in the attached file.</p>
Software Development: RE: Cannot establish an ethernet connection
http://support.criticallink.com/redmine/boards/10/topics/6256?r=6257#message-6257
2022-12-05T14:26:50Z
Jonathan Cormier
jcormier@criticallink.com
<p>Hi Vadym, Could you tell me what software and hardware you are using?</p>
<p>Also a console log from boot would be helpful showing the problem your seeing.</p>
Software Development: Cannot establish an ethernet connection
http://support.criticallink.com/redmine/boards/10/topics/6256
2022-12-04T22:10:12Z
Vadym Kolesnyk
<p>I cannot establish an ethernet connection for ssh and package updating. How to fix it?</p>
Software Development: RE: meta-mitydsp-l138 issue - SRCREV = "${AUTOREV}"
http://support.criticallink.com/redmine/boards/10/topics/6205?r=6207#message-6207
2022-08-30T21:26:54Z
Fred Weiser
Frederick.Weiser@technipfmc.com
<p>I do hope you reconsider the practice of using AUTOREV. Meanwhile, to protect myself, I'll duplicate your repo, make a stable branch, and store them locally.</p>
Software Development: RE: meta-mitydsp-l138 issue - SRCREV = "${AUTOREV}"
http://support.criticallink.com/redmine/boards/10/topics/6205?r=6206#message-6206
2022-08-30T20:58:39Z
Bob Duke
bob.duke@criticallink.com
<p>Fred,</p>
<p>I understand your concern. Your fix (set SRCREV to a specific commit) is the right one and we typically review that option with customers during delivery, although I missed reviewing that with you.</p>
<p>We typically have our Yocto builds use the latest versions of everything, but that can cause annoying problems if you are applying patches (as you discovered).</p>
<p>If you have any difficulty with adjusting the SRCREV or if you'd like me to create a separate stable branch on our support server, please let me know.</p>
Software Development: meta-mitydsp-l138 issue - SRCREV = "${AUTOREV}"
http://support.criticallink.com/redmine/boards/10/topics/6205
2022-08-30T20:07:27Z
Fred Weiser
Frederick.Weiser@technipfmc.com
<p>I'd like to report an issue in the meta-mitydsp-l138 (branch "daisy")repo where recipes use SRCREV = "${AUTOREV}". The specific issue I saw was caused by recent changes being pushed to the master branch of the u-boot-mitydspl138 repo, to which recipes in meta-mitydsp-l138 refer using SRCREV = "${AUTOREV}"; the changes broke the Yocto build I use as patches being applied fail. I might add that the recipe for our product was also written by Critical Link for a contract, and it also included SRCREV = "${AUTOREV}" (and the patches themselves). While functional at the time, the simple updates and pushes to u-boot-mitydspl138 broke quite a few things. My solution will be to revise the u-boot-mitydspl138 repo to have SRCREV point to the correct commit. I'd be happy to push the change for upstream if we can set up a merge request.</p>
<p>Meanwhile, I would recommend the general practice of always using specific commit hashes for all SRCREV commands in bitbake recipes to avoid further future problems. The practice assures any future build will exactly reproduce the build that was done originally.</p>
Software Development: RE: Is it possible to use C++ 11?
http://support.criticallink.com/redmine/boards/10/topics/6180?r=6183#message-6183
2022-03-30T13:40:21Z
Jonathan Cormier
jcormier@criticallink.com
<p>Also, Make sure to add the "-std=c++11" flag to the g++ compiler to actually enable c++11 features.</p>
Software Development: RE: Is it possible to use C++ 11?
http://support.criticallink.com/redmine/boards/10/topics/6180?r=6182#message-6182
2022-03-30T13:06:26Z
Vadym Kolesnyk
<p>Hello Mike,</p>
<p>That's exactly what I wanted to know. Thank you very much for your prompt reply <img src="/redmine/plugin_assets/redmine_wiki_extensions/images/smile.png" alt=":)"></p>
Software Development: RE: Is it possible to use C++ 11?
http://support.criticallink.com/redmine/boards/10/topics/6180?r=6181#message-6181
2022-03-30T12:45:00Z
Michael Williamson
<p>Hi Vadym,</p>
<p>Yes. Are you referring to the DSP programming or the ARM programming?</p>
<p>For the ARM, the version of GCC in the 2018 toolchain is 4.8.3. According to <a href="https://gcc.gnu.org/gcc-4.8/cxx0x_status.html" class="external">this page</a>, all of the c++11 standard is supported except garbage collection / leak detection.</p>
<p>If the DSP, the <a href="https://www.ti.com/tool/C6000-CGT" class="external">latest version of the compiler</a> should support up to c++14.</p>
<p>Does this help?</p>
<p>-Mike</p>
Software Development: Is it possible to use C++ 11?
http://support.criticallink.com/redmine/boards/10/topics/6180
2022-03-30T12:32:56Z
Vadym Kolesnyk
<p>I would know is it possible to apply the c++11 standard during development?</p>
Software Development: RE: Change data between ARM & DSP cores, undefined behaviour
http://support.criticallink.com/redmine/boards/10/topics/5715?r=6058#message-6058
2021-02-25T19:49:16Z
Demon Demonof
<p>Gregory Gluszek wrote:</p>
<blockquote>
<p>My guess is that the system is running out of DSPLink buffers. I would recommend checking return codes for functions such as GetBuffer(). GetBuffer() will return a NULL pointer if it cannot obtain a new buffer.</p>
<p>Thanks,<br />\Greg</p>
</blockquote>
<p>Maybe you need to create a memory pool cmem in the command line terminal?</p>
Software Development: RE: MityDSP-L138 Starterware Example Code
http://support.criticallink.com/redmine/boards/10/topics/1500?r=6053#message-6053
2021-01-11T19:45:57Z
Thomas Catalino
tom.catalino@criticallink.com
<p>Hello -</p>
<p>You may wish to post this on one of the TI forums.</p>
<p>We are unable to support TI development kits.</p>
<p>If you are using one of our OMAPL138 based SOM modules in a product we may be able to help.</p>
<p>Thank you</p>
Software Development: RE: MityDSP-L138 Starterware Example Code
http://support.criticallink.com/redmine/boards/10/topics/1500?r=6052#message-6052
2021-01-07T06:59:51Z
Shubham Khot
<p>Hello <br />I am working on the LCDKOMAP-l138 board for the timer driver.</p>
<p>When using the Sysdelay function after having used the SysDelayTimerSetup the application hangs.<br />Studying the source code(platform/beaglebone/sysdelay.c)) the Sysdelay function uses the Timer 0.</p>
<p>Debugging the code I show that the Counter Register (TCRR) of the Timer receives the proper value show<br />that after x milisecs it will overflow. But when the TimerEnable(SOC_TMR_0_REGS, TMR_TIMER12, TMR_ENABLE_ONCE); <br />is invoked instead of setting the TCLR _ST bit of the TCLR register, the value of the TCRR is cleared and the value of TCLR remains zero.</p>
<p>This results in never starting the timer and the Sysdelay function to get stuck at the <br />while(flagIsrCnt);<br />As the Timer never started and now overflow occurs to trigger an interrupt.</p>
<p>Since the TCR receives the proper value, I assume that the timer is configured properly. <br />Then what is the problem?</p>
Software Development: RE: OMAPL138: DSP Boot from Linux
http://support.criticallink.com/redmine/boards/10/topics/6024?r=6025#message-6025
2020-07-07T17:01:01Z
Michael Williamson
<p>Hello,</p>
<p>Could you load the DSP image and launch it using uBoot and have it wait / sync up with the ARM when it load linux.</p>
<p>We have a bootdsp command for uBoot that works with COFF files.</p>
<p><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Quick_Start">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Quick_Start</a></p>
<p>-Mike</p>
Software Development: OMAPL138: DSP Boot from Linux
http://support.criticallink.com/redmine/boards/10/topics/6024
2020-07-05T15:57:43Z
Aviv Prital
<p>Hello,</p>
<p>I have built a bare metal DSP image for custom board that I would like to load from ARM running linux. I do not use IPC API (ARM and DSP use proprietary drivers to exchange data over DSP memory ), just need to load and run.</p>
<p>Currently the only option partially working is DSPlink, which loads and runs the DSP image in COFF format well, but then it utilizes more that 90% ARM CPU and I cannot kill it.</p>
<p>Another option tried was to use slaveloader, but this silently did not run the full DSP image (neither COFF nor EABI), but succeeded to run some smaller image.</p>
<p>Is there any way to achieve my basic need?</p>
<p>Killing the DSPlink would be good enough.</p>
<p>Any advice?</p>
<p>Thanks,</p>
<p>Aviv</p>
Software Development: RE: OMAP L132E secure CPU
http://support.criticallink.com/redmine/boards/10/topics/5908?r=5910#message-5910
2020-01-13T16:39:31Z
Bob Duke
bob.duke@criticallink.com
<p>Bernd,</p>
<p>If you are using a Critical Link product in your design we are happy to help in this forum. From your picture, it looks like you are not using a Critical Link product.</p>
<p>If you have general questions about a custom design based on an OMAP processor, you should direct your questions to TI's e2e forum <<a class="external" href="https://e2e.ti.com/">https://e2e.ti.com/</a>> .</p>
<p>Thanks,</p>
<p>-Bob</p>
Software Development: RE: OMAP L132E secure CPU
http://support.criticallink.com/redmine/boards/10/topics/5908?r=5909#message-5909
2020-01-13T16:37:28Z
Bernd Schmitz
<p>This is the original Firmware the file above was for testing!</p>
Software Development: OMAP L132E secure CPU
http://support.criticallink.com/redmine/boards/10/topics/5908
2020-01-13T16:31:32Z
Bernd Schmitz
<p>I have a custom board with an OMAP L132E secure cpu (attached).The firmware is corrupted and I want to fix it.<br />In the schematic,I found this:<br />Oscillator clock is 19,2 MHz<br />Nand FLASH is 16 Bit 128 MByte MT29F1G16ABBDAH4<br />MDDR is 16 Bit 32 MByte MT46H16M16LFBF</p>
<p>I have a ramloder,the linux kernel and some other files in the firmware (attached).<br />Does anybody know,how can I flash it into the device?<br />UART acess is ok.<br />I downloaded the TI secure tools,but I don´t know what is exactly to do.</p>
Software Development: RE: NAND Flash
http://support.criticallink.com/redmine/boards/10/topics/5871?r=5879#message-5879
2019-11-21T06:52:07Z
Marcin Grzelak
<p>OK, I will try with TI's Processor SDK.<br />Thank you for your time.<br />Best regards</p>
Software Development: RE: NAND Flash
http://support.criticallink.com/redmine/boards/10/topics/5871?r=5877#message-5877
2019-11-20T15:36:22Z
Bob Duke
bob.duke@criticallink.com
<p>Marcin,</p>
<p>If you are using a Critical Link product in your design we are happy to help in this forum. From your comments, it looks like you are not using a Critical Link product. Our U-Boot is customized for our specific SOM. I would not recommend it for a different design.</p>
<p>TI's Processor SDK would be a better starting point <<a class="external" href="http://www.ti.com/tool/PROCESSOR-SDK-OMAPL138">http://www.ti.com/tool/PROCESSOR-SDK-OMAPL138</a>> .</p>
<p>If you have questions about a custom design based on the OMAP-L138, you should direct your questions to TI's e2e forum <<a class="external" href="https://e2e.ti.com/">https://e2e.ti.com/</a>> .</p>
<p>Thanks,</p>
<p>-Bob</p>
Software Development: RE: NAND Flash
http://support.criticallink.com/redmine/boards/10/topics/5871?r=5875#message-5875
2019-11-20T06:35:52Z
Marcin Grzelak
<p>This is not SOM. But our module, similar to the MityDSP-L138 only with one memory (NAND) and we use the U-Boot 2009.11.</p>
<p>I am looking for information about what may be the cause of wrong ECC calculation. Can I path this u-boot or use a different version?</p>
<p>Thank you for your advice.</p>
Software Development: RE: NAND Flash
http://support.criticallink.com/redmine/boards/10/topics/5871?r=5874#message-5874
2019-11-19T15:47:05Z
Jonathan Cormier
jcormier@criticallink.com
<p>Could you provide all the information on the barcode located on the module? Serial number, model number, etc.</p>
<p>It looks like you have a custom version of the UBL and u-boot.</p>
<p>Some oddities are that your clocks are non standard. U-boot is complaining about missing the NOR. And we don't recommend booting u-boot and kernel from the nand. They should be stored in the NOR.<br />See our architecture page.<br /><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/MityDSP-L138_Architecture#Non-Volatile-Storage">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/MityDSP-L138_Architecture#Non-Volatile-Storage</a></p>
<blockquote>
<p>UBL Flashtype: NAND<br />Starting NAND Copy...</p>
</blockquote>
<p>I'm also confused how you managed to load the UBL from nand. This is not a boot mode we support.</p>
<p>We also don't recommend using the 2.6 kernel for new designs.</p>
Software Development: RE: NAND Flash
http://support.criticallink.com/redmine/boards/10/topics/5871?r=5873#message-5873
2019-11-19T06:30:54Z
Marcin Grzelak
<p>Boot log<br /><pre>
OMAP-L138 initialization passed!
Booting TI User Boot Loader
UBL Version: 1.65
UBL Flashtype: NAND
Starting NAND Copy...
Valid magicnum, 0x55424CBB, found in block 0x00000006.
DONE
Jumping to entry point at 0xC1080000.
U-Boot 2009.11-svn (cze 19 2019 - 11:54:40)
I2C: ready
DRAM: 128 MB
NAND: 512 MiB
MMC: davinci: 0
Bad block table not found for chip 0
Bad block table not found for chip 0
Bad block table written to 0x00001ffe0000, version 0x01
Bad block table written to 0x00001ffc0000, version 0x01
In: serial
Out: serial
Err: serial
error reading I2C Configuration Block
Error - unable to probe SPI flash.
ARM Clock : 399360000 Hz
DDR Clock : 145920000 Hz
EMIFA CLock : 99840000 Hz
DSP Clock : 399360000 Hz
ASYNC3 Clock : 199680000 Hz
Enet config : 0
MMC 0 Enable : 0
Net: No ETH PHY detected!!!
Hit any key to stop autoboot: 0
Loading from nand0, offset 0x200000
Image Name: Linux-2.6.34-rc1
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 1429428 Bytes = 1.4 MB
Load Address: c0008000
Entry Point: c0008000
## Booting kernel from Legacy Image at c0700000 ...
Image Name: Linux-2.6.34-rc1
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 1429428 Bytes = 1.4 MB
Load Address: c0008000
Entry Point: c0008000
Verifying Checksum ... Bad Data CRC
ERROR: can't get kernel image!
</pre></p>
<p>printenv<br /><pre>
bootargs=mem=32M@0xc0000000 mem=64M@0xc4000000 console=ttyS0,115200n8 ubi.mtd=5,2048 root=ubi0:rootfs rootfstype=ubifs rootflags=sync
bootcmd=nboot 0xc0700000 0 0x200000; bootm 0xc0700000
bootdelay=1
baudrate=115200
bootfile="uImage"
flashuboot= mw.b 0xC0700000 0xFF 0x40000; loady 0xC0700000 115200; nand erase 0xc0000 0x40000; nand write 0xC0700000 0xc0000 0x40000;
flashkernel= mw.b 0xC2000000 0xFF 0x400000; loady 0xC2000000 115200; nand erase 0x200000 0x200000; nand write 0xC2000000 0x200000 0x200000;
flashrescue= mw.b 0xC2000000 0xFF 0x3000000; loady 0xC2000000 115200; nand erase 0x400000 0x400000; nand write 0xC2000000 0x400000 0x400000;
autoload=no
mtdids=nand0=nand
mtdparts=mtdparts=nand:128M(rootfs),-(userfs)
bootargsbase=mem=96M console=ttyS1,115200n8
flashargs=setenv bootargs ${bootargsbase} ${mtdparts} root=/dev/mtdblock0 rw,noatime rootfstype=jffs2
rescue=set bootargs initrd=0xc4000000,4174336 console=ttyS0,115200n8; nand read 0xc4000000 0x400000 0x400000; nboot 0xc0700000 0 0x200000; bootm 0xc0700000
stdin=serial
stdout=serial
stderr=serial
ver=U-Boot 2009.11-svn (cze 19 2019 - 11:54:40)
Environment size: 1116/131068 bytes
</pre></p>
Software Development: RE: NAND Flash
http://support.criticallink.com/redmine/boards/10/topics/5871?r=5872#message-5872
2019-11-18T15:04:31Z
Jonathan Cormier
jcormier@criticallink.com
<p>Please attach a complete boot log. And the output of 'printenv'</p>
Software Development: NAND Flash
http://support.criticallink.com/redmine/boards/10/topics/5871
2019-11-18T12:39:55Z
Marcin Grzelak
<p>Hello,<br />I have a board based on MityDSP-L138 with 4 Gb NAND Flash (MT29F4G08ABADAWP). And I use MityDSP-L138 u-boot (U-Boot 2009.11). But I probably have problem with ECC calculation. After some time during booting I get message:<br /><pre>
Verifying Checksum ... Bad Data CRC
ERROR: can't get kernel image!
</pre><br />Do you have any ideas what exactly is wrong?</p>
Software Development: RE: Enabling UART2 for MitydspL138F Expansion port at ARM running Linux
http://support.criticallink.com/redmine/boards/10/topics/5869?r=5870#message-5870
2019-11-13T16:25:50Z
Jonathan Cormier
jcormier@criticallink.com
<p>Aviv Prital wrote:</p>
<blockquote>
<p>Hi,</p>
<p>I'd like to use MitydspL138F Expansion port to get another serial connection to be used by Linux application.<br />What should be done for this (at U-boot, kernel, etc)?<br />I found some 6 years old related thread which was not completed:<br /><a class="external" href="https://support.criticallink.com/redmine/boards/10/topics/3548">https://support.criticallink.com/redmine/boards/10/topics/3548</a></p>
</blockquote>
<p>To use a peripheral on the L138 you need to ensure the pinmux is set correctly and the appropriate driver is enabled.</p>
UART2 is already setup in the kernel for use as an RS-485 port (though without the RS485 adapter its the same as a UART). These pins go to the J504 connector on the industrial io devkit. You can find the devkit schematics here: <a class="external" href="https://support.criticallink.com/redmine/projects/indio/wiki/Industrial_IO_Revision_Information">https://support.criticallink.com/redmine/projects/indio/wiki/Industrial_IO_Revision_Information</a>
<ul>
<li>The pinmux in the kernel is setup for UART2, so you should be able to use it by accessing /dev/ttyS2<br />baseboard-industrialio.c<br /><pre>
/**
* UART2 Pins for expansion port (RS-485 port).
*/
static short baseboard_uart2_pins[] __initdata = {
>---DA850_UART2_RXD,
>---DA850_UART2_TXD,
>----1,
};
</pre></li>
</ul>
<blockquote>
<p>I'm also curious about enabling UART2 from bare-metal dsp code.</p>
</blockquote>
<p>As long as the pins are pinmuxed, either in u-boot, linux, or your dsp code. Then you shouldn't have a problem using UART2. <a class="external" href="http://www.ti.com/lit/ug/sprufm6c/sprufm6c.pdf">http://www.ti.com/lit/ug/sprufm6c/sprufm6c.pdf</a></p>
Software Development: Enabling UART2 for MitydspL138F Expansion port at ARM running Linux
http://support.criticallink.com/redmine/boards/10/topics/5869
2019-11-12T15:27:34Z
Aviv Prital
<p>Hi,</p>
<p>I'd like to use MitydspL138F Expansion port to get another serial connection to be used by Linux application.<br />What should be done for this (at U-boot, kernel, etc)?<br />I found some 6 years old related thread which was not completed:<br /><a class="external" href="https://support.criticallink.com/redmine/boards/10/topics/3548">https://support.criticallink.com/redmine/boards/10/topics/3548</a><br />I'm also curious about enabling UART2 from bare-metal dsp code.</p>
<p>Thanks,<br />Aviv</p>
Software Development: RE: L138-FX-225-RC not available at Digikey
http://support.criticallink.com/redmine/boards/10/topics/5865?r=5868#message-5868
2019-10-25T15:42:57Z
Alexander Block
alex.block@criticallink.com
<p>Happy to hear you're all set and thanks for bringing the description issue to our attention.</p>
<p>I have forwarded your comments to our marketing team to look into it.</p>
<p>Alex</p>
Software Development: RE: L138-FX-225-RC not available at Digikey
http://support.criticallink.com/redmine/boards/10/topics/5865?r=5867#message-5867
2019-10-24T23:24:16Z
Ian St. John
isinjun@gmail.com
<p>Thank you. I actually just found this out. I was misdirected because the digikey descriptor for that part was</p>
<p>MITYDSP-+L138F+ SOM W/ OMAP-L138</p>
<p>and I believed that the L138F means it had an FPGA included. However, the part number itself was 1057-L138-FX-325-RC-ND which I was later to find was the same as the 1057-L138-FX-225-RC-ND but with 16 MB NOR as you point out.</p>
<p>Thanks. I can now order. Good to know about the 5 year active status.</p>
Software Development: RE: L138-FX-225-RC not available at Digikey
http://support.criticallink.com/redmine/boards/10/topics/5865?r=5866#message-5866
2019-10-24T21:27:40Z
Alexander Block
alex.block@criticallink.com
<p>The MityDSP-L138 family (both with and without the FPGA) is still in active production and is planned to be over the next 5 years plus.</p>
<p>The issue you are running into is actually due to this PCN20180209000 (<a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Module_Product_Change_Notifications">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Module_Product_Change_Notifications</a>) which discusses the fact that the 8MB NOR part went obsolete. Due to this we had to switch to a 16MB sized NOR which is why you are finding the "225" modules as unavailable from distribution but the "325" are, or will be, available. We are currently working on providing inventory to our distribution partners of the new "325" variants.</p>
<p>If you still need assistance in obtaining product feel free to contact us using our <a class="email" href="mailto:info@criticallink.com">info@criticallink.com</a> e-mail and someone from our sales team can provide further assistance. Please be sure to include information about how many units you need if you make such an inquiry.</p>
<p>Thanks,</p>
<p>Alex</p>
Software Development: L138-FX-225-RC not available at Digikey
http://support.criticallink.com/redmine/boards/10/topics/5865
2019-10-24T20:50:22Z
Ian St. John
isinjun@gmail.com
<p>I am developing for the L138-FX-225-RC MityDSP board. I can no longer source them at Digikey. All pages come back 404. There are pages for the <abbr title="F">L138</abbr> with FPGA but I am no FPGA programmer. Can anyone tell me what the MityDSP L138 path is going to be over the next 5 years or so and if the L138F (more expensive but available) can be used with no FPGA programming or experience as an L138 equivalent?</p>
<p>Note. I know that there are a few left at Mouser but there are issues that make Digikey a much easier option.</p>
Software Development: RE: Loading and running PRU
http://support.criticallink.com/redmine/boards/10/topics/5853?r=5860#message-5860
2019-09-24T21:30:07Z
Bob Duke
bob.duke@criticallink.com
<p>Aviv,</p>
<p>Did you try to run the example programs discussed in the thread you linked?</p>
<p><a class="external" href="https://support.criticallink.com/redmine/boards/10/topics/4026?r=4135#message-4135">https://support.criticallink.com/redmine/boards/10/topics/4026?r=4135#message-4135</a></p>
<p>That content should still be relevant since we are still running the 3.2 kernel in the latest MDK release for the MityDSP-L138.</p>
Software Development: Loading and running PRU
http://support.criticallink.com/redmine/boards/10/topics/5853
2019-08-28T12:49:13Z
Aviv Prital
<p>Hi, <br />I'd like to load and run a simple PRU .out writing to shared RAM at my MityDSP-L138F<br />I found some old related thread "How to enable PRU Subsystem on MityDSP-L138F SOM ???" (<a class="external" href="https://support.criticallink.com/redmine/boards/10/topics/4026?r=4135#message-4135">https://support.criticallink.com/redmine/boards/10/topics/4026?r=4135#message-4135</a>)<br />Is there any up-to-date howto?<br />ARM is running the following Linux version:<br />root@mityomapl138:~# cat /etc/os-release<br />ID=cl-systemd<br />NAME=Critical Link Linux (systemd)<br />VERSION=1.6.0 (daisy)<br />VERSION_ID=1.6.0<br />PRETTY_NAME=Critical Link Linux (systemd) 1.6.0 (daisy)<br />ANSI_COLOR=0;32<br />root@mityomapl138:~# uname -r<br />3.2.0+</p>
<p>Thanks,<br />Aviv</p>
Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)
http://support.criticallink.com/redmine/boards/10/topics/5845?r=5852#message-5852
2019-08-19T14:00:54Z
Jonathan Cormier
jcormier@criticallink.com
<p>Check out TI's CMEM.</p>
<blockquote>
<p>Note that you will probably have to invalidate caches when using shared memory. The CMEM ti kernel module can be used to reserve a chunk of memory and handle caching from linux user space. <a class="external" href="http://processors.wiki.ti.com/index.php/CMEM_Overview">http://processors.wiki.ti.com/index.php/CMEM_Overview</a></p>
</blockquote>
Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)
http://support.criticallink.com/redmine/boards/10/topics/5845?r=5851#message-5851
2019-08-18T11:54:38Z
Aviv Prital
<p>Hi,<br />I've leveraged TI's quickStartOMAPL1x_rCSL project and implemented the DSP side code sharing memory at SHARED_CPU_VARS_MEM 0x8001FC00 (sharedCpuVars.h).<br />At the ARM side I run Linux user space utility that mmaps this shared memory, reads and writes data. <br />The issue is that this utility successfully reads data, but cannot write. My guess is that there is no coherency between the sides. I don't see any section defined for SHARED_CPU_VARS_MEM in quickStartOMAPL1x_rCSL examples. <br />What are the solutions for this issue? Is there a way to flush/invalidate cache from user space?<br />Below is the user space code I run.<br />Thanks,<br />Aviv</p>
<p>typedef struct {<br /> Uint32 cnt;<br /> Uint32 rxpshptr; //Rx Fifo psh ptr<br /> Uint32 rxpopptr; //Rx Fifo pop ptr<br /> Uint32 rxfifo<sup><a href="#fn16">16</a></sup>; //Rx Fifo<br /> Uint32 overflow;<br />} SHARED_DSP_ARM_DATA;</p>
<p>SHARED_DSP_ARM_DATA *sd_ptr;</p>
<p>int main(int argc, char *argv[]) {<br /> if (argc < 2) {<br /> printf("Usage: %s <phys_addr> \n", argv<sup><a href="#fn0">0</a></sup>);<br /> return 0;<br /> }</p>
<pre><code>off_t offset = strtoul(argv[1], NULL, 16);</code></pre>
<pre><code>//size_t len = strtoul(argv[2], NULL, 16);<br /> size_t len = sizeof(SHARED_DSP_ARM_DATA);</code></pre>
<pre><code>// Truncate offset to a multiple of the page size, or mmap will fail.<br /> size_t pagesize = sysconf(_SC_PAGE_SIZE);<br /> off_t page_base = (offset / pagesize) * pagesize;<br /> off_t page_offset = offset - page_base;</code></pre>
<pre><code>int fd = open("/dev/mem", O_RDWR | O_SYNC);<br /> unsigned char *mem = (unsigned char *)mmap(NULL, page_offset + len, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, page_base);<br /> if (mem == MAP_FAILED) {<br /> perror("Can't map memory");<br /> return -1;<br /> }</code></pre>
<pre><code>sd_ptr = (SHARED_DSP_ARM_DATA *)&(mem[page_offset]);<br /> printf("1:cnt 0x%08x rxpshptr 0x%08x rxpopptr 0x%08x overflow 0x%08x\n", sd_ptr->cnt , sd_ptr->rxpshptr, sd_ptr->rxpopptr, sd_ptr->overflow);<br /> sd_ptr->rxpopptr += 1;<br /> sd_ptr->overflow = 0;<br /> printf("2:cnt 0x%08x rxpshptr 0x%08x rxpopptr 0x%08x overflow 0x%08x", sd_ptr->cnt , sd_ptr->rxpshptr, sd_ptr->rxpopptr, sd_ptr->overflow);<br /> printf("\n\n");<br /> return 0;<br />}</code></pre>
Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)
http://support.criticallink.com/redmine/boards/10/topics/5845?r=5850#message-5850
2019-07-22T13:34:26Z
Jonathan Cormier
jcormier@criticallink.com
<p>Aviv Prital wrote:</p>
<blockquote>
<p>Hi, thanks for reply!<br />Two follow up questions:<br />Concerning "you may want to look at some of the DSPlink or syslink code" where could I see this code?</p>
</blockquote>
<p>The dsplink sources are in the 2014 MDK. MDK_2014-01-13/sw/3rdparty/dsplink_linux_1_65_00_03<br />Syslink can be download here: <a class="external" href="http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/syslink/index.html">http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/syslink/index.html</a></p>
<blockquote>
<p>Concerning "opening "/dev/mem" and using mmap()": will I be able to read/write to any address in RAM?</p>
</blockquote>
<p>Yes but you shouldn't. Our default linux bootargs gives linux the first 96MB of memory to manage. Any memory managed by linux should not be directly accessed either from userspace /dev/mem or from the DSP, as this can lead to crashing your system. So under the default settings, you'd want to use the top 32MB to exchange information.</p>
Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)
http://support.criticallink.com/redmine/boards/10/topics/5845?r=5849#message-5849
2019-07-18T06:00:43Z
Aviv Prital
<p>Hi, thanks for reply!<br />Two follow up questions:<br />Concerning "you may want to look at some of the DSPlink or syslink code" where could I see this code?<br />Concerning "opening "/dev/mem" and using mmap()": will I be able to read/write to any address in RAM? <br />Aviv</p>
Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)
http://support.criticallink.com/redmine/boards/10/topics/5845?r=5848#message-5848
2019-07-17T15:04:10Z
Jonathan Cormier
jcormier@criticallink.com
<p>Note if your writing your own bare-metal communication you may want to look at some of the DSPlink or syslink code as you'll need to do similar things as they do.</p>
<p>Talked with another engineer.</p>
<blockquote>
<p>We have done a couple different things.</p>
<p>We have created a serial link in the FPGA which allows the ARM to open it's serial port, and another for the DSP. These are tied together allows the ARM and DSP to communicate as a normal serial port. This works fine for limited quantities of data.</p>
<p>We have also just passed memory addresses from the DSP to the ARM for bulk data. The ARM will access the memory usually opening "/dev/mem" and using mmap(). And the DSP can use mmap directly.</p>
</blockquote>
<p>Note that you will probably have to invalidate caches when using shared memory. The CMEM ti kernel module can be used to reserve a chunk of memory and handle caching from linux user space. <a class="external" href="http://processors.wiki.ti.com/index.php/CMEM_Overview">http://processors.wiki.ti.com/index.php/CMEM_Overview</a></p>
<p>Note we do have a wiki page on writing a bare-metal DSP app with StarterWare. <a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/StarterWare">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/StarterWare</a></p>
Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)
http://support.criticallink.com/redmine/boards/10/topics/5845?r=5847#message-5847
2019-07-17T14:05:34Z
Aviv Prital
<p>Thanks for the prompt reply!<br />I'm thinking about shared RAM that ARM user space linux driver will be able to mmap in order to write/read to DSP. <br />Thanks,<br />Aviv</p>
Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)
http://support.criticallink.com/redmine/boards/10/topics/5845?r=5846#message-5846
2019-07-17T14:01:00Z
Jonathan Cormier
jcormier@criticallink.com
<p>Could you provide more information on what is suitable for your project?</p>
Software Development: Change data between ARM(Linux) - DSP (bare-metal)
http://support.criticallink.com/redmine/boards/10/topics/5845
2019-07-17T13:44:49Z
Aviv Prital
<p>Hi,<br />I'd like to use MityDSPL138 kit in order to develop <abbr title="Linux">ARM</abbr> - DSP (bare-metal) data exchange over shared memory.<br />As far as I understand TI's DSPLink/SYSLINK rely on RTOS at DSP which is not suitable in my case.<br />Is there any example that I might use at least for reference? What are the other ways beside shared memory to implement such communication?<br />Thanks,<br />Aviv</p>
Software Development: RE: uPP receive clock lower limitation in SDR (Single Data Rate mode)
http://support.criticallink.com/redmine/boards/10/topics/5829?r=5839#message-5839
2019-07-08T10:05:19Z
Vivek Ponnani
vivek_p78@live.com
<p>Thanks Greg for your reply and sorry for the late reply.</p>
<p>I will forward your response to our FPGA team. They are using reference from AnalogExpansionSuite (from Critical Link).</p>
<p>Initially as I mentioned, we are able to get demodulated output when FPGA reads data at 40 MHz from ADC and sends data to uPP at 50 MHz clock rate.</p>
<p>We have tried with 12.5 MHz (from FPGA to uPP receive of DSP) clock with some preprocessing is done in FPGA, but the data we received on DSP side is different from the data sent by FPGA. FPGA side simulation shows the data is generated correctly but when we print the debug data on DSP side, the data is different.. Now what could be the reason? Is it clock related or something else? As we have never tried uPP receive clock below 50 MHz.</p>
<p>Thanks,<br />Vivek Ponnani.</p>
Software Development: RE: uPP receive clock lower limitation in SDR (Single Data Rate mode)
http://support.criticallink.com/redmine/boards/10/topics/5829?r=5830#message-5830
2019-06-24T16:38:00Z
Gregory Gluszek
<p>Hi Vivek,</p>
<p>I believe the datasheet is saying that regardless of whether the clock is being used as DDR or SDR the rate cannot be set below 4.69 MHz. However, this also seems to be assuming a default CPU clock of 300 MHz. This all seems to be tied to UPICR.CLKDIV and the maximum difference this allows between the clock fed to the uPP from the main CPU clock domain and the uPP receive clock coming in from the FPGA. It's possible, though not recommended (see below for what might be a better solution), that if you take a closer look at the rest of the clock tree you could further divide down the CPU clock being fed into the uPP to get the results you want.</p>
<p>That being said, rather than trying to change the clock tree and dealing with the myriad number of side effects that might have, could you add another clock domain and DCFIFO to your FPGA design? The uPP receive interface has an ENABLE pin and does not need a new sample of data each clock cycle. Therefore, why not have the logic receiving/processing your data run at the clock rate you need that is lower than 4.69 MHz, then have a DCFIFO that transitions this data to a faster clock domain that the uPP can handle (i.e. 75 MHz, 37.50 MHz, 4.69 MHz) and then have the logic in the uPP clock domain use the ENABLE signal to only mark valid data when it is in the FIFO?</p>
<p>Hope this helps.</p>
<p>Let me know if you have any further questions.</p>
<p>Thanks,<br />Greg</p>
Software Development: uPP receive clock lower limitation in SDR (Single Data Rate mode)
http://support.criticallink.com/redmine/boards/10/topics/5829
2019-06-21T08:05:39Z
Vivek Ponnani
vivek_p78@live.com
<p>Hi,</p>
<p>I have a custom board with <br />-- MityDspl-138F module (with FPGA)<br />-- No Ethernet port<br />-- UART,USB,SD CARD interface</p>
<p>we have done following steps till date.</p>
<p>-- I have built VM with MityDSP Critical_Link_Unified_VM_14-04_04-2017.ova file from critical link.<br />-- I have successfully run the example programs.<br />-- I have build new kernel with Analog Expansion support. We followed <a class="external" href="https://support.criticallink.com/redmine/projects/90-000173/wiki">https://support.criticallink.com/redmine/projects/90-000173/wiki</a> for the build of new kernel.<br />-- We have developed application in which DSP gets modulated data from ADC via FPGA interface. All the process is done in DSP and we are able to get demodulated output.<br />In this process FPGA reads data at 40MHz from ADC and sends data to uPP at 50 Mhz clock rate. everything is working fine.</p>
<p>Now some process is done in FPGA. FPGA sets clock to uPP interface in receive mode. Can FPGA sets the clock below 4.69 MHz for uPP(in receive mode)? <br />As per uPP datasheet, it limits lower clock limit in receive mode in DDR mode, The same thing applies to SDR mode? As it says "In receive mode, a channel I/O clock is generated by an external source, but the same speed limit applies", is for DDR only or SDR also?<br />Below is the reference point from uPP datasheet.</p>
<p>*2.1.3 Double Data Rate<br />The uPP peripheral supports two I/O clocking schemes. The first, single data rate (SDR), clocks data from<br />the DATA pins on either the rising edge or the falling edge (depending on UPICR.CLKINVn) of the I/O<br />clock.<br />The second clocking scheme is double data rate (DDR). In this mode, data is clocked on both the rising<br />and falling edges of the I/O clock. However, DDR mode imposes a lower I/O clock speed limit of one<br />eighth (1/8) the device CPU clock for both transmit and receive modes. The operating speed for transmit<br />mode with various divisors in each data rate are summarized in Table 1 (in this table, a data word is<br />defined as the data represented on the DATA pins; uPP supports data words in the 8-bit to 16-bit range).<br />In receive mode, a channel I/O clock is generated by an external source, but the same speed limit applies.
*</p>
<p>Thanks,<br />Vivek Ponnani.</p>
Software Development: RE: MityDSPL138
http://support.criticallink.com/redmine/boards/10/topics/5821?r=5827#message-5827
2019-06-06T15:12:32Z
Jonathan Cormier
jcormier@criticallink.com
<p>VIDYA J wrote:</p>
<blockquote>
<p>But in CCS they are asking initialization file for the processor.</p>
</blockquote>
<p>When your building?</p>
Software Development: RE: MityDSPL138
http://support.criticallink.com/redmine/boards/10/topics/5821?r=5826#message-5826
2019-06-06T15:10:52Z
VIDYA J
<p>But in CCS they are asking initialization file for the processor.</p>
Software Development: RE: MityDSPL138
http://support.criticallink.com/redmine/boards/10/topics/5821?r=5824#message-5824
2019-06-06T13:16:05Z
Jonathan Cormier
jcormier@criticallink.com
<p>VIDYA J wrote:</p>
<blockquote>
<p>I used UART_echo code from OMAPL138_StarterWare_1_10_03_03 folder. For coding ARM i read like i need to add gel file. Can you provide me the corresponding gel file. Without gel file when i tried the code was not getting debugged, but while building there was no error</p>
</blockquote>
<p>The gel file is not used for building the code. It is a list of instructions to the debugger to setup the CPU and memory interface.</p>
<p>Attached the two gel files from the 2014 MDK.</p>
Software Development: RE: MityDSPL138
http://support.criticallink.com/redmine/boards/10/topics/5821?r=5823#message-5823
2019-06-06T06:13:40Z
VIDYA J
<p>I used UART_echo code from OMAPL138_StarterWare_1_10_03_03 folder. For coding ARM i read like i need to add gel file. Can you provide me the corresponding gel file. Without gel file when i tried the code was not getting debugged, but while building there was no error</p>
Software Development: RE: MityDSPL138
http://support.criticallink.com/redmine/boards/10/topics/5821?r=5822#message-5822
2019-06-04T13:47:57Z
Jonathan Cormier
jcormier@criticallink.com
<p>VIDYA J wrote:</p>
<blockquote>
<p>For my project i want to do inter process communication on omapl138. Please reply for my below doubts<br />1. Is there Linux on board of MITYDSPL138-FX 225 RC, or is it something which i should do ?</p>
</blockquote>
<p>The SOMs don't come with Linux pre-installed, unless bought with a devkit. They have a bootloader installed only. If you want to boot from NAND this is a good guide for updating u-boot and flashing the kernel and example filesystem. <a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Updating_devkit_to_latest_MDK">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Updating_devkit_to_latest_MDK</a></p>
<p>Note the SOM can also be booted from sd card. See <a class="wiki-page" href="http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Linux_Root_File_System">Linux_Root_File_System</a> for different ways the SOM can be booted.</p>
<blockquote>
<p>2. I tried running code to print hello world, its getting executed, but when i tried uart-echo code from the examples provided by mitydsp its not getting debugged. When i contacted with TI, they responded like gel file some error is there. Can i get the proper gel file.</p>
</blockquote>
<p>Are you running barebones code? Can you link to the guide your following?</p>
<blockquote>
<p>3. I am able to see only the L1D memory, is there any way to see the flash memory using ccs.</p>
</blockquote>
<p>The NOR flash is attached over SPI so there is no direct memory map for it. The NAND memory is attached over the EMIFA parrallel bus and there is no direct memory map either. I'm not familiar enough with using CCS to program this processor barebones, I usually use Linux. But I can ask around here if thats something your trying to do.</p>
<blockquote>
<p>4. can i access both ARM and DSP through JTAG without a linux environment.</p>
</blockquote>
<p>Yes</p>
<p>Note we do have a <a class="wiki-page" href="http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/StarterWare">StarterWare</a> barebones guide written a few years back</p>
Software Development: MityDSPL138
http://support.criticallink.com/redmine/boards/10/topics/5821
2019-06-04T07:16:41Z
VIDYA J
<p>For my project i want to do inter process communication on omapl138. Please reply for my below doubts<br />1. Is there Linux on board of MITYDSPL138-FX 225 RC, or is it something which i should do ?<br />2. I tried running code to print hello world, its getting executed, but when i tried uart-echo code from the examples provided by mitydsp its not getting debugged. When i contacted with TI, they responded like gel file some error is there. Can i get the proper gel file.<br />3. I am able to see only the L1D memory, is there any way to see the flash memory using ccs.<br />4. can i access both ARM and DSP through JTAG without a linux environment.</p>
Software Development: uPP channel B in receives mode missing data from FPGA
http://support.criticallink.com/redmine/boards/10/topics/5820
2019-05-28T09:10:40Z
Vivek Ponnani
vivek_p78@live.com
<p>Hi,</p>
<p>I have a custom board with <br />-- MityDspl-138F module (with FPGA)<br />-- No Ethernet port<br />-- UART,USB,SD CARD interface</p>
<p>we have done following steps till date.</p>
<p>-- I have built VM with MityDSP Critical_Link_Unified_VM_14-04_04-2017.ova file from critical link.<br />-- I have successfully run the example programs.<br />-- I have build new kernel with Analog Expansion support. We followed <a class="external" href="https://support.criticallink.com/redmine/projects/90-000173/wiki">https://support.criticallink.com/redmine/projects/90-000173/wiki</a> for the build of new kernel.<br />-- We have developed application in which DSP gets modulated data from ADC via FPGA interface. All the process is done in DSP and we are able to get demodulated output.<br /> In this process FPGA reads data at 40MHz from ADC and sends data to uPP at 50 Mhz clock rate. everything is working fine.<br />-- Now we want to add extra features in DSP but we are not able to add as DSP doesn't have time to do all the task. So, we have transferred half of our job to FPGA side. Now <br /> uPP will get data at 5 MHz clock rate. In this case, we are missing data from FPGA. I have implemented 3 buffers to get data from uPP with ping-pong buffer technique.My <br /> each buffer size is 128*16. Will uPP work at 5 MHz frequency in receive mode? Becuse when we send data from FPGA with uPP clock rate of 12.5 MHz , we are missing less data <br /> compare to 5 MHz clock rate. I have kept DMA receive thread priority 15, which is highest. What could be the reasons of missing data from FPGA to uPP? Please suggest.</p>
<p>Thanks,<br />Vivek Ponnani.</p>
Software Development: RE: Cannot install the GCC Toolchain for Angström
http://support.criticallink.com/redmine/boards/10/topics/5409?r=5808#message-5808
2019-04-29T14:32:04Z
Jonathan Cormier
jcormier@criticallink.com
<p>VIDYA J wrote:</p>
<blockquote>
<p>I am also facing same problem, ./usr/local/oecore-i686/environment-setup-armv5te-angstrom-linux-gnueabi, is not giving any response</p>
</blockquote>
<p>Please try <code>source /usr/local/oecore-i686/environment-setup-armv5te-angstrom-linux-gnueabi</code></p>
<p>Note this doesn't print anything when you run it.</p>
Software Development: RE: Cannot install the GCC Toolchain for Angström
http://support.criticallink.com/redmine/boards/10/topics/5409?r=5807#message-5807
2019-04-27T06:49:25Z
VIDYA J
<p>I am also facing same problem, ./usr/local/oecore-i686/environment-setup-armv5te-angstrom-linux-gnueabi, is not giving any response</p>
Software Development: RE: UPP problem
http://support.criticallink.com/redmine/boards/10/topics/4201?r=5806#message-5806
2019-04-16T13:19:15Z
Jonathan Cormier
jcormier@criticallink.com
<p>Thanks for bringing this up again. We'll look into it.</p>
Software Development: RE: UPP problem
http://support.criticallink.com/redmine/boards/10/topics/4201?r=5805#message-5805
2019-04-13T12:51:15Z
Douglas Gomes
<p>+1. Just wanted to give attention to this solution, which also solved a 2-day problem that I was having when receiving values. <br />The values read from the buffers were never updated until I did the invalidation of the cache.</p>
Software Development: RE: Latest MityDSP-L138 U-Boot image
http://support.criticallink.com/redmine/boards/10/topics/5800?r=5804#message-5804
2019-04-10T11:08:28Z
Mathew Jones
<p>Thanks, that's great.</p>
Software Development: RE: Latest MityDSP-L138 U-Boot image
http://support.criticallink.com/redmine/boards/10/topics/5800?r=5803#message-5803
2019-04-09T16:02:03Z
Federico Rueda
<p>Hi Mathew,</p>
<p>Jon spoke to me about building the files for you. I've attached the files you were asking for.</p>
Software Development: RE: Latest MityDSP-L138 U-Boot image
http://support.criticallink.com/redmine/boards/10/topics/5800?r=5802#message-5802
2019-04-09T14:22:06Z
Mathew Jones
<p>Thanks for that quick info.</p>
<p>I've realised that the u-boot.img file you attached is without the UBL header and so it can't be used for in-field upgrades<br />(but it does work with the Windows Flash programming tool sfh_OMAP_L138.exe).<br />I downloaded and extracted the Release 2018.04, but unlike previous MDKs I could not find the pre-built file <strong>'u-boot-ubl.bin'</strong> (nor u-boot.bin)</p>
<p>Could you attach the file <strong>u-boot-ubl.bin</strong>?</p>
<p>Much appreciated,<br />Mat</p>
Software Development: RE: Latest MityDSP-L138 U-Boot image
http://support.criticallink.com/redmine/boards/10/topics/5800?r=5801#message-5801
2019-04-08T15:29:27Z
Jonathan Cormier
jcormier@criticallink.com
<p>Mathew Jones wrote:</p>
<blockquote>
<p>Hi,<br />As part of investigating the impacts of the 8MB NOR Flash obsolescence and its 16MB replacement (PCN 20180209000),<br />I'd like to be able to re-program the latest U-Boot image back onto any MityDSP-L138 SOM.</p>
<p>Do you have a binary image to download for the version currently being delivered on these SOMs<br />(reported during boot-up as "2009.11-00004-gabfcd69 Jan 03 2018 - 11:30:43") ?</p>
</blockquote>
<p>You can either build the latest u-boot or we do have a yocto based MDK released that has the newer u-boot binary. See the Release 2018.04 in the <a href="https://support.criticallink.com/redmine/projects/arm9-platforms/files" class="external">files section</a></p>
<p>Note: I've attached the u-boot and uImage shipped with that MDK. They should work without having to reflash the filesystem.</p>
<p>This wiki page can help for flashing a newer u-boot.<br /><a class="wiki-page" href="http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Updating_devkit_to_latest_MDK">Updating devkit to latest MDK</a></p>
<blockquote>
<p>Also, is the latest U-Boot image that supports the 16MB NOR Flash backward compatible on MityDSP-L138 SOMs with the older 8MB NOR Flash?</p>
</blockquote>
<p>Yes, u-boot patch added support for detecting newer largers NORs. Older NOR is not effected.<br /><a class="external" href="https://support.criticallink.com/gitweb/?p=u-boot-mitydspl138.git;a=commitdiff;h=abfcd79c2716ab088f61a503ec5a5f0bf3656ca0;hp=4910df7895edccc69726de90e26d1ca6c7600fe4">https://support.criticallink.com/gitweb/?p=u-boot-mitydspl138.git;a=commitdiff;h=abfcd79c2716ab088f61a503ec5a5f0bf3656ca0;hp=4910df7895edccc69726de90e26d1ca6c7600fe4</a></p>
<blockquote>
<p>Thanks<br />Mat</p>
</blockquote>
Software Development: Latest MityDSP-L138 U-Boot image
http://support.criticallink.com/redmine/boards/10/topics/5800
2019-04-08T14:51:00Z
Mathew Jones
<p>Hi,<br />As part of investigating the impacts of the 8MB NOR Flash obsolescence and its 16MB replacement (PCN 20180209000),<br />I'd like to be able to re-program the latest U-Boot image back onto any MityDSP-L138 SOM.</p>
<p>Do you have a binary image to download for the version currently being delivered on these SOMs<br />(reported during boot-up as "2009.11-00004-gabfcd69 Jan 03 2018 - 11:30:43") ?</p>
<p>Also, is the latest U-Boot image that supports the 16MB NOR Flash backward compatible on MityDSP-L138 SOMs with the older 8MB NOR Flash?</p>
<p>Thanks<br />Mat</p>
Software Development: RE: We want to know about SPI for CAN Interface with Linux
http://support.criticallink.com/redmine/boards/10/topics/5787?r=5792#message-5792
2019-02-28T16:45:34Z
Jonathan Cormier
jcormier@criticallink.com
<p>sin-ka kang wrote:</p>
<blockquote>
<p>Thank you for reply.</p>
<p>You said that I don't have to make any nodes with 'mknod' command to me,</p>
<p>but when i want to access to SPI1 to control mcp2515 directly, how can I access to SPI1? like open(/dev/spi1.1); in linux.</p>
</blockquote>
<p>Linux has several mechanisms for creating device node files automatically based on what is configured in the kernel. Its almost always the wrong answer to manually create a device node. udev, mdev, or devtmpfs are different mechanisms linux can use to create device nodes.</p>
<p>If /dev/spi1.1 is missing then there is a good chance the spidev driver in the kernel isn't being correctly configured and manually creating the device node still won't work since there won't be a device driver to connect to.</p>
<p>The following code shows how to configure a spidev device on spi1. <a class="external" href="https://support.criticallink.com/gitweb/?p=linux-davinci.git;a=blob;f=arch/arm/mach-davinci/baseboard-industrialio.c;h=112cbf0f19942494dd521adaf5e8bf411a6a7f3a;hb=refs/heads/mitydsp-linux-v3.2#l333">https://support.criticallink.com/gitweb/?p=linux-davinci.git;a=blob;f=arch/arm/mach-davinci/baseboard-industrialio.c;h=112cbf0f19942494dd521adaf5e8bf411a6a7f3a;hb=refs/heads/mitydsp-linux-v3.2#l333</a></p>
<p>I've attached an example c++ class for interacting with the spidev interface.</p>
Software Development: RE: We want to know about SPI for CAN Interface with Linux
http://support.criticallink.com/redmine/boards/10/topics/5787?r=5791#message-5791
2019-02-27T08:27:47Z
sin-ka kang
<p>Thank you for reply.</p>
<p>You said that I don't have to make any nodes with 'mknod' command to me,</p>
<p>but when i want to access to SPI1 to control mcp2515 directly, how can I access to SPI1? like open(/dev/spi1.1); in linux.</p>
Software Development: RE: We want to know about SPI for CAN Interface with Linux
http://support.criticallink.com/redmine/boards/10/topics/5787?r=5789#message-5789
2019-02-19T20:30:24Z
Bob Duke
bob.duke@criticallink.com
<p>Are you using the latest MDK available under the files tab?</p>
<p><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/files">https://support.criticallink.com/redmine/projects/arm9-platforms/files</a><br />Filename: mitydsp-l138-MDK-gui-2018-04-13.sh</p>
<p>This filesystem has the can-utils installed. This is probably the easiest path for you to interact with <code>can0</code>.</p>
<p>You should not need to make any nodes with the mknod command. The nodes should be automatically created for any device defined in the baseboard file.</p>
Software Development: RE: We want to know about SPI for CAN Interface with Linux
http://support.criticallink.com/redmine/boards/10/topics/5787?r=5788#message-5788
2019-02-18T19:05:09Z
sin-ka kang
<p>In addition, should i make node with 'mknod' command?</p>
Software Development: We want to know about SPI for CAN Interface with Linux
http://support.criticallink.com/redmine/boards/10/topics/5787
2019-02-18T16:25:52Z
sin-ka kang
<p>I sent the following mail to Developers:</p>
<blockquote>
<p>We bought MityDSP-L138F with Industrial IO Board.</p>
<p>We want to use CAN interface(mcp2515) with linux system.</p>
<p>But I don't know how to open spi port in /dev folder. (I can open uart port with '/dev/ttys2')</p>
<p>if you have some example program source for SPI with CAN interface, Could you send me some example sources?</p>
<p>in addition, if there is another proceed before making program, I will really appreciate for your additional information about setting.</p>
</blockquote>
<p>And I got a following Answer:</p>
<blockquote>
<p>The mcp251x driver is already in the kernel and you should be able to access the CAN device via can0. Have you reviewed our wiki page which discusses CAN support? <<a class="external" href="https://support.criticallink.com/redmine/projects/indio/wiki/CAN_support">https://support.criticallink.com/redmine/projects/indio/wiki/CAN_support</a>><br />Regarding SPI, you will need to make sure all of the pinmuxes are set for the pins in question, and then update the spi device initialization tables. If you want to use spidev (to control your devices in userspace), then you'll need to add an entry for spidev in the spi device initialization tables for each chip select entry. There should be some examples of spidev in some of the other baseboard-*.c files you should be able to reference.</p>
</blockquote>
<p>Thank you for your reply.</p>
<p>At first, I found wiki page which discusses CAN support <<a class="external" href="https://support.criticallink.com/redmine/projects/indio/wiki/CAN_support">https://support.criticallink.com/redmine/projects/indio/wiki/CAN_support</a>> already, but I cannot install 'can-utils' and 'iproute2' packages in MityDSP terminal window. I think the problem is feed server, but i don't know how can I modify feed server. so I can't test can0 in MityDSP-L138F board yet.</p>
<p>And, He told me about 'baseboard-*.c' and i found a 'baseboard-industrilio.c', but i think it is not useful for connect spi(CAN) in MityDSP(Industrial IO), but when i want to use SPI in my custom board.</p>
<p>how can i code my source to connect SPI / mcp2515?</p>
<p>in addition, When i want to connect to UART2, Does it work well "open(/dev/ttys2)" ?</p>
<p>Thank you for reading.</p>
Software Development: RE: Double boot u-Boot
http://support.criticallink.com/redmine/boards/10/topics/5763?r=5770#message-5770
2018-11-28T07:36:57Z
Oleh Mela
oleh.mela@gmail.com
<p>Thank Jonathan,</p>
<p>The problem is resolved. The problem was in hardware.</p>
Software Development: RE: Double boot u-Boot
http://support.criticallink.com/redmine/boards/10/topics/5763?r=5769#message-5769
2018-11-21T14:35:27Z
Jonathan Cormier
jcormier@criticallink.com
<p>Oleh Mela wrote:</p>
<blockquote>
<p>Jonathan,<br />Could be my problem connected with to the that there is no pull-up on SPI1 on the own carrier board?</p>
<p>Thanks</p>
</blockquote>
<p>Looking at our devkit, we don't put any pull-ups on the spi1 pins. <a class="external" href="https://support.criticallink.com/redmine/attachments/download/15416/80-000268RI-3_SCH_RevC.PDF">https://support.criticallink.com/redmine/attachments/download/15416/80-000268RI-3_SCH_RevC.PDF</a></p>
Software Development: RE: Double boot u-Boot
http://support.criticallink.com/redmine/boards/10/topics/5763?r=5768#message-5768
2018-11-21T11:08:58Z
Oleh Mela
oleh.mela@gmail.com
<p>Jonathan,<br />Could be my problem connected with to the that there is no pull-up on SPI1 on the own carrier board?</p>
<p>Thanks</p>
Software Development: RE: Double boot u-Boot
http://support.criticallink.com/redmine/boards/10/topics/5763?r=5767#message-5767
2018-11-19T19:44:26Z
Jonathan Cormier
jcormier@criticallink.com
<p>That is very strange. Could you comment out pieces of your code until it starts working again? To see if you can determine a section of the code that causes this and we can look at it to see if we can determine what is going wrong.</p>
Software Development: RE: Double boot u-Boot
http://support.criticallink.com/redmine/boards/10/topics/5763?r=5766#message-5766
2018-11-19T15:17:30Z
Oleh Mela
oleh.mela@gmail.com
<p>Jonathan,<br />with simple hello world dsp program following is:</p>
<p>OMAP-L138/AM-1808/AM-1810 initialization passed!<br />Configuring 128MB mDDR<br /> Booting TI User Boot Loader<br /> UBL Version: 1.65:2.28.1 BuiltJul 11 2011 12:49:53<br /> UBL Flashtype: SPI<br />Starting SPI Memory Copy...<br />Valid magicnum, 0x55424CBB, found at offset 0x00010000.<br /> DONE<br />Jumping to entry point at 0xC1080000.<br />OMAP-L138/AM-1808/AM-1810 initialization passed!<br />Configuring 128MB mDDR<br /> Booting TI User Boot Loader<br /> UBL Version: 1.65:2.28.1 BuiltJul 11 2011 12:49:53<br /> UBL Flashtype: SPI<br />Starting SPI Memory Copy...<br />Valid magicnum, 0x55424CBB, found at offset 0x00010000.<br /> DONE<br />Jumping to entry point at 0xC1080000.</p>
<p>U-Boot 2009.11 (Jan 13 2014 - 11:14:02)</p>
<p>I2C: ready<br />DRAM: 128 MB<br />NAND: 256 MiB<br />MMC: davinci: 0<br />In: serial<br />Out: serial<br />Err: serial<br />ARM Clock : 300000000 Hz<br />DDR Clock : 150000000 Hz<br />EMIFA CLock : 100000000 Hz<br />DSP Clock : 300000000 Hz<br />ASYNC3 Clock : 150000000 Hz<br />Enet config : 2<br />MMC 0 Enable : 0<br />Resetting ethernet phy<br />Net: No ETH PHY detected!!!</p>
<p>Hit any key to stop autoboot: 0<br />8192 KiB M25P64 at 0:0 is now current device<br />Loading coff data from address 0xc0700000<br />... loading 512 bytes to address 0x11811800<br />... loading 17152 bytes to address 0x118058a0<br />... loading 12 bytes to address 0x1180f7f4<br />... loading 22688 bytes to address 0x11800000<br />... loading 4004 bytes to address 0x1180dfc0<br />... loading 76 bytes to address 0x1180f798<br />... loading 1376 bytes to address 0x11810000<br />... loading 12 bytes to address 0x118117f4<br />... loading 4032 bytes to address 0x1180d000<br />... loading 905 bytes to address 0x11810e78<br />... loading 4 bytes to address 0x1180ef64<br />... loading 512 bytes to address 0x11811588<br />... loading 48 bytes to address 0x118117c4<br />... loading 48 bytes to address 0x11811ce8<br />Starting DSP at address 0x11810380<br />U-Boot ></p>
Software Development: RE: Double boot u-Boot
http://support.criticallink.com/redmine/boards/10/topics/5763?r=5765#message-5765
2018-11-19T15:13:31Z
Oleh Mela
oleh.mela@gmail.com
<p>U-Boot > printenv<br />bootargs=mem=96M console=ttyS1,115200n8 root=/dev/mtdblock0 rw rootwait<br />bootdelay=3<br />baudrate=115200<br />bootfile="uImage" <br />flashuboot=tftp 0xc0700000 mityomap/u-boot-ubl.bin; sf probe 0; sf erase 0x10000 0x80000; sf write 0xc0700000 0x10000 ${filesize}<br />flashkernel=tftp 0xc0700000 mityomap/uImage; sf probe 0; sf erase 0x100000 0x280000; sf write 0xc0700000 0x100000 ${filesize}<br />flashubl=tftp 0xc0700000 mityomap/UBL_SPI_MEM.ais; sf probe 0; sf erase 0 0x10000; sf write 0xc0700000 0 0x10000<br />flashrootfs=tftp 0xc2000000 mityomap/mityomap-base-mityomapl138.jffs2; nand erase 0 0x08000000; nand write.jffs2 0xc2000000 0 ${filesize}<br />serverip=10.0.0.23<br />autoload=no<br />mtdids=nand0=nand<br />mtdparts=mtdparts=nand:128M(rootfs),-(userfs)<br />bootargsbase=mem=96M console=ttyS1,115200n8<br />flashargs=setenv bootargs ${bootargsbase} ${mtdparts} root=/dev/mtdblock0 rw,noatime rootfstype=jffs2<br />filesize=1732CC<br />bootcmd=sf probe 0; sf read 0xc0700000 0x100000 0x300000;bootdsp 0xc0700000;<br />stdin=serial<br />stdout=serial<br />stderr=serial<br />ethaddr=00:50:c2:fc:6c:cf<br />ver=U-Boot 2009.11 (Jan 13 2014 - 11:14:02)</p>
<p>Environment size: 1070/65532 bytes</p>
<blockquote><blockquote><blockquote>
<p>Does this processor reset happen when the DSP program isn't automatically loaded?</p>
</blockquote></blockquote></blockquote>
<p>No.</p>
<blockquote><blockquote><blockquote>
<p>Does it happen if you try to load a simple hello world dsp program?</p>
</blockquote></blockquote></blockquote>
<p>No, with simple hello world dsp program working fine.</p>
Software Development: RE: Double boot u-Boot
http://support.criticallink.com/redmine/boards/10/topics/5763?r=5764#message-5764
2018-11-19T14:35:21Z
Jonathan Cormier
jcormier@criticallink.com
<p>Oleh,</p>
<p>Could you provide your u-boot environment? <code>printenv</code></p>
<p>Does this processor reset happen when the DSP program isn't automatically loaded? Does it happen if you try to load a simple hello world dsp program?</p>
Software Development: Double boot u-Boot
http://support.criticallink.com/redmine/boards/10/topics/5763
2018-11-19T11:38:14Z
Oleh Mela
oleh.mela@gmail.com
<p>Hi,</p>
<p>I run myfile.out on the MityDSP-L138 (L138-DX-225-RI) module (not MityDSP-L138F). Linux not use (according to DSP Quick Start). myfile.out is compiled in CCS and works fine. At startup (according to Autoload DSP during boot from SPI NOR) there is a double launch of the u-Boot, and then myfile.out is functioning fine. There was no such problem on the MityDSP-L138F module. <br />Why does this occur? Is it possible to avoid double boot?</p>
<p>OMAP-L138/AM-1808/AM-1810 initialization passed! <---------------- Power on (first boot)<br />Configuring 128MB mDDR<br /> Booting TI User Boot Loader<br /> UBL Version: 1.65:2.28.1 BuiltJul 11 2011 12:49:53<br /> UBL Flashtype: SPI<br />Starting SPI Memory Copy...<br />Valid magicnum, 0x55424CBB, found at offset 0x00010000.<br /> DONE<br />Jumping to entry point at 0xC1080000.</p>
<p>U-Boot 2009.11 (Jan 13 2014 - 11:14:02)</p>
<p>I2C: ready<br />DRAM: 128 MB<br />NAND: 256 MiB<br />MMC: davinci: 0<br />In: serial<br />Out: serial<br />Err: serial<br />ARM Clock : 300000000 Hz<br />DDR Clock : 150000000 Hz<br />EMIFA CLock : 100000000 Hz<br />DSP Clock : 300000000 Hz<br />ASYNC3 Clock : 150000000 Hz<br />Enet config : 2<br />MMC 0 Enable : 0<br />Resetting ethernet phy<br />Net: No ETH PHY detected!!!</p>
<p>Hit any key to stop autoboot: 0<br />8192 KiB M25P64 at 0:0 is now current device<br />Loading coff data from address 0xc0700000<br />... loading 512 bytes to address 0xc62f7c00<br />... loading 21888 bytes to address 0xc62de200<br />... loading 294784 bytes to address 0xc628e280<br />... loading 19540 bytes to address 0xc62e8a68<br />... loading 1284 bytes to address 0xc62f6b20<br />... loading 124 bytes to address 0xc62f8360<br />... loading 1952 bytes to address 0xc62f58e0<br />... loading 12 bytes to address 0xc62f7af4<br />... loading 21218 bytes to address 0xc62e3780<br />... loading 4 bytes to address 0xc628e27c<br />... loading 512 bytes to address 0xc62f7e00<br />... loading 24 bytes to address 0xc62f8578<br />... loading 16 bytes to address 0xc628e26c<br />... loading 1984 bytes to address 0x11808800<br />Starting DSP at address 0xc62f5e60</p>
<p>OMAP-L138/AM-1808/AM-1810 initialization passed! <--------------Second boot<br />Configuring 128MB mDDR<br /> Booting TI User Boot Loader<br /> UBL Version: 1.65:2.28.1 BuiltJul 11 2011 12:49:53<br /> UBL Flashtype: SPI<br />Starting SPI Memory Copy...<br />Valid magicnum, 0x55424CBB, found at offset 0x00010000.<br /> DONE<br />Jumping to entry point at 0xC1080000.</p>
<p>U-Boot 2009.11 (Jan 13 2014 - 11:14:02)</p>
<p>I2C: ready<br />DRAM: 128 MB<br />NAND: 256 MiB<br />MMC: davinci: 0<br />In: serial<br />Out: serial<br />Err: serial<br />ARM Clock : 300000000 Hz<br />DDR Clock : 150000000 Hz<br />EMIFA CLock : 100000000 Hz<br />DSP Clock : 300000000 Hz<br />ASYNC3 Clock : 150000000 Hz<br />Enet config : 2<br />MMC 0 Enable : 0<br />Resetting ethernet phy<br />Net: No ETH PHY detected!!!</p>
<p>Hit any key to stop autoboot: 0<br />8192 KiB M25P64 at 0:0 is now current device<br />Loading coff data from address 0xc0700000<br />... loading 512 bytes to address 0xc62f7c00<br />... loading 21888 bytes to address 0xc62de200<br />... loading 294784 bytes to address 0xc628e280<br />... loading 19540 bytes to address 0xc62e8a68<br />... loading 1284 bytes to address 0xc62f6b20<br />... loading 124 bytes to address 0xc62f8360<br />... loading 1952 bytes to address 0xc62f58e0<br />... loading 12 bytes to address 0xc62f7af4<br />... loading 21218 bytes to address 0xc62e3780<br />... loading 4 bytes to address 0xc628e27c<br />... loading 512 bytes to address 0xc62f7e00<br />... loading 24 bytes to address 0xc62f8578<br />... loading 16 bytes to address 0xc628e26c<br />... loading 1984 bytes to address 0x11808800<br />Starting DSP at address 0xc62f5e60 <----------------- Fine working<br />U-Boot ></p>