MityDSP-L138 (ARM9 Based Platforms): FPGA Developmenthttp://support.criticallink.com/redmine/http://support.criticallink.com/redmine/redmine/favicon.ico?16338348402019-07-08T14:57:47ZCritical Link Support
Redmine FPGA Development: Reference Project AnalogExpansionSuite queryhttp://support.criticallink.com/redmine/boards/12/topics/58402019-07-08T14:57:47ZVivek Ponnanivivek_p78@live.com
<p>Hi,</p>
<p>I have a custom board with <br />-- MityDspl-138F module (with FPGA)<br />-- No Ethernet port<br />-- UART,USB,SD CARD interface<br />-- ADC5560 and DAC5672 is used.</p>
<p>we have done following steps till date.</p>
<p>-- I have built VM with MityDSP Critical_Link_Unified_VM_14-04_04-2017.ova file from critical link.<br />-- I have successfully run the example programs.<br />-- I have build new kernel with Analog Expansion support. We followed <a class="external" href="https://support.criticallink.com/redmine/projects/90-000173/wiki">https://support.criticallink.com/redmine/projects/90-000173/wiki</a> for the build of new kernel.<br />-- We have developed application in which DSP gets modulated data from ADC via FPGA interface. All the process is done in DSP and we are able to get demodulated output.<br />In this process FPGA reads data at 40MHz from ADC and sends data to uPP at 50 Mhz clock rate. everything is working fine.<br />Now, we need to change the clocks in FPGA, as we need to do some processes in FPGA.<br />In FPGA program which is the reference program from AnalogExpansionSuite (from Critical Link), we have one doubt from the comment of UPP interface in IndustrialIO_top file.<br />We are using ADS5560 with 40MSPS. <br />There is a component declaration for ADS5560 as below<br />component ads5560<br /> Port ( <br /> clk : in std_logic;<br /> i_ABus : in std_logic_vector(5 downto 0);<br /> i_DBus : in std_logic_vector(15 downto 0);<br /> o_DBus : out std_logic_vector(15 downto 0);<br /> i_wr_en : in std_logic;<br /> i_rd_en : in std_logic;<br /> i_cs : in std_logic;<br /> o_irq : out std_logic := '0';<br /> i_ilevel : in std_logic_vector(1 downto 0) := "00"; <br /> i_ivector : in std_logic_vector(3 downto 0) := "0000"; </p>
<pre><code>-- ADC interface<br /> i_adc_in_p : in std_logic_vector(7 downto 0); -- DDR inputs<br /> i_adc_in_n : in std_logic_vector(7 downto 0); -- DDR inputs<br /> i_adc_clk_p : in std_logic;<br /> i_adc_clk_n : in std_logic;<br /> i_adc_ovr : in std_logic;<br /> o_adc_clk : out std_logic;</code></pre>
<pre><code>-- UPP interface<br /> <strong>i_upp_clock : in std_logic; -- from fabric, minimum 40 MHz</strong><br /> o_upp_clock : out std_logic;<br /> o_upp_d : out std_logic_vector(15 downto 0);<br /> o_upp_enable : out std_logic;<br /> o_upp_start : out std_logic;<br /> i_upp_wait : in std_logic</code></pre>
<pre><code>);<br />end component;<br /><strong>The i_upp_clock signal is commented with the statement that from fabric, minimum 40 MHz</strong><br />What does it mean? It means the clock we assign to i_upp_clock should always be more than 40 MHz? <br />In example code from AnalogExpansionSuite , we understand that i_upp_clock is set to 50MHz which is from CLKDV of DCM_SP module. And this i_upp_clock is given to the uPP channel B of DSP. Channel B of uPP is set in receive mode in DSP. So, uPP of DSP gets clock of 50 MHz from FPGA. So, finally in FPGA, It writes data in FIFO at 40 MHz and reads data from FIFO at 50 MHz.<br />As per comment </code></pre>
<pre><code><strong>i_upp_clock : in std_logic; -- from fabric, minimum 40 MHz</strong></code></pre>
<p>we can not assign i_upp_clock below 40 MHz. That means we can not give uPP clock below 40 MHz? Is it so? Please clarify.</p>
<p>Thanks,<br />Vivek Ponnani</p> FPGA Development: RE: FPGA GPIO issuehttp://support.criticallink.com/redmine/boards/12/topics/5660?r=5666#message-56662018-05-21T15:56:19ZJonathan Cormierjcormier@criticallink.com
<p>Okay thanks Tom. I put that link in the wiki page to hopefully help people in the future.</p> FPGA Development: RE: FPGA GPIO issuehttp://support.criticallink.com/redmine/boards/12/topics/5660?r=5664#message-56642018-05-16T15:15:00ZTom Riddle
<p>Hi Jonathan,</p>
<p>Here's the link</p>
<p><a class="external" href="https://support.criticallink.com/redmine/boards/12/topics/2224">https://support.criticallink.com/redmine/boards/12/topics/2224</a></p>
<p>It's been a few years since my last FPGA project, so I was a bit rusty. What I benefited from most was looking at that posted source example and how it was modified. The wiki (which is good overall) has this... so an example of what is "proper" is what I needed <img src="/redmine/plugin_assets/redmine_wiki_extensions/images/smile.png" alt=":)"></p>
<p>-----<br />An FPGA image with Critical Link's GPIO core built in properly.</p>
<pre><code>See $MDK/examples/industrial_io/fpga/vhdl/IndustrialIO_top.vhd for an example of proper core usage.<br /> Note: Make sure that the GPIO core you add to your project has the IRQ level selected to match ARM usage so that core is enumerated by Linux (IRQ Level = 0 for a core should make Linux enumerate the core by default).<br />-----</code></pre>
<p>So I've been working with the ISE project "build_dvi_rev_c", and initially made no modifications. It wasn't clear to me initially how to enable the GPIO core or what specific IndustrialIO_top.vhd modifications were needed to get it going (plus I'm really a verilog guy). Just running the base ISE example will yield the error of the missing gpiochip144. Anyway it's fairly obvious, but that along with the vhd example changes, the UCF file needs to be updated accordingly. Regs, Tom</p> FPGA Development: RE: FPGA GPIO issuehttp://support.criticallink.com/redmine/boards/12/topics/5660?r=5663#message-56632018-05-16T13:16:48ZJonathan Cormierjcormier@criticallink.com
<p>Can you link to the post? It may help me update the wiki page.</p> FPGA Development: RE: FPGA GPIO issuehttp://support.criticallink.com/redmine/boards/12/topics/5660?r=5662#message-56622018-05-16T00:05:18ZTom Riddle
<p>Hi Jonathan, thanks for the info... So I followed an example from a post a few years back (FPGA GPIO: toggle problem) and was able to get the GPIO going.</p>
<p>Regs, Tom</p> FPGA Development: RE: FPGA GPIO issuehttp://support.criticallink.com/redmine/boards/12/topics/5660?r=5661#message-56612018-05-15T15:23:25ZJonathan Cormierjcormier@criticallink.com
<p>The fpga can connect the gpio core to any pin you want. Gpio 144 should map to the first gpio core pin in the fpga image.</p>
<p>The .ucf file is used to map processor pins to net names in the vhdl.</p>
<p>MDK_2014-01-13/examples/industrial_io/fpga/vhdl/IndustrialIO_rev_C.ucf<br /><pre>
NET "o_diode<0>" LOC = "H14" | IOSTANDARD = LVCMOS33; # J702-7 32_N
NET "o_diode<1>" LOC = "E13" | IOSTANDARD = LVCMOS33; # J702-15 24_N
</pre></p>
<p>And the vhd will connect the net names to the gpio core.</p>
<p>MDK_2014-01-13/examples/industrial_io/fpga/vhdl/IndustrialIO_top.vhd<br /><pre>
gpio1 : gpio^M
generic map (^M
NUM_BANKS => 1,^M
NUM_IO_PER_BANK => 2^M
)^M
Port Map (^M
clk => ema_clk,^M
i_ABus => addr_r,^M
i_DBus => edi_r,^M
o_DBus => edo_arm(CORE_GPIO_MODULE),^M
i_wr_en => wr_r,^M
i_rd_en => rd_r,^M
i_cs => arm_cs5_r(CORE_GPIO_MODULE),^M
o_irq => irq_map(CORE_GPIO_IRQ_LEVEL)(CORE_GPIO_IRQ_VECTOR),^M
i_ilevel => conv_std_logic_vector(CORE_GPIO_IRQ_LEVEL, 2), ^M
i_ivector => conv_std_logic_vector(CORE_GPIO_IRQ_VECTOR, 4), ^M
i_io => "00",^M
t_io => open,^M
o_io => o_diode,^M
i_initdir => "11",^M
i_initoutval => "11" ^M
);^M
</pre></p>
<p>There is also a spreadsheet at MDK_2014-01-13/fpga/vhdl/OMAP-L138toFPGA.xlsx which maps the FPGA pin names to the SOMs pin names.</p> FPGA Development: FPGA GPIO issuehttp://support.criticallink.com/redmine/boards/12/topics/56602018-05-15T01:45:15ZTom Riddle
<p>Hi,</p>
<p>I am attempting to get some FPGA GPIO control going with an L138/LX45 IndustrialIO board. Have been following these instructions</p>
<p><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Core_Device_Drivers">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Core_Device_Drivers</a></p>
<p>The fpga gets programmed, kernel modules loaded and the fpga image version is "PROGRAMMED, Base Module version 01:01". However, looking at the /sys/class/gpio there is no gpiochip144 as outlined in the instructions</p>
<p>Change directory to /sys/class/gpio</p>
<pre><code>In addition to gpiochip0, gpiochip32, ..., gpiochip128, you should see gpiochip144.<br /> The FPGA GPIO Core pins start at pin #144 on the Linux side of things.</code></pre>
<p>Also how does one map the physical pins on the expansion connectors to the GPIO control #? For example on J702, pin 23 is "FPGA_IO_43_N" how does that map to the kernel gpio number if FPGA enumeration starts at 144?</p>
<p>Thanks, Tom</p> FPGA Development: RE: FPGA Done led not turning on with CPU programminghttp://support.criticallink.com/redmine/boards/12/topics/5603?r=5621#message-56212018-02-06T10:14:35ZVivek Ponnanivivek_p78@live.com
<p>Michael Williamson wrote:</p>
<blockquote>
<p>How are you generating the bin file?</p>
<p>Check this <a href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Overview" class="external">wiki page</a>. At the bottom there is a command for generation.</p>
<p>-Mike</p>
</blockquote>
<p>Thanks a lot Michael. There was a problem in .bin file generation. We followed your suggested wiki page and now it is working.</p>
<p>Thanks.<br />- Vivek</p> FPGA Development: RE: FPGA Done led not turning on with CPU programminghttp://support.criticallink.com/redmine/boards/12/topics/5603?r=5604#message-56042018-01-31T14:42:41ZMichael Williamson
<p>How are you generating the bin file?</p>
<p>Check this <a href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Overview" class="external">wiki page</a>. At the bottom there is a command for generation.</p>
<p>-Mike</p> FPGA Development: FPGA Done led not turning on with CPU programminghttp://support.criticallink.com/redmine/boards/12/topics/56032018-01-31T14:04:45ZVivek Ponnanivivek_p78@live.com
<p>Hi,<br />We have made our own customized board uing the Industrial IO Board and the Analog expansion board.</p>
<p>We were programming the FPGA (x16) using the JTAG programmer. We used to have the Done LED turned ON once the programming was done. Using the JTAG programmer we were downloading the .bit file.</p>
<p>Now we are trying to load FPGA via CPU. We are following the link:<br />"https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA"</p>
<p>1. When we program the FPGA with the IndustrialIO_top_aexp.bin file provided in the Analog Expansion Suite, we again have the FGPA Done LED turned ON. The set of steps and response is as below</p>
<p>_U-Boot >loadb 0xC0700000<br />Ready for binary (kermit) download to 0xC0700000 at 115200 bps...<br />Total Size = 0x00071544 = 464196 Bytes<br />Start Addr = 0xC0700000</p>
<p>uBoot> sf probe 0<br />uBoot> sf erase 0x580000 0x80000<br />uBoot> sf write 0xC0700000 0x580000 0x00071544</p>
<p>uBoot> sf probe 0<br />uBoot> sf read 0xc0700000 0x580000 0x80000<br />uBoot> loadfpga 0xc0700000</p>
<p>Loading FPGA from 0xC0700000 with 0x80000 bytes<br />Loading FPGA done<br />Found Device ID 00-Base Module (01.01) at 66000000 [0]<br />Found Device ID 04-GPIO (01.03) at 66000080 [1]<br />Found Device ID 14-SPI Interface (02.01) at 66000100 [2]<br />Found Device ID 255-Unknown (01.00) at 66000180 [3]_</p>
<p>2. We used the <strong>IndustrialIO.xise</strong> from the Analog Expansion suite and created our own project. We were able to add relevant source files and compile our project. We are able to program the .bit file generated successfully through JTAG. The program runs fine with FPGA LED turned ON.</p>
<p>Now we try to load the associated .bin file of our project via CPU (following the steps as per "https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA") we get the following response:</p>
_Hit any key to stop autoboot: 0<br />U-Boot > loadb 0xC0700000
<ol>
<li>Ready for binary (kermit) download to 0xC0700000 at 115200 bps...</li>
<li>Total Size = 0x00071544 = 464196 Bytes</li>
<li>Start Addr = 0xC0700000<br />U-Boot ><br />U-Boot > sf probe 0<br />8192 KiB M25P64 at 0:0 is now current device<br />U-Boot > sf erase 0x580000 0x80000<br />U-Boot > sf write 0xC0700000 0x580000 0x00071544<br />U-Boot > sf probe 0<br />8192 KiB M25P64 at 0:0 is now current device<br />U-Boot > sf read 0xc0700000 0x580000 0x80000<br />U-Boot > loadfpga 0xc0700000<br />Loading FPGA from 0xC0700000 with 0x80000 bytes<br />Loading FPGA done_</li>
</ol>
<p>We find that the FPGA Done LED does not turn ON and we do not get the following response:</p>
<p><em>Found Device ID 00-Base Module (01.01) at 66000000 [0]<br />Found Device ID 04-GPIO (01.03) at 66000080 [1]<br />Found Device ID 14-SPI Interface (02.01) at 66000100 [2]<br />Found Device ID 255-Unknown (01.00) at 66000180 [3]</em></p>
<p>It seems we are missing the Device ID settings some where in VHDL programming. Kinldy suggest the solution for the above problem.</p>
<p>Thanks and Regards,<br />Vivek Ponnani</p> FPGA Development: RE: Core Creation Guidelineshttp://support.criticallink.com/redmine/boards/12/topics/2832?r=5552#message-55522017-12-12T23:13:31ZJonathan Cormierjcormier@criticallink.com
<p>Jorden Luke wrote:</p>
<blockquote>
<p>I am trying to get some help with this one as well. Is there are up date to this one?</p>
</blockquote>
<p>It doesn't look like we ever created that guide. I'd recommend looking at the provided source files as examples.</p>
<p>examples/industrial_io/fpga/vhdl/IndustrialIO_top.vhd<br />This file is an example top level vhdl file which connects the different cores together.</p>
<p>fpga/vhdl/gpio.vhd<br />This is the vhdl for our gpio fpga core.</p>
<p>sw/ARM/linux/drivers/fpga/fpga_gpio.c<br />This is the linux driver for the gpio fpga core.</p> FPGA Development: RE: Core Creation Guidelineshttp://support.criticallink.com/redmine/boards/12/topics/2832?r=5551#message-55512017-12-12T18:52:14ZJorden Luke
<p>I am trying to get some help with this one as well. Is there are up date to this one?</p> FPGA Development: RE: Alternate GPIO Controlhttp://support.criticallink.com/redmine/boards/12/topics/5538?r=5540#message-55402017-11-29T22:06:52ZTom Riddle
<p>Greq, good point WRT the inouts... thanks for bringing it up. In our case they were going to be dedicated outputs. Either way it's great that CL supplies those cores, no doubt they will be utilized. Regs, Tom</p> FPGA Development: RE: Alternate GPIO Controlhttp://support.criticallink.com/redmine/boards/12/topics/5538?r=5539#message-55392017-11-29T21:39:21ZGregory Gluszek
<p>Hi Tom,</p>
<p>One concern I have regarding your proposed approach would be the case of your GPIOs needing to be run-time configured as inputs or outputs. Configuring your FPGA passthrough ports to be inouts may be sufficient, but you may also need some logic in the FPGA to indicate the direction of the passthrough. Of course if your GPIOs are always going to be inputs or outputs this will not be an issue.</p>
<p>Another option would be to add an instance of Critical Link's gpio vhdl core to your FPGA and connect it to the FPGA pins you want to use as GPIOs. The fpga_gpio Linux driver that interfaces with this core will allow you to control the GPIOs from the ARM via Linux in the same manner as any other Linux GPIO. Similarly the DspFpgaGpio DSP core library class would allow you to control these GPIOs from the DSP.</p>
<p>Let me know if you have any questions.</p>
<p>Thanks,<br />\Greg</p> FPGA Development: Alternate GPIO Controlhttp://support.criticallink.com/redmine/boards/12/topics/55382017-11-29T19:23:49ZTom Riddle
<p>Hi,</p>
<p>Direct GPIO control from the L138 is pretty nice to have. In our current task we need a number of GPIOs, more then what is available on the expansion connections when considering the other L138 functions we are using. The ability to use the Critical Link GPIO FPGA core is, of course an option.</p>
<p>So of the interfaces between the L138 and the FPGA, we only plan on using EMIFA and the uPP. With UHPI, MMCSD1, LCD and VPIF not utilized, the pin-mux tool shows a number of GPIOs in groups GP6, GP8 pretty much free. So if we configure them as GPIO and implemented a simple signal "pass thru" in the FPGA to the appropriate FPGA_IO pins we'd be good to go? Just wanted to make sure I'm not missing anything obvious with this approach. Thanks, Tom</p> FPGA Development: RE: Example fpga bin filehttp://support.criticallink.com/redmine/boards/12/topics/5444?r=5445#message-54452017-09-29T19:09:51ZTom Riddle
<p>Never mind... I was able to successfully use the bin file out of build_dvi_revc_lx45 to validate with the Impact tool. Thanks</p> FPGA Development: Example fpga bin filehttp://support.criticallink.com/redmine/boards/12/topics/54442017-09-28T17:24:03ZTom Riddle
<p>Hi,</p>
<p>I'm using MDK_2014-01-03 and wanted to just validate the FPGA programming mechanisms outlined in the wiki. Is there a generic .bin file available to test with or do I have to build one from the examples? Thanks, Tom</p> FPGA Development: RE: L138F breakout adapter pinouthttp://support.criticallink.com/redmine/boards/12/topics/5436?r=5439#message-54392017-09-26T20:15:45ZTom Riddle
<p>Alex, thanks... Regs, Tom</p> FPGA Development: RE: L138F breakout adapter pinouthttp://support.criticallink.com/redmine/boards/12/topics/5436?r=5438#message-54382017-09-26T19:22:33ZAlexander Blockalex.block@criticallink.com
<p>Tom,</p>
<p>You can find the pin-out of the JTAG adapter board in the datasheet for the board (<a class="external" href="http://www.criticallink.com/wp-content/uploads/80-000286_L138_Debug_Adapter.pdf">http://www.criticallink.com/wp-content/uploads/80-000286_L138_Debug_Adapter.pdf</a>).</p>
<p>Please let us know if you need anything else,</p>
<p>Alex</p> FPGA Development: L138F breakout adapter pinouthttp://support.criticallink.com/redmine/boards/12/topics/54362017-09-26T15:13:17ZTom Riddle
<p>Hi,</p>
<p>Can someone point me to the docs that outline the pin assignments for the 2 user connectors on the emulator adapter board -- Critical Link (CL) part number 80-000286.</p>
<p>Thanks, Tom</p> FPGA Development: RE: FPGA coding and programming for customized board using Mity DSP L138Fhttp://support.criticallink.com/redmine/boards/12/topics/5355?r=5372#message-53722017-07-18T12:02:44ZVivek Ponnanivivek_p78@live.com
<p>we are using ADS5560 of the analog expansion board through FPGA. We are using CLK and Data through FPGA to connect to uPP interface of the OMAP-L138.<br />We are using example program from the analog expansion suite.<br />How can we debug/check that we have received data from FPGA?<br />Which .ko files(MDK_2014-01-13\fs\mityomap-full\lib\modules\3.2.0\extra) related to FPGA are to be inserted using the insmod command on the board?</p>
<p>Also please revert back to my query put forward earlier on June 30 2017.</p>
<p>Thanks in advance for your support.<br />Vivek Ponnani</p> FPGA Development: FPGA coding and programming for customized board using Mity DSP L138Fhttp://support.criticallink.com/redmine/boards/12/topics/53552017-06-30T13:23:22ZVivek Ponnanivivek_p78@live.com
<p>We have made our own customized board using the Industrial IO board as well as the Analog Expansion board. We have the schematics attached herewith.</p>
<p>We are also attaching the entire FPGA package project (Mity_DSP_Analog.rar) so that it can be reviewed. We have not changed any pins between the ADC and DAC interface to the FPGA. Is it possible that somebody can review the package and let us know if there are any concerns and suggestions?</p>
<p>Secondly I did try to program the FPGA using the Xilinx tool (Platform Cable USB II). I initialized the chain using the IMPACT tool. The tools shows me only one Xilinx device connected. The tool then also shows a pop-up of an SPI device that seems to be associated with the FPGA. I am presently moving forward by saying no to program the SPI device.</p>
<p>Since we are a newbie to FPGA coding and programming, we would like to be guided for the same.</p>
<p>Thanks in advance for support.</p> FPGA Development: RE: FPGA pins in Mity DSP L138Fhttp://support.criticallink.com/redmine/boards/12/topics/5211?r=5222#message-52222017-04-11T03:35:30ZShalini K
<p>Hello,</p>
<p>Thank you, that was what I was looking at.</p>
<p>With Regards<br />Shalini</p> FPGA Development: RE: FPGA pins in Mity DSP L138Fhttp://support.criticallink.com/redmine/boards/12/topics/5211?r=5220#message-52202017-04-10T14:12:13ZJonathan Cormierjcormier@criticallink.com
<p>I think your looking for the carrier board design guide. <a class="external" href="http://www.criticallink.com/wp-content/uploads/2014/01/MityDSP-L138F-Carrier-Board-Design-Guide.pdf">http://www.criticallink.com/wp-content/uploads/2014/01/MityDSP-L138F-Carrier-Board-Design-Guide.pdf</a>. Specifically section "3.4 Omap-L138 Pin-out."</p> FPGA Development: RE: FPGA pins in Mity DSP L138Fhttp://support.criticallink.com/redmine/boards/12/topics/5211?r=5219#message-52192017-04-10T09:57:04ZShalini K
<p>Hello,</p>
<p>Sorry for delay in reply..I was on leave for a few days.Thanks for reply. I think this is not the reply I intended for. I would like to know about connections between FPGA and OMAP ie the FPGA and OMAP pins used in mmcsd,emac ,uhpi, upp ,vpif i/o etc used in Figure 1 MityDSP-L138F Block Diagram of datasheet of mity DSP L138F processor card. I want to get details of connection between FPGA and DSP.</p>
<p>With Regards<br />shalini</p> FPGA Development: RE: FPGA pins in Mity DSP L138Fhttp://support.criticallink.com/redmine/boards/12/topics/5211?r=5213#message-52132017-04-05T13:51:46ZAlexander Blockalex.block@criticallink.com
<p>Shalini,</p>
<p>You can find the mapping of MityDSP-L138F pins from the Edge Connector to the specific balls on both the OMAP-L138 processor and Xilinx Spartan 6 FPGA from the module datasheet (<a class="external" href="http://www.criticallink.com/wp-content/uploads/2014/01/MityDSP-L138F_Spec.pdf">http://www.criticallink.com/wp-content/uploads/2014/01/MityDSP-L138F_Spec.pdf</a>). This is located in Table 1 of that document on pages 5 to 7.</p>
<p>The Xilinx Spartan 6 package used on the module is the CSG324 type. Each module variant utilizes one of a few different specific Xilinx part numbers and we would recommend that you refer to the part markings on your specific module to determine which FPGA is installed (i.e. LX16 Industrial Temperature vs LX45 Commercial Temperature, etc.).</p>
<p>I hope this answers your questions but let us know if you need any further assistance,</p>
<p>Alex</p> FPGA Development: FPGA pins in Mity DSP L138Fhttp://support.criticallink.com/redmine/boards/12/topics/52112017-04-05T08:41:01ZShalini K
<p>Hello,</p>
<p>I have been referring to the schematic showing various components in mity DSP L138F. The referred PDF is attached. The bank 0 and bank 1 pins in FPGA are shown in page1. The names given to the FPGA pins are the ones corresponding to the mity kit. How can I relate each pin to the actual pin number like E7,F2,M16 like that given in xilinx ug385? Where can I get more information on this? I am mew to using DSP kits, only familiar with FPGA boards.I am not even getting information on which FPGA package is used in this. Please help me.</p>
<p>Thanks in advance<br />Shalini</p> FPGA Development: RE: Problems building the Kernelhttp://support.criticallink.com/redmine/boards/12/topics/5161?r=5165#message-51652017-02-17T14:00:24ZJonathan Cormierjcormier@criticallink.com
<p>Your right I can't find the u-boot-tools archive anymore.</p>
<p>Luckily the mkimage tool is built by u-boot. So it can be copied to the system so its available in the path.</p>
<p>Instructions partially from <a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Das_U-Boot_Port#Building-u-Boot">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Das_U-Boot_Port#Building-u-Boot</a><br /><pre>
cd ~/projects/
git clone git://support.criticallink.com/home/git/u-boot-mitydspl138.git u-boot-mitydspl138
cd u-boot-mitydspl138
make ARCH=arm CROSS_COMPILE=arm-angstrom-linux-gnueabi- mityomapl138_config
make ARCH=arm CROSS_COMPILE=arm-angstrom-linux-gnueabi-
sudo cp tools/mkimage /usr/bin
</pre></p> FPGA Development: RE: Problems building the Kernelhttp://support.criticallink.com/redmine/boards/12/topics/5161?r=5164#message-51642017-02-17T13:39:54ZHector Bojorquezhector.bojorquez@ge.com
<p>Hi Jonathan,</p>
<p>We followed the instructions in the link, but we continue having problems to get the U-boot-tools package, it updated some other things, but we got this error:</p>
<p><strong>W: Failed to fetch <a class="external" href="http://ppa.launchpad.net/u-boot-tools/ppa/ubuntu/dists/lucid/main/binary-i386/Packages.gz">http://ppa.launchpad.net/u-boot-tools/ppa/ubuntu/dists/lucid/main/binary-i386/Packages.gz</a> 404 Not Found</strong></p>
<p>we disabled the pp.launchpad.net link from the update source manager, but we continue with no success finding the u-boot-tools package.</p>
<p>all the log is attached, <strong>is there an updated version for the ppa.launchpad link?</strong>... it looks that Ubuntu is trying to get the u-boot-tools package through this link</p>
<p>Thanks!</p>
<p>Héctor.</p> FPGA Development: RE: Problems building the Kernelhttp://support.criticallink.com/redmine/boards/12/topics/5161?r=5163#message-51632017-02-17T12:34:33ZJonathan Cormierjcormier@criticallink.com
<p>We are working on releasing new versions of the VM. In the mean time you can change the repos so they point to the "old-releases".<br /><a class="external" href="http://askubuntu.com/questions/91815/how-to-install-software-or-upgrade-from-an-old-unsupported-release?rq=1">http://askubuntu.com/questions/91815/how-to-install-software-or-upgrade-from-an-old-unsupported-release?rq=1</a></p> FPGA Development: Problems building the Kernelhttp://support.criticallink.com/redmine/boards/12/topics/51612017-02-17T12:32:19ZHector Bojorquezhector.bojorquez@ge.com
<p>Hi all,</p>
<p>I´m trying to do the <a href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Core_Device_Drivers#FPGA-GPIO-Core-Example" class="external">FPGA GPIO Core Example</a> <br />In the step #1 "Load an FPGA image with a GPIO core component" it sends to see other guide <a href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Linux_Kernel" class="external">Linux_Kernel</a></p>
<p>So, following the instructions, we are trying to have the previous requirements, this includes a valid version of GCC Toolchain (we already have it), the git tool (already have it), and then the guide indicates that we need to install additional Ubuntu packages, we are working with the Critical Link VM, so we have Ubuntu 10.04 LTS, we have modified the packages list for looking in old releases but, we can´t get the U-boot-tools packages,</p>
<p><strong>I wonder if you have some updated repositories with the u-boot-tools package?</strong> or if you have other suggestions or advice for get this problem solved.</p>
<p>Thanks in advance for your time,</p>
<p>Héctor Bojórquez</p> FPGA Development: MitySOM-1810F PROFIBUS Development kit: Programming uart.ngc file in FPGA Spart...http://support.criticallink.com/redmine/boards/12/topics/51582017-02-15T10:28:47ZJesus Alejandro Alvarez Trejojesusalejandro.alvarez@ge.com
<p>Hello, good day,</p>
<p>I am working with the MitySOM-1810F PROFIBUS Development kit which includes the AM1810 ARM Microprocessor For PROFIBUS and Spartan 6, I would like to implement the UART core for FPGA which is located in:</p>
<p>\fpga\cores\build_spartan6\uart.ngc</p>
<p>Could you tell me step by step the process to programming the fpga with uart.ngc and the output pins that involves the code?<br />Thanks for your time, I will really appreciate your help.</p>
<p>Alex</p> FPGA Development: Communication between AM1810 ARM Microprocessor For PROFIBUS and Spartan 6http://support.criticallink.com/redmine/boards/12/topics/51402017-01-12T11:15:57ZJesus Alejandro Alvarez Trejojesusalejandro.alvarez@ge.com
<p>Hello, Good Day, I have the MitySOM-1810F PROFIBUS Development kit which includes the AM1810 ARM Microprocessor For PROFIBUS and Spartan 6, I would like to know how I can communicate both devices, I mean, what kind of protocol and how implement it, please.<br />Thanks</p> FPGA Development: RE: Communication EGD or ModBus/TCP Coreshttp://support.criticallink.com/redmine/boards/12/topics/4946?r=4962#message-49622016-07-27T17:19:48ZJonathan Cormierjcormier@criticallink.com
<p>Good question, I'm not sure if there are any files on there that specify which version it is. But if nobody has updated it since you bought it then it will be running the older MDK filesystem.</p> FPGA Development: RE: Communication EGD or ModBus/TCP Coreshttp://support.criticallink.com/redmine/boards/12/topics/4946?r=4961#message-49612016-07-27T17:06:20ZHector Bojorquezhector.bojorquez@ge.com
<p>How can I check my currently devkit MDK?</p> FPGA Development: RE: Communication EGD or ModBus/TCP Coreshttp://support.criticallink.com/redmine/boards/12/topics/4946?r=4960#message-49602016-07-27T15:56:55ZJonathan Cormierjcormier@criticallink.com
<p>Looks like you are using the older toolchain which apparently doesn't have the rpl_* support. This post gives some possible solutions.<br /><a class="external" href="https://www.linuxquestions.org/questions/linux-software-2/undefined-reference-to-%60rpl_malloc'-587256/">https://www.linuxquestions.org/questions/linux-software-2/undefined-reference-to-%60rpl_malloc'-587256/</a></p>
<p>However I'd recommend installing the newer "Aug-2012 SDK Tarball" from <a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/GCC_Toolchain">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/GCC_Toolchain</a>. This will ofcourse require you to be running the newer MDK on the L138 since it switches from gcc 4.3.3 to 4.5.4.</p>
<p>You can follow this guide if you need to update to the newest MDK. <a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Updating_devkit_to_latest_MDK">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Updating_devkit_to_latest_MDK</a></p> FPGA Development: RE: Communication EGD or ModBus/TCP Coreshttp://support.criticallink.com/redmine/boards/12/topics/4946?r=4959#message-49592016-07-27T15:34:28ZHector Bojorquezhector.bojorquez@ge.com
<p>Jonathan,</p>
<p>I used the tarball instead of the git, I share you my log, it is different than yours, it is attached.</p>
<p>I can see some Errors. After this Should I be able to compile in Eclipse using the library ?</p>
<p>Thanks,</p>
<p>Hector</p> FPGA Development: RE: Communication EGD or ModBus/TCP Coreshttp://support.criticallink.com/redmine/boards/12/topics/4946?r=4958#message-49582016-07-27T13:43:33ZJonathan Cormierjcormier@criticallink.com
<p>I created a FAQ entry for future reference to building autotools based libraries.<br /><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/ARM_Software_FAQs#Building-library-which-uses-autotools">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/ARM_Software_FAQs#Building-library-which-uses-autotools</a></p> FPGA Development: RE: Communication EGD or ModBus/TCP Coreshttp://support.criticallink.com/redmine/boards/12/topics/4946?r=4957#message-49572016-07-27T13:33:07ZJonathan Cormierjcormier@criticallink.com
<p>Hector Bojorquez wrote:</p>
<blockquote>
<p>I got the error in Eclipse Console messages I have not tried on the MitySOM, I tried the $file command and it looks good<br /><img src="File_Command.PNG" alt="" /></p>
</blockquote>
<p>This shows that the object file your trying to use was built of an intel processor. Not for the ARM L138 processor.</p>
<blockquote>
<p>I want to share you the Library installation log, it is attached, the installation created some folders but the one indicated as the principal is /urs/local/lib in this folder are located the .la and the .so files among others</p>
</blockquote>
<p>The files located in /lib, /usr/lib, and /usr/local/lib are supposed to be compiled for the linux VM. You don't want to run the plain <code>make install</code> when you are cross compiling as it will install the libraries to the linux system.</p>
<blockquote>
<p><img src="Lib_folder.PNG" alt="" /></p>
<p>So I tried to configure project properties in Eclipse, first the Directories<br /><img src="Directories.PNG" alt="" /></p>
<p>Then the libraries<br /><img src="Libraries.PNG" alt="" /></p>
<p>And finally the Miscellaneous<br /><img src="Miscellaneous.PNG" alt="" /></p>
<p>And when I try to build the project I don't get any Error in the "Problems" label in Eclipse, I only get the Building error in the Console log</p>
<p><img src="Console_log.PNG" alt="" /></p>
</blockquote>
<p>It looks like you ran the ./configure without setting it up for the crosscompile. See below. Note if you grabbed the tarball instead of using git then you should be able to skip the git and the autogen.sh command. Also note the --host provided to configure, this should match your cross compiler. Also notice the DESTDIR= added to make install, this ensures the files are copied to the current directory/ARM. See the build log for what gets placed in this ARM folder.</p>
<pre>
git clone git://github.com/stephane/libmodbus
cd libmodbus/
. /usr/local/oecore-i686/environment-setup-armv5te-angstrom-linux-gnueabi
./autogen.sh
./configure --host=arm-angstrom-linux-gnueabi
make
make install DESTDIR=$PWD/ARM
</pre>
<p>See my build log <a class="attachment" href="http://support.criticallink.com/redmine/attachments/11653">libmodbus_build.log</a></p> FPGA Development: RE: Communication EGD or ModBus/TCP Coreshttp://support.criticallink.com/redmine/boards/12/topics/4946?r=4956#message-49562016-07-27T11:58:25ZHector Bojorquezhector.bojorquez@ge.com
<p>I got the error in Eclipse Console messages I have not tried on the MitySOM, I tried the $file command and it looks good<br /><img src="http://support.criticallink.com/redmine/attachments/download/11644/File_Command.PNG" title="Checking compatibility" alt="Checking compatibility" /></p>
<p>I want to share you the Library installation log, it is attached, the installation created some folders but the one indicated as the principal is /urs/local/lib in this folder are located the .la and the .so files among others <br /><img src="http://support.criticallink.com/redmine/attachments/download/11645/Lib_folder.PNG" alt="" /></p>
<p>So I tried to configure project properties in Eclipse, first the Directories<br /><img src="http://support.criticallink.com/redmine/attachments/download/11643/Directories.PNG" title="Conf_Directories" alt="Conf_Directories" /></p>
<p>Then the libraries<br /><img src="http://support.criticallink.com/redmine/attachments/download/11647/Libraries.PNG" alt="" /></p>
<p>And finally the Miscellaneous<br /><img src="http://support.criticallink.com/redmine/attachments/download/11650/Miscellaneous.PNG" alt="" /></p>
<p>And when I try to build the project I don't get any Error in the "Problems" label in Eclipse, I only get the Building error in the Console log</p>
<p><img src="http://support.criticallink.com/redmine/attachments/download/11642/Console_log.PNG" title="Console log -Error- File in wrong format" alt="Console log -Error- File in wrong format" /></p> FPGA Development: RE: Communication EGD or ModBus/TCP Coreshttp://support.criticallink.com/redmine/boards/12/topics/4946?r=4955#message-49552016-07-27T11:03:20ZJonathan Cormierjcormier@criticallink.com
<p>Where did you get this error? When running the program on the L138?</p>
<p>The error usually indicates the object was built for a different architecture or using a different toolchain. You can use the <code>file</code> command to verify if it was properly built. You want to make sure it states ARM and not x86 or x64.</p>
<p>For example<br /><pre>
$ file libpcre.so.0.0.1
libpcre.so.0.0.1: ELF 32-bit LSB shared object, ARM, EABI5 version 1 (SYSV), dynamically linked, stripped
</pre></p>
<p>I don't believe that you should need any special CXXFlAGS, my first step would be to make sure you use the same compiler to build both library and executable.</p>
<p>It would help if you attached your build logs for the library and the app.</p> FPGA Development: RE: Communication EGD or ModBus/TCP Coreshttp://support.criticallink.com/redmine/boards/12/topics/4946?r=4954#message-49542016-07-27T10:47:54ZHector Bojorquezhector.bojorquez@ge.com
<p>Hi,</p>
<p>Well I have <strong>.so</strong> and a <strong>.la</strong> file, the <em>dinamic library</em> and the <em>static library used by the GNU "libtools" package.</em></p>
<p>I tried to add the libmodbus with the .so file to the linker following the wiki for adding dsplink.lib file <a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Hello_World#Compiling-for-the-ARM">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Hello_World#Compiling-for-the-ARM</a></p>
<p>All the <em>"undefined reference to 'modbus...."</em> advices gone, but in the console messages I got " <em><strong>/usr/local/lib/libmodbus.so: could not read symbols: File in wrong format</strong></em> " <a href="http://stackoverflow.com/questions/2527780/c-linker-error-sdl-image-could-not-read-symbols" class="external">In this forum</a> some ones suggest that it maybe is for an incompatibility of 32/64 bit systems</p>
<p>and they suggest to compile the program with a special CXXFLAGS to make it compatible. <strong>Can I make the Building of the project using Terminal commands?</strong> for then, try to apply the suggested solution.</p>
<p>Hector/</p> FPGA Development: RE: Communication EGD or ModBus/TCP Coreshttp://support.criticallink.com/redmine/boards/12/topics/4946?r=4953#message-49532016-07-26T16:41:03ZAlexander Blockalex.block@criticallink.com
<p>Hector,</p>
<p>Concerning the Vivado question:</p>
<p>At this time we do not recommend using Vivado as it does not support the Spartan 6 based devices. We recommend Xilinx ISE 14.X and frankly to begin with you can start with their free webpack versions until you need to implement chipscope or other features of the paid version.</p>
<p><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Overview">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Overview</a></p>
<p>Hope this helps,</p>
<p>Alex</p> FPGA Development: RE: Communication EGD or ModBus/TCP Coreshttp://support.criticallink.com/redmine/boards/12/topics/4946?r=4952#message-49522016-07-26T16:22:54ZJonathan Cormierjcormier@criticallink.com
<p>I would have expected you to get either get a .a or .so file.<br /><a class="external" href="http://stackoverflow.com/a/12237595">http://stackoverflow.com/a/12237595</a></p>
<p><a class="external" href="https://stackoverflow.com/questions/8332460/how-do-i-include-a-statically-linked-library-in-my-eclipse-c-project">https://stackoverflow.com/questions/8332460/how-do-i-include-a-statically-linked-library-in-my-eclipse-c-project</a></p> FPGA Development: RE: Communication EGD or ModBus/TCP Coreshttp://support.criticallink.com/redmine/boards/12/topics/4946?r=4951#message-49512016-07-26T16:16:27ZHector Bojorquezhector.bojorquez@ge.com
<p>I added the library and its path, but I did not get any .lib file after the library installation, Should I have a .lib file?</p>
<p>I only got some "modbus..".h files and one .pc file</p> FPGA Development: RE: Communication EGD or ModBus/TCP Coreshttp://support.criticallink.com/redmine/boards/12/topics/4946?r=4950#message-49502016-07-26T14:59:52ZJonathan Cormierjcormier@criticallink.com
<p>Hector Bojorquez wrote:</p>
<blockquote>
<p>Hi Jonathan and Alex,</p>
<p>It is really helpful information, thank you.</p>
<p>I did not know about libmodbus library, now I'm trying to use it but it looks like the compiler is not linking correctly the modbus library, I added the library path in the Include Directories in Eclipse, but it still</p>
<p>not working, I got an advice about "undefined reference to 'modbus_new_tcp' ", I searched in the Internet and I found a <a href="https://answers.launchpad.net/libmodbus/+question/172535" class="external">Forum post</a> about, they talk about a solution in the Reply #16.</p>
<p><strong>Did you have the same issue?</strong></p>
</blockquote>
<p>Did you add the library to the linker? See the following link for how we add the dsplink.lib file. <a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Hello_World#Compiling-for-the-ARM">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Hello_World#Compiling-for-the-ARM</a></p> FPGA Development: RE: Communication EGD or ModBus/TCP Coreshttp://support.criticallink.com/redmine/boards/12/topics/4946?r=4949#message-49492016-07-26T14:33:58ZHector Bojorquezhector.bojorquez@ge.com
<p>Hi Jonathan and Alex,</p>
<p>It is really helpful information, thank you.</p>
<p>I did not know about libmodbus library, now I'm trying to use it but it looks like the compiler is not linking correctly the modbus library, I added the library path in the Include Directories in Eclipse, but it still</p>
<p>not working, I got an advice about "undefined reference to 'modbus_new_tcp' ", I searched in the Internet and I found a <a href="https://answers.launchpad.net/libmodbus/+question/172535" class="external">Forum post</a> about, they talk about a solution in the Reply #16.</p>
<p><strong>Did you have the same issue?</strong></p>
<p>About the FPGA programming, we are thinking about getting Vivado software, Can you suggest me other options to consider about?</p>
<p>Thanks!</p>
<p>Hector.</p> FPGA Development: RE: Communication EGD or ModBus/TCP Coreshttp://support.criticallink.com/redmine/boards/12/topics/4946?r=4948#message-49482016-07-20T15:21:28ZAlexander Blockalex.block@criticallink.com
<p>Hector,</p>
<p>I spoke with Jon C. about this issue and we have a little more followup.</p>
<p>In the past for the MitySOM/DSP-L138 family of modules we have utilized Modbus/TCP however it was implemented on the ARM processor in Linux using the <a href="http://libmodbus.org/" class="external">libmodbus</a> library. We have done Modbus implementations on other processor platforms as well but never in the FPGA itself. If you have a reason to implement it in the FPGA we unfortunately don't have guidance at this time.</p>
<p>There is a 5 year old Modbus FPGA core from <a href="http://opencores.org/project,modbus" class="external">OpenCores</a> however we have no experience with it.</p>
<p>We have never implemented EGD to my knowledge.</p>
<p>Thank you,</p>
<p>Alex</p> FPGA Development: RE: Communication EGD or ModBus/TCP Coreshttp://support.criticallink.com/redmine/boards/12/topics/4946?r=4947#message-49472016-07-20T10:16:00ZJonathan Cormierjcormier@criticallink.com
<p>Hector Bojorquez wrote:</p>
<blockquote>
<p>Hi,</p>
<p>I'm a beginner with FPGA and embedded systems, now I'm creating a communication between some devices and the MitySOM1810 through EGD and ModBus/TCP communication protocols.</p>
<p>After this stage we are thinking about implementing the communication protocol in the Spartan 6 or if it is possible, a big part of all the application.</p>
<p>If some of you could give me some advices about, it would help me a lot.</p>
<p><strong>1.- Is it possible to implement the ModBus or EGD protocol in the FPGA?</strong></p>
</blockquote>
<p>Most likely it is possible, though i'm only briefly aware of how Modbus works and don't know EGD.</p>
<blockquote>
<p><strong>2.- Are there existing cores for the Spartan 6 that could work with these protocols?</strong></p>
</blockquote>
<p>Don't think we have dealt with any. A brief google search doesn't show much other than this dissertation.<br /><a class="external" href="http://www.dissertationtopic.net/doc/283774">http://www.dissertationtopic.net/doc/283774</a></p>
<blockquote>
<p>Please any comment or advice would help a lot, feel free to sharing me your personal opinions.</p>
<p>Have a great day,</p>
<p>Hector.</p>
</blockquote> FPGA Development: Communication EGD or ModBus/TCP Coreshttp://support.criticallink.com/redmine/boards/12/topics/49462016-07-20T09:42:37ZHector Bojorquezhector.bojorquez@ge.com
<p>Hi,</p>
<p>I'm a beginner with FPGA and embedded systems, now I'm creating a communication between some devices and the MitySOM1810 through EGD and ModBus/TCP communication protocols.</p>
<p>After this stage we are thinking about implementing the communication protocol in the Spartan 6 or if it is possible, a big part of all the application.</p>
<p>If some of you could give me some advices about, it would help me a lot.</p>
<p><strong>1.- Is it possible to implement the ModBus or EGD protocol in the FPGA?</strong></p>
<p><strong>2.- Are there existing cores for the Spartan 6 that could work with these protocols?</strong></p>
<p>Please any comment or advice would help a lot, feel free to sharing me your personal opinions.</p>
<p>Have a great day,</p>
<p>Hector.</p> FPGA Development: RE: Linux application cannot read/write FPGA registershttp://support.criticallink.com/redmine/boards/12/topics/4592?r=4596#message-45962016-01-13T08:52:37ZMathew Jones
<p>Hi Greg<br />Excellent, that has definitely helped as I can now see /dev/0 after the following two commands (with FPGA loaded from uBoot).<br /><pre>
# insmod /lib/modules/$(uname -r)/extra/fpga_ctrl.ko
# echo 3 > /sys/devices/fpga_ctrl/cmd
</pre><br />Now when I run 'mmap_demo' for lcd rev c 'IndustrialIO.bin' I get:<br /><pre>
Beginning mmap demo.
Device DNA: 0x0000000000000000
Found core at 0x4030b000 - ID: 0
Found core at 0x4030b080 - ID: 23
Found core at 0x4030b180 - ID: 2
</pre><br />I can also use 'fpgautil' to write and read from the base core 0 scratch ram area at 0x40-0x7f.</p>
<p>My problems arose because I was relying on uBoot to load the FPGA before Linux is booted, but I wasn't issuing command 3 to the fpga_ctrl driver.<br />Later on I was using the linux driver to load the FPGA but had previously changed 'mmap_demo' & 'fpgautil' to use /dev/mem, instead of /dev/0, which didn't work.</p>
<p>Thanks<br />Mat</p> FPGA Development: RE: Linux application cannot read/write FPGA registershttp://support.criticallink.com/redmine/boards/12/topics/4592?r=4594#message-45942016-01-12T11:35:11ZGregory Gluszek
<p>Hi Matthew,</p>
<p>First we need to deal with the issue of /dev/0 not being present. Using /dev/mem is ultimately not what you want to do as you will run into caching issues.</p>
<p>/dev/0 is created after the FPGA is loaded and the device drives finds the base module. Have you checked that /dev/0 does not exist after you load the FPGA?</p>
<p>Thanks,<br />\Greg</p> FPGA Development: Linux application cannot read/write FPGA registershttp://support.criticallink.com/redmine/boards/12/topics/45922016-01-12T11:16:36ZMathew Jones
<p>I am trying write a simple C application (for Linux on the MityDSP-L138 ARM) that can access registers within an LX16 FPGA image, which is yet to be implemented but I'd like to get the basics working for now with any of the CriticalLink FPGA images.</p>
<p>I want to prove that I can use the mmap mechanism to read/write to the FPGA but so far I've run into some issues.<br />For starters, both the examples 'fpgautil' and 'mmap_demo' try to open "/dev/0", which does not exist in the supplied Jan 2014 kernel/fs. I've changed both examples to access "/dev/mem".<br />'mmap_demo' outputs the following, and does not seem to enumerate any of the core ids as the code suggests:<br /><pre>
Beginning mmap demo.
Device DNA: 0x0000000000000000
</pre><br />For an 'fpgautil' read operation it outputs 0000 for any address I try, but I was expecting to be able to at least read the core ids.</p>
<p>The FPGA images I've tried are: "build_dvi_rev_c/IndustrialIO.bin", "build_lcd_rev_c/IndustrialIO.bin", and <br />also an in-house image. I can read registers from uBoot but not once Linux has started.</p>
<p>I'm using the MityDSP-L138 with LX16 FPGA and the FPGA images are from MDK_2014_01_13.<br />I've tried it when the FPGA is loaded from uBoot (from NAND Flash):<br /><pre>
U-Boot > sf probe 0; sf read 0xc0700000 0x580000 0x170000; loadfpga 0xc0700000 0x170000
8192 KiB M25P64 at 0:0 is now current device
Loading FPGA from 0xC0700000 with 0x170000 bytes
Loading FPGA done
Found Device ID 00-Base Module (01.01) at 66000000 [0]
</pre><br />For "build_lcd_rev_c/IndustrialIO.bin": I get:<br /><pre>
Found Device ID 00-Base Module (01.01) at 66000000 [0]
Found Device ID 23-ADS7843 Touch Screen (01.02) at 66000080 [1]
Found Device ID 02-LCD Settings Controller (01.00) at 66000180 [3]
</pre><br />and from Linux ("build_dvi_rev_c/IndustrialIO.bin"):<br /><pre>
# insmod /lib/modules/$(uname -r)/extra/fpga_ctrl.ko
# echo 1 > /sys/devices/fpga_ctrl/cmd
# echo 2 > /sys/devices/fpga_ctrl/cmd
# cat industrialIO.bin > /sys/devices/fpga_ctrl/image
# echo 3 > /sys/devices/fpga_ctrl/cmd
fpga fpga_ctrl: Found Device ID 00-Base Module (01.01) at C6878000
</pre><br />For "build_lcd_rev_c/IndustrialIO.bin": I get<br /><pre>
fpga fpga_ctrl: Found Device ID 00-Base Module (01.01) at C6878000
fpga fpga_ctrl: Found Device ID 23-ADS7843 Touch Screen (01.02) at C6878080
fpga fpga_ctrl: Found Device ID 02-LCD Settings Controller (01.00) at C6878180
</pre><br />Our Linux version is "3.2.0 #1 PREEMPT Mon Jan 13 11:06:16 EST 2014 armv5tejl GNU/Linux"</p>
<p>I notice that the load addresses(?) are different between uBoot and Linux.<br />Is there anything I'm missing?</p> FPGA Development: RE: Mity L138F FPGA -> OMAP interrupt lineshttp://support.criticallink.com/redmine/boards/12/topics/4198?r=4384#message-43842015-03-25T10:57:09ZChristopher Brunsonchristopher.brunson@nottingham.ac.uk
<p>Hi Alex,</p>
<p>I was using MDK_2012-03-12 and in the included UCF the IO standard on those pin was different:</p>
<p>NET "o_nmi_n" LOC = "N8" | IOSTANDARD = LVCMOS33;<br />NET "o_int<0>" LOC = "K6" | IOSTANDARD = LVCMOS33;<br />NET "o_int<1>" LOC = "F2" | IOSTANDARD = LVCMOS33;</p>
<p>I think the confusion was coming from the fact that I was using an old version of the MDK which had different IO standards setup for those pins.</p>
<p>Thanks,</p>
<p>Chris B.</p> FPGA Development: RE: Mity L138F FPGA -> OMAP interrupt lineshttp://support.criticallink.com/redmine/boards/12/topics/4198?r=4382#message-43822015-03-23T17:08:47ZAlexander Blockalex.block@criticallink.com
<p>Chris,</p>
<p>Hopefully you happened upon this on your own but the details for the pin-configuration, voltage standards, can be found in the sample .ucf files we provide in the MDK BSP (<a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Board_Support_Package">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Board_Support_Package</a>).</p>
<p>From that file:<br /><pre>
NET "o_nmi_n" LOC = "N8" | IOSTANDARD = LVCMOS33 ;
NET "o_int<0>" LOC = "K6" | IOSTANDARD = LVCMOS18;
NET "o_int<1>" LOC = "F2" | IOSTANDARD = LVCMOS18;
</pre></p> FPGA Development: RE: FPGA serial programming interfacehttp://support.criticallink.com/redmine/boards/12/topics/4375?r=4381#message-43812015-03-12T11:06:27ZAlexander Blockalex.block@criticallink.com
<p>We are happy to provide further assistance with this issue, however I will be contacting you directly at your e-mail address that is on-file.</p>
<p>Thank you.</p>
<p>Alex</p> FPGA Development: RE: FPGA serial programming interfacehttp://support.criticallink.com/redmine/boards/12/topics/4375?r=4380#message-43802015-03-11T10:23:59Zstephan bernerstephan.berner@purevlc.com
<p>Thanks for the information.</p>
<p>We are prototyping a future product and due to pin count restrictions we can't use parallel slave mode.</p>
<p>How are the two resistors called, Rxxx and Ryyy ?</p> FPGA Development: RE: FPGA serial programming interfacehttp://support.criticallink.com/redmine/boards/12/topics/4375?r=4379#message-43792015-03-11T10:18:51ZAlexander Blockalex.block@criticallink.com
<p>I discussed this with one of our engineers here and it may be possible however they is likely a bit of work required in order to make it functional.</p>
<p>As well he wanted to know what the reasoning is behind programming the FPGA in the Slave Serial mode vs the current 8-bit parallel?</p>
<p>Thank you.</p> FPGA Development: RE: FPGA serial programming interfacehttp://support.criticallink.com/redmine/boards/12/topics/4375?r=4378#message-43782015-03-11T08:32:54ZAlexander Blockalex.block@criticallink.com
<p>SB,</p>
<p>I apologize.</p>
<p>The M0 and M1 FPGA pins are tied to resistors on the module to GND (M0) and 3.3V (M1) forcing the mode to Slave SelectMAP. The CCLK and DIN connections are tied to the OMAP-L138 processor.</p>
<p>It may be possible to "remove" the M0 and M1 resistors which would allow the internal default pull-up signals to allow the Slave Serial mode to be used (Note 4 - Page 23: <a class="external" href="http://www.xilinx.com/support/documentation/user_guides/ug380.pdf">http://www.xilinx.com/support/documentation/user_guides/ug380.pdf</a>). I will work with some of our engineering staff to see if there are any further considerations.</p>
<p>Alex</p> FPGA Development: RE: FPGA serial programming interfacehttp://support.criticallink.com/redmine/boards/12/topics/4375?r=4377#message-43772015-03-10T17:04:33Zstephan bernerstephan.berner@purevlc.com
<p>I understand that. However, I would like to configure the FPGA in serial slave mode.</p> FPGA Development: RE: FPGA serial programming interfacehttp://support.criticallink.com/redmine/boards/12/topics/4375?r=4376#message-43762015-03-10T17:01:06ZAlexander Blockalex.block@criticallink.com
<p>SB,</p>
<p>The FPGA is configured using 8 bit parallel slave select mode via the EMIFA bus connection to the Omap L138 processor.</p>
<p>Please reference this Wiki page for information about programming the FPGA: <a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA</a></p>
<p>Alex</p> FPGA Development: FPGA serial programming interfacehttp://support.criticallink.com/redmine/boards/12/topics/43752015-03-10T15:36:48Zstephan bernerstephan.berner@purevlc.com
<p>hi,</p>
<p>are the pins CCLK, DIN and the MODE pins available on the OMAP-138 as GPIOs, or are they open/hardcoded on the PCB.</p>
<p>SB</p> FPGA Development: RE: FPGA programminghttp://support.criticallink.com/redmine/boards/12/topics/4307?r=4309#message-43092015-01-12T05:48:00ZOleh Melaoleh.mela@gmail.com
<p>Thank for your reply Mike.</p>
<p>Is it possible to write an image FPGA through СОМ1 on MityDSP? Whether it is possible to make it under Windows?</p>
<p>Oleh</p> FPGA Development: RE: FPGA programminghttp://support.criticallink.com/redmine/boards/12/topics/4307?r=4308#message-43082015-01-10T09:17:37ZMichael Williamson
<p>Once you have a bit file that you like you can run the promgen tool to create the binary image to load per this wiki page:</p>
<p><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Overview">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Overview</a></p>
<p>Once you have a binary image, you can choose to program the FPGA from either u-Boot or from the linux command line, the choice depends on your application requirements.</p>
<p>Instructions for flashing the binary image to non-volatile storage and programming the FPGA from u-Boot or linux on boot up can be found here:</p>
<p><a class="external" href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA">https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA</a></p>
<p>-Mike</p> FPGA Development: FPGA programminghttp://support.criticallink.com/redmine/boards/12/topics/43072015-01-10T09:10:16ZOleh Melaoleh.mela@gmail.com
<p>Hi,</p>
<p>I have board L138-FI-236-RL.<br />Developed in Xilinx ISE the design fine works on FPGA at use ISE iMPACT.<br />Please, tell a step-by-step how to create an image for FPGA and how to provide working of the design at power off/power on.</p>
<p>Best regards,<br />Oleh</p> FPGA Development: RE: Programming the FPGAhttp://support.criticallink.com/redmine/boards/12/topics/604?r=4293#message-42932015-01-05T19:08:23ZFlemming Abrahamsenflabr@kkwindsolutions.com
<p>Hi</p>
<p>What was the solution to the last problem (add source error)? I get the same warning when trying to add pwm.ngc etc into a lx45 project.</p>
<p>thanks, Flemming</p> FPGA Development: RE: PlanAhead issuehttp://support.criticallink.com/redmine/boards/12/topics/4256?r=4257#message-42572014-11-17T07:29:52ZMichael Williamson
<p>For ISE (and I think ISE / PlanAhead are still the tools for Spartan 6, as the Vivado tools are for 7 series and higher), if you analyze your design with commercial temp and keep the non-commercial parts within their rated voltages and temperature, the speed scales and the part should work over it's specified range. So if your design meets timing for commercial speedgrade, then it will meet timing for the industrial over the industrial temperature range.</p>
<p>See these Xilinx posts:</p>
<p><a class="external" href="http://www.xilinx.com/support/answers/4235.html">http://www.xilinx.com/support/answers/4235.html</a><br /><a class="external" href="http://www.xilinx.com/support/answers/2945.html">http://www.xilinx.com/support/answers/2945.html</a><br /><a class="external" href="http://www.xilinx.com/support/answers/24245.html">http://www.xilinx.com/support/answers/24245.html</a></p>
<p>If you want to know the performance at a specific temperature, you can use the TEMPERATURE constraint, (see the last link above), but you need to scale the temperature by 15 degrees C.</p>
<p>Hope this helps. It's a little odd how Xilinx appears to handle this.</p>
<p>-Mike</p> FPGA Development: PlanAhead issuehttp://support.criticallink.com/redmine/boards/12/topics/42562014-11-17T03:21:49ZOleh Melaoleh.mela@gmail.com
<p>Hi,<br />Why at creation of the project in PlanAhead 14.7 for the chip xc6slx45csg324-3 it is not possible to specify Temp Grade I (only C)? In fact according to the specification on L138-FI-236-RL-ND it works in a range-40°C ~ 70°C.</p>
<p>Best Regards</p> FPGA Development: Clock for FPGAhttp://support.criticallink.com/redmine/boards/12/topics/42462014-10-31T10:44:50ZOleh Melaoleh.mela@gmail.com
<p>Hi.<br />I'm using MityDSP-L138F Board. As will ensure that the generated clock signal to FPGA?</p>
<p>Thanks</p> FPGA Development: RE: Mity L138F FPGA -> OMAP interrupt lineshttp://support.criticallink.com/redmine/boards/12/topics/4198?r=4200#message-42002014-09-18T10:07:12ZChristopher Brunsonchristopher.brunson@nottingham.ac.uk
<p>Thanks Mike,</p>
<p>I have found the pin mapping for INT0 and INT1 I couldn't find the mapping for the Non Maskable Interrupt (NMI) pin in the table. I also couldn't find the IOSTANDARD to use the interrupt pins.</p>
<p>Chris B.</p> FPGA Development: RE: Mity L138F FPGA -> OMAP interrupt lineshttp://support.criticallink.com/redmine/boards/12/topics/4198?r=4199#message-41992014-09-18T09:48:19ZMichael Williamson
<p>Hi Chris,</p>
<p>The information you need is in Table 4 of the <a href="http://www.criticallink.com/wp-content/uploads/2014/01/MityDSP-L138F-Carrier-Board-Design-Guide.pdf" class="external">Carrier Board Design Guide</a>.</p>
<p>-Mike</p> FPGA Development: Mity L138F FPGA -> OMAP interrupt lineshttp://support.criticallink.com/redmine/boards/12/topics/41982014-09-18T09:36:29ZChristopher Brunsonchristopher.brunson@nottingham.ac.uk
<p>I was trying to use an FPGA interrrupt which should be serviced by the DSP core in the OMAP.</p>
<p>From the MityL138.ucf I have the following FPGA pins:<br /><pre>
NET "o_int[1]" LOC = F2;
NET "o_int[0]" LOC = K6;
NET "o_nmi_n" LOC = N8;
</pre></p>
<p>Should these pins be IOSTANDARD LVCMOS33 or LVCMOS18?</p>
<p>So far what I think the OMAP interrupt pins are:<br /><pre>
INT0 -> GP6[12] -> R16
INT1 -> GP6[13] -> R17
NMI -> J17
</pre></p>
<p>I couldn't find the order in which the FPGA pins are mapped to the pins on the OMAP.</p>
<p>What pins/interrupts do the FPGA pins<pre> o_int[1](F2)</pre> and <pre>o_int[0](K6)</pre> map to on the OMAP?</p>
<p>Is it <pre>o_int[1](F2) -> INT0(GP6_12)</pre> and <pre>o_int[0](K6) -> INT1(GP6_13)</pre> or the other way around?</p>
<p>Thanks,</p>
<p>Chris B.</p> FPGA Development: RE: fpgautil read Issuehttp://support.criticallink.com/redmine/boards/12/topics/4080?r=4082#message-40822014-07-23T23:06:55Zpari subramaniampari.subramaniam@microsonics.com
<p>Hi Mike,<br /> I found the issue. I was updating the edo_out signals only when rd was going high.</p>
<pre><code>From the waveform i found rd signal going high after edo_out is driven on the interface.</code></pre>
<p>It really make sense when updated register value comes on the second register read. because the value only gets updated on rd after driving the edo_out.</p>
<p>Now, i removed the rd qualifier and it works fine.</p>
<p>Thanks Mike, the remainder about the waveform helped to relook my design.</p>
<p>--<br />Pari</p> FPGA Development: RE: fpgautil read Issuehttp://support.criticallink.com/redmine/boards/12/topics/4080?r=4081#message-40812014-07-23T20:42:48ZMichael Williamson
<p>Can you post (or email me) you VHDL source related to the loopback register?</p>
<p>Do you have Chipscope? It might be worth using chipscope to track the address / register data through the transfer cycle.</p>
<p>-Mike</p> FPGA Development: fpgautil read Issuehttp://support.criticallink.com/redmine/boards/12/topics/40802014-07-23T20:22:46Zpari subramaniampari.subramaniam@microsonics.com
<p>I'm using MityDSP-L138 Board. I have implemented a Custom IP in the FPGA board.</p>
<p>I'm using the CS5 ARM Chipselect and using the frame work available in fpga/vhdl directory.<br />Also, i'm using the fpgautil program in examples dir to read my register space in the custom IP.</p>
<p>When I read the register in the custom IP using fpgautil , it returns the value of the previous read. When i read the register again, it returns the actual value of register during the second read.</p>
<p>I checked the FPGA code and it seems to be behaving correctly.</p>
<p>Any idea where the issue could be?</p> FPGA Development: RE: DSP to FPGA SPI Setup Questionhttp://support.criticallink.com/redmine/boards/12/topics/3903?r=3956#message-39562014-06-25T16:02:47Zlijun yanglijunyang@my.unt.edu
<p>Hello,Mike<br />Thank you very much.</p> FPGA Development: RE: DSP to FPGA SPI Setup Questionhttp://support.criticallink.com/redmine/boards/12/topics/3903?r=3954#message-39542014-06-25T12:42:11ZMichael Williamson
<p>What is your target update rate? Continuous?</p>
<p>You might try first to rip out all of the overhead on the tcDspFpgaSpi.cpp code (there is LCK_pend()/LCK_post() for serialization control, etc) and boil it down to the register writes.</p>
<p>You could use the UPP, but you'd need to write your own UPP to SPI interface, which should not really be required.</p>
<p>You might try to write a FIFO to shift register interface in the FPGA and just write that FIFO directly and not use the SPI core.</p>
<p>-Mike</p> FPGA Development: RE: DSP to FPGA SPI Setup Questionhttp://support.criticallink.com/redmine/boards/12/topics/3903?r=3946#message-39462014-06-25T11:32:46Zlijun yanglijunyang@my.unt.edu
<p>Hello,Mike<br />Thank you for your help.<br />I have attached two pic <br />----one is the SPI bits transfer rate(This is our desired speed),</p>
<p>----another one is the word to word transfer rate(This is slow. We want it can be fast,Could you give us some ideas?)</p>
<p>If it can't work, we have to try the UPP.<br />Could you give us some ideas about UPP?</p>
<p>Than you very much.<br />Regards<br />LJ</p> FPGA Development: RE: DSP to FPGA SPI Setup Questionhttp://support.criticallink.com/redmine/boards/12/topics/3903?r=3943#message-39432014-06-25T10:47:34ZMichael Williamson
<p>Can you check with a scope at what the clock rate is on the SPI device, and the interword write delay? I just want to confirm they are getting 50 MHz clock rate.</p>
<p>It might be the EMIFA transfer, but we should confirm that the SPI device is running at rate.</p>
<p>-Mike</p> FPGA Development: RE: DSP to FPGA SPI Setup Questionhttp://support.criticallink.com/redmine/boards/12/topics/3903?r=3942#message-39422014-06-25T10:39:25ZAlexander Blockalex.block@criticallink.com
<p>Update and followup question from the customer:</p>
<p>We have made the SPI work, but transmitting the word to word is slow.(about 11 uSec to send a 24bit word).</p>
<p>This is the code we run in the DSP:</p>
<p>spi = new tcDspFpgaSpi((void *)my_base_addr);<br />spi->ConfigCS(0, 0, 0, 50000000, tcDspFpgaSpi::ee24Bit);<br />while(1)<br /> spi->Transfer(outData, NULL, 1, 0);</p>
<p>We suspect that the EMIFA communication is the bottleneck.</p>
<p><strong>Is this the bandwidth we should expect from EMIFA?</strong></p> FPGA Development: DSP to FPGA SPI Setup Questionhttp://support.criticallink.com/redmine/boards/12/topics/39032014-06-20T12:57:43Zlijun yanglijunyang@my.unt.edu
<p>Hello,ALL<br />I want to test the DspFpgaSpi, but not successfully setup,Could anyone give me some instructions?<br />Before I have successfully tested the GPIO from your help, Thank you very much!</p>
<p>This the VHDL code Setup<br />/////////////////////////<br />constant CORE_SPI_MODULE : integer :=14; /*the number is found in cores_id.h*/ <br />constant CORE_SPI_IRQ_LEVEL: integer :=1; /* communicate with DSP set 1 */<br />constant CORE_SPI_IRQ_VECTOR: integer :=0; ? How about this one,d,is it related to DSP ?,</p>
<pre><code>------------------------------------<br />---SPi&FIFO components port mapping--posted by Michael Williamson<br />----------------------------------<br />spi_core : spi<br /> Port Map ( <br /> emif_clk => ema_clk, <br /> i_ABus => addr_r,<br /> i_DBus => edi_r,<br /> o_DBus => edo_arm(CORE_SPI_MODULE),<br /> i_wr_en => wr_r,<br /> i_rd_en => rd_r,<br /> i_cs => arm_cs5_r(CORE_SPI_MODULE),<br /> o_irq => irq_map(CORE_SPI_IRQ_LEVEL)(CORE_SPI_IRQ_VECTOR),<br /> i_ilevel => CONV_STD_LOGIC_VECTOR(CORE_SPI_IRQ_LEVEL,2),<br /> i_ivector => CONV_STD_LOGIC_VECTOR(CORE_SPI_IRQ_VECTOR,4),</code></pre>
<pre><code>-- SPI interface signals <br /> o_sclk => spi_clk, ---These pins I have setted in ucf to map the Fpgat pins.<br /> o_cs_n => spi_cs,<br /> o_mosi => spi_mosi,<br /> i_miso => spi_miso,</code></pre>
<pre><code>-- In/Out FIFO interfaces (NO FIRST WORD FALL THROUGH) ///// Using the xilinx-ise to generate the FiFo Ip cores<br /> -- Synchronous on emif_clock<br /> i_fifo_depth => "010",<br /> o_mosi_fifo_wr => mosi_wr_en,<br /> o_mosi_fifo_rd => mosi_rd_en,<br /> o_mosi_fifo_in => mosi_din, -- fifo data input<br /> i_mosi_fifo_out => mosi_dout,<br /> i_mosi_write_cnt => mosi_wr_data_count,<br /> i_mosi_empty => mosi_empty,</code></pre>
<pre><code>o_miso_fifo_wr => miso_wr_en,<br /> o_miso_fifo_rd => miso_rd_en,<br /> o_miso_fifo_in => miso_din,<br /> i_miso_fifo_out => miso_dout,<br /> i_miso_read_cnt => miso_rd_data_count,<br /> i_miso_empty => miso_empty,</code></pre>
<pre><code>o_fifo_rst => spi_fifo_rst</code></pre>
<pre><code>);</code></pre>
<pre><code>spi_ccs<=spi_cs(0);<br /> --------------------------</code></pre>
<pre><code>mosi_fifo : fifo_dpram64x32<br /> port map (<br /> clk => ema_clk,<br /> rst => spi_fifo_rst,<br /> din => mosi_din,<br /> wr_en => mosi_wr_en,<br /> rd_en => mosi_rd_en,<br /> dout => mosi_dout,<br /> full => open,<br /> empty => mosi_empty,<br /> data_count => mosi_wr_data_count(5 downto 0));</code></pre>
<p>miso_fifo : fifo_dpram64x32<br /> port map (<br /> clk => ema_clk,<br /> rst => spi_fifo_rst,<br /> din => miso_din,<br /> wr_en => miso_wr_en,<br /> rd_en => miso_rd_en,<br /> dout => miso_dout,<br /> full => open,<br /> empty => miso_empty,<br /> data_count => miso_rd_data_count(5 downto 0)); <br />--------------------------------------------------------------</p>
<p>The DSP code<br />--------------------------<br />Using the existing function in DspFpgaSpi.cpp<br />---<br />---<br />-------------------------<br /> char outData<sup><a href="#fn32">32</a></sup>;<br /> char inData<sup><a href="#fn32">32</a></sup>;<br /> int i;<br /> unsigned int my_base_addr = 0x66000A00;<br /> // Setup the address, CORE_GPIO_MODUL=14(in vhdl),14*0x80=A00,set address:0x66000A00 )<br />spi = new tcDspFpgaSpi((void *)my_base_addr);<br /> // setup Chip Select<br />spi->ConfigCS(0, 0, 0, 1000000, tcDspFpgaSpi::ee8Bit);</p>
<p>while(1)
{</p>
<pre><code>// load TX data<br /> for (i=0; i&lt;32; i++)
{<br /> outData[i] = i;</code></pre>
<pre><code>}</code></pre>
<pre><code>// Do a SPI transfer<br /> spi->Transfer(outData, inData, 32, 0);<br /> }<br />//////////////////////////////////////////////////////////////////</code></pre>
<p>Best Regards<br />lj</p> FPGA Development: RE: Looking for help about SPI core communicate with DSPFPGAspihttp://support.criticallink.com/redmine/boards/12/topics/3879?r=3901#message-39012014-06-19T21:13:56ZGregory Gluszek
<p>Hello,</p>
<p>Your CORE_GPIO_MODULE and base address (0x66000080) do not match one another. The address should be the CORE offset times 0x80 bytes + 0x66000000.</p>
<p>So <br /><pre>
mpGpio = new tcDspFpgaGpio((void)0x66000080*); /* write the address*/
</pre><br />should be <br /><pre>
mpGpio = new tcDspFpgaGpio((void)0x66000200*); /* write the address*/
</pre><br />since CORE_GPIO_MODULE is set to 4.</p>
<p>Please let us know if this fixes the problem and if you have any further issues.</p>
<p>Thanks,<br />\Greg</p> FPGA Development: RE: Help me check out the gpio Setup,It is not work.http://support.criticallink.com/redmine/boards/12/topics/3898?r=3900#message-39002014-06-19T15:27:28Zlijun yanglijunyang@my.unt.edu
<p>Thank you very much,Mike</p> FPGA Development: RE: Help me check out the gpio Setup,It is not work.http://support.criticallink.com/redmine/boards/12/topics/3898?r=3899#message-38992014-06-19T15:11:55ZMichael Williamson
<p>The address for the constructor is not correct. The Address is: the CORE offset times 0x80 bytes + 0x66000000.</p>
<p>In your example, it should be 4*0x80 = 0x66000200.</p>
<p>The code looks OK, though you only need a 0x1 instead of a 0x3 for writing to 1 pin (bank 0, offset 0).</p>
<p>-Mike</p> FPGA Development: Help me check out the gpio Setup,It is not work.http://support.criticallink.com/redmine/boards/12/topics/38982014-06-19T14:58:46Zlijun yanglijunyang@my.unt.edu
<p>Hello.<br />Ask the same questions about the GPIO<br />I also try to use the DSP to communicate with FPGA<br />The follow is the VHDL code for gpio setup</p>
<p>/----------------------------------------------------------------------------/<br />--Gpio setup--<br />----------------------------------------------------<br />constant CORE_GPIO_MODULE : integer :=4; -- For Gpio core use defined in core_ids.h<br />constant CORE_GPIO_IRQ_LEVEL : integer :=1;-- level 1 is used for cores managed by the DSP<br />constant CORE_GPIO_IRQ_VECTOR :* integer :=0*;<br />------------------------------------------------------------------<br />--Gpio component define---<br />-------------------------------------------<br />gpio1 : gpio<br />generic map (<br />NUM_BANKS => 1,<br />NUM_IO_PER_BANK => 16<br />)<br />Port Map (<br />clk => ema_clk,<br />i_ABus => addr_r,<br />i_DBus => edi_r, * o_DBus => edo_arm(CORE_GPIO_MODULE),<br />i_wr_en => wr_r,<br />i_rd_en => rd_r,<br />i_cs => arm_cs5_r(CORE_GPIO_MODULE),<br />o_irq => irq_map(CORE_GPIO_IRQ_LEVEL)(CORE_GPIO_IRQ_VECTOR),<br />i_ilevel => conv_std_logic_vector(CORE_GPIO_IRQ_LEVEL, 2),<br />i_ivector => conv_std_logic_vector(CORE_GPIO_IRQ_VECTOR, 4),*<br />i_io => x"0000",<br />t_io => open,<br />o_io => o_diode,<br />i_initdir => x"FFFF",<br />i_initoutval => x"0000" <br />);<br />------------------------------------------------------<br />--------------------------------------------<br />The DSP code<br />------<br />-----------------------------------------------<br />MityDSP::tcDspFpgaGpio* mpGpio;</p>
<p>mpGpio = new tcDspFpgaGpio((void)0x66000080*); /* write the address*/<br />mpGpio->ConfigurePin(0,0,true,0,true,false); /* config the pin*/<br />while(1) {<br />mpGpio->WritePins(0,1,0x0);<br />for(int i=0;i<1000;i++); /*for delay*/<br />mpGpio->WritePins(0,1,0x3);<br />}<br />------------------------------------------<br />I just want to the gpio output the value 0x0 and 0x3<br />Who could help me check out whether I defined these variables right or not?</p>
<p>Thank you very much</p> FPGA Development: RE: Looking for help about SPI core communicate with DSPFPGAspihttp://support.criticallink.com/redmine/boards/12/topics/3879?r=3897#message-38972014-06-19T14:26:41Zlijun yanglijunyang@my.unt.edu
<p>Hello.<br />Ask the same questions about the GPIO<br />I also try to use the DSP to communicate with FPGA<br />The follow is the VHDL code for gpio setup</p>
<p>/----------------------------------------------------------------------------/<br />--Gpio setup--<br />----------------------------------------------------<br />constant CORE_GPIO_MODULE : <strong>integer :=4</strong>; -- For Gpio core use defined in core_ids.h<br />constant CORE_GPIO_IRQ_LEVEL : <strong>integer :=1;</strong>-- level 1 is used for cores managed by the DSP<br />constant CORE_GPIO_IRQ_VECTOR :* integer :=0*;<br />------------------------------------------------------------------<br />--Gpio component define---<br />-------------------------------------------<br />gpio1 : gpio<br /> generic map (<br /> NUM_BANKS => 1,<br /> NUM_IO_PER_BANK => 16<br /> )<br /> Port Map (<br /> clk => ema_clk,<br /> i_ABus => addr_r,<br /> i_DBus => edi_r,
* o_DBus => edo_arm(CORE_GPIO_MODULE),<br /> i_wr_en => wr_r,<br /> i_rd_en => rd_r,<br /> i_cs => arm_cs5_r(CORE_GPIO_MODULE),<br /> o_irq => irq_map(CORE_GPIO_IRQ_LEVEL)(CORE_GPIO_IRQ_VECTOR),<br /> i_ilevel => conv_std_logic_vector(CORE_GPIO_IRQ_LEVEL, 2), <br /> i_ivector => conv_std_logic_vector(CORE_GPIO_IRQ_VECTOR, 4),* <br /> i_io => x"0000",<br /> t_io => open,<br /> o_io => o_diode,<br /> i_initdir => x"FFFF",<br /> i_initoutval => x"0000" <br /> );<br />------------------------------------------------------<br />--------------------------------------------<br />The DSP code<br />------<br />-----------------------------------------------<br />MityDSP::tcDspFpgaGpio* mpGpio;</p>
<p>mpGpio = new tcDspFpgaGpio(<strong>(void</strong>)0x66000080*); /* write the address*/<br /> mpGpio->ConfigurePin(<strong>0,0,true,0,true,false</strong>); /* config the pin*/<br /> while(1)
{<br /> mpGpio->WritePins(<strong>0,1,0x0</strong>);<br />for(int i=0;i<1000;i++); /*for delay*/<br /> mpGpio->WritePins(<strong>0,1,0x3</strong>);<br /> }<br />------------------------------------------<br />I just want to the gpio output the value 0x0 and 0x3<br />Who could help me check out whether I defined these variables right or not?</p>
<p>Thank you very much</p> FPGA Development: RE: Looking for help about SPI core communicate with DSPFPGAspihttp://support.criticallink.com/redmine/boards/12/topics/3879?r=3896#message-38962014-06-19T13:09:48ZGregory Gluszek
<p>Hello,</p>
<pre>
constant CORE_SPI_IRQ_LEVEL : integer := 0;
</pre>
<p>Will route the IRQ to the ARM and not the DSP.</p>
<p>Try</p>
<pre>
constant CORE_SPI_IRQ_LEVEL : integer := 1;
</pre>
<p>Also, what base address are your feeding into the tcDspFpgaSpi constructor? Since you specified <br /><pre>
constant CORE_SPI: integer := 1;
</pre><br />the base address should be 0x66000080.</p>
<p>Hope this helps.</p>
<p>Let us know if you're still having trouble.</p>
<p>Thanks,<br />\Greg</p> FPGA Development: Looking for help about SPI core communicate with DSPFPGAspihttp://support.criticallink.com/redmine/boards/12/topics/38792014-06-17T14:21:57Zlijun yanglijunyang@my.unt.edu
<p>Hello,All<br />I have followed the instruction posted by Michael Williamson. The spi core on FPGA</p>
<p>--https://support.criticallink.com/redmine/boards/12/topics/1672?r=2036#message-2036</p>
<p>I built the FIFO using the IP CORES and put the SPI core component into the "the entity of the MityDSP_L138_top"</p>
<p>I am confused about some ports define<br /><pre>
/* o_irq => irq_map(CORE_SPI_IRQ_LEVEL)(CORE_SPI_IRQ_VECTOR),
i_ilevel => CONV_STD_LOGIC_VECTOR(CORE_SPI_IRQ_LEVEL,2),
i_ivector => CONV_STD_LOGIC_VECTOR(CORE_SPI_IRQ_VECTOR,4),*/
</pre><br />I defined the CORE_SPI_IRQ_LEVEL,CORE_SPI_IRQ_VECTOR,CORE_SPI as<br /><pre>
/*constant CORE_SPI_IRQ_LEVEL : integer := 0;
constant CORE_SPI_IRQ_VECTOR : integer := 1;
constant CORE_SPI: integer := 1;*/
</pre></p>
<p>Actually, it can pass the compiler.</p>
<p>My purpose is to use the DSPFPGASpi to test the Spi core whether it can work.</p>
<p>Unfortunately,I can't get the test signal from the spi.</p>
<p>Looking for someone know about how to using spi core communicate with DSPFPGAspi.</p>
<p>Thanks</p> FPGA Development: RE: Programming FPGA Flash using IMPACThttp://support.criticallink.com/redmine/boards/12/topics/3806?r=3818#message-38182014-05-19T16:43:59ZAhmed Shaabanashaban@ttctech.com.eg
<p>Thanks Michael,<br />I shall follow the steps in the link you mentioned and let you know results.</p> FPGA Development: RE: Programming FPGA Flash using IMPACThttp://support.criticallink.com/redmine/boards/12/topics/3806?r=3814#message-38142014-05-15T20:36:03ZMichael Williamson
<p>Hi,</p>
<p>Please take a look at the <a class="wiki-page" href="http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA">Programming the FPGA</a> wiki page for information about programming the FPGA.</p>
<p>The FPGA can be programmed via JTAG or via 8 bit parallel slave select mode through the OMAP-L138 (or AM18XX) EMIFA databus.</p>
<p>There is <a href="https://support.criticallink.com/gitweb/?p=u-boot-mitydspl138.git;a=blob;f=board/davinci/mityomapl138/fpga.c;h=29496402d5991df76c2c5026fe124f1f78f49282;hb=b305cd8ff244ff9c15f75eef5fd6ae70340b637e" class="external">code implemented in uBoot</a> for programming the FPGA, or you can use the linux drivers provided in the <a href="https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Board_Support_Package" class="external">Board Support Package</a>.</p>
<p>The NAND FLASH is a Micron x8 bit NAND. The FPGA does not use this NAND directly to boot (however, the processor can read a stored FPGA image on the NAND device to program the FPGA).</p>
<p>Please let me know if these links do not provide enough information.</p>
<p>-Mike</p> FPGA Development: RE: UPP Sample Code neededhttp://support.criticallink.com/redmine/boards/12/topics/3744?r=3807#message-38072014-05-11T13:03:49ZAhmed Shaabanashaban@ttctech.com.eg
<p>Thanks for you.That really helps.</p> FPGA Development: Programming FPGA Flash using IMPACThttp://support.criticallink.com/redmine/boards/12/topics/38062014-05-11T13:02:44ZAhmed Shaabanashaban@ttctech.com.eg
<p>Hello everyone, i have a MityARM-1808F with 256-Mb NAND Flash. <br />1 - I need to know the steps to Program FPGA Flash (NAND Flash as I think) using IMPACT (because I don't use Linux in my App. on ARM).<br />2 - what is NAND Flash Type ?</p>
<p>Thanks,<br />I appreciate your help.</p> FPGA Development: RE: Programming the FPGAhttp://support.criticallink.com/redmine/boards/12/topics/83?r=3798#message-37982014-04-27T12:45:38ZAnatoly Ivanov
<p>Or, you can simply try this (It has been checked on L138F and slx45, just remove -b option):</p>
<p><a class="external" href="http://www.xilinx.com/support/answers/35686.htm">http://www.xilinx.com/support/answers/35686.htm</a></p>
<p>BIN by bitgen is a non-byte-swapped file, the Sync Wordis read as "AA 99 55 66". <br />In older iMPACT versions, the generated BIN file by default is byte swapped. The Sync Word is "55 99 AA 66" in it. <br />In serial configuration by MCU, a non-byte-swapped BIN should be used; if the configuration mode is parallel/selectMAP, where Xilinx requires D0 be the most significant bit, you should use a byte-swapped BIN file. <br />The batch command to generate a BIN file is as below: <br />promgen -w [-b] -p bin -u 0 xxx.bit -o xxx.bin <br />Option -b stands for disabling byte swapping. If a byte-swapped Bin file is needed, remove the -b option.</p> FPGA Development: RE: Broken i_ema_a<8>http://support.criticallink.com/redmine/boards/12/topics/3505?r=3768#message-37682014-04-12T14:43:17ZAlexander Blockalex.block@criticallink.com
<p>Lukasz,</p>
<p>I have found the RMA request e-mail you have mentioned and have replied to that e-mail accordingly.</p>
<p>Thank you,</p>
<p>Alex</p> FPGA Development: RE: Broken i_ema_a<8>http://support.criticallink.com/redmine/boards/12/topics/3505?r=3767#message-37672014-04-12T12:58:10ZŁukasz Dałekluk0104@gmail.com
<p>I have more questions about RMA procedure.</p>
<p>The company send an e-mail to <a class="email" href="mailto:orders@criticallink.com">orders@criticallink.com</a> with a question about<br />initiating RMA procedure and till now there is no answer from there.<br />Can anyone from CL help me to solve this case?</p> FPGA Development: RE: UPP Sample Code neededhttp://support.criticallink.com/redmine/boards/12/topics/3744?r=3747#message-37472014-04-07T07:43:12ZMichael Williamson
<p>For the FPGA interface, you could take a look at the <a href="https://support.criticallink.com/redmine/projects/indio/wiki/Vision_Framework_Kit" class="external">Vision Framework Design FIles</a>. This uses the UPP to push video data from the FPGA to the OMAP-L138. Unfortunately, the OMAP-L138 SW does not use the tcDspUpp class in our current MDK -- it was written before this class was made available.</p>
<p>The UPP interface is pretty simple. It's basically a parallel bus with a simple "WAIT" handshake signal. The timing constraints will be somewhat specific to your clock configuration, as you may need to add clock-to-pad skew depending on the direction of the bus.</p>
<p>-Mike</p> FPGA Development: UPP Sample Code neededhttp://support.criticallink.com/redmine/boards/12/topics/37442014-04-03T01:26:02ZAhmed Shaabanashaban@ttctech.com.eg
<p>Hi everyone,<br />I need a sample FPGA code for <abbr title="Supported by Critical Link">UPP</abbr> with it's UCF file(including timing constraints). <br />Thanks in advance.</p> FPGA Development: RE: Manage LX16 and LX45 at runtimehttp://support.criticallink.com/redmine/boards/12/topics/3726?r=3728#message-37282014-03-23T20:05:54ZFrançois Tremblayfrancois@satellesinc.com
<p>Thanks a lot Mike!</p>
<p>As usual, your support is impressive!</p>
<p>Ticket close.</p>
<p>-François</p> FPGA Development: RE: Manage LX16 and LX45 at runtimehttp://support.criticallink.com/redmine/boards/12/topics/3726?r=3727#message-37272014-03-23T17:18:25ZMichael Williamson
<p>The model number for the part should be readable in the factory configuration information in the I2C prom. The model number includes a letter code for the FPGA type for the SOM. There is a factoryconfig utility program that can be run in linux to get the FPGA type or you can read the information off of the I2C prom directly using the correct MTD device. Source for the factoryconfig program should be included in the MDK and the executable should be included with the reference filesystems.</p>
<p>The programming script and the control module can be used to program either FPGA if provided with the correct programming bitstream.</p>
<p>-Mike</p> FPGA Development: Manage LX16 and LX45 at runtimehttp://support.criticallink.com/redmine/boards/12/topics/37262014-03-23T16:55:38ZFrançois Tremblayfrancois@satellesinc.com
<p>We have a product based on MityDSP-L138F using either LX16 and LX45 fpga cores.</p>
<p>Q1) Can we detect which FPGA core is running at runtime from Linux?</p>
<p>Q2) Is program_fpga.sh script and fpga_ctrl.ko module are able to handle both at runtime?</p>
<p>Thanks</p>
<p>-François</p> FPGA Development: I2C SMBus developmenthttp://support.criticallink.com/redmine/boards/12/topics/36232014-02-05T11:04:22ZAngelos SpanosAngelos.Spanos@purevlc.com
<p>Hi All,</p>
<p>I can see here (<a class="external" href="http://support.criticallink.com/rm_embedded/dsp-products/MDK_DOCS/2.11/core/class_mity_d_s_p_1_1tc_dsp_i2c2.html">http://support.criticallink.com/rm_embedded/dsp-products/MDK_DOCS/2.11/core/class_mity_d_s_p_1_1tc_dsp_i2c2.html</a>) that there is support for I2C-SMBus. However, in MDK_2013-05-15, I couldn't find the header core/DspI2c2.h.</p>
<p>Is DSP SMBus communication supported in this MDK?</p>
<p>Cheers,</p>
<p>Angelos</p> FPGA Development: RE: Broken i_ema_a<8>http://support.criticallink.com/redmine/boards/12/topics/3505?r=3512#message-35122014-01-07T19:18:32ZŁukasz Dałekluk0104@gmail.com
<p>ChipScope confirmed that sth is wrong with i_ema_a<8> pin.</p>
<p>Serial numbers of Mity modules: 121924 (broken), 131576 (working).</p>
<p>Lukasz</p> FPGA Development: RE: Broken i_ema_a<8>http://support.criticallink.com/redmine/boards/12/topics/3505?r=3509#message-35092014-01-07T08:11:49ZŁukasz Dałekluk0104@gmail.com
<p>I'll send them tomorrow.</p>
<p>Lukasz</p> FPGA Development: RE: Broken i_ema_a<8>http://support.criticallink.com/redmine/boards/12/topics/3505?r=3508#message-35082014-01-07T07:59:55ZMichael Williamson
<p>Yes. Two different mity boards. Can you give me the serial numbers?</p>
<p>-Mike</p> FPGA Development: RE: Broken i_ema_a<8>http://support.criticallink.com/redmine/boards/12/topics/3505?r=3507#message-35072014-01-07T07:57:38ZŁukasz Dałekluk0104@gmail.com
<p>Hello Mike,<br />1. What do you mean by two separate modules, two mity boards?<br />2. Yes, Same kernel, same application, same FPGA image.<br />3. Two diffrent host boards, but I don't think that host board can be a problem,<br />because no EMIF signal is routed outside module.</p>
<p>I'll try to test it using Chipscope by the end of the week.</p>
<p>Lukasz Dalek</p> FPGA Development: RE: Broken i_ema_a<8>http://support.criticallink.com/redmine/boards/12/topics/3505?r=3506#message-35062014-01-07T07:18:26ZMichael Williamson
<p>Hello Mr. Dalek,</p>
<p>It might be a problem. Between your "good and bad" boards:</p>
<p>- You are referring to 2 separate modules? Can you provide the serial numbers of the modules?<br />- You are running the same software image (same kernel, same application, same FPGA image, etc.)?<br />- You are using the same host board. Is it our DevKit or your custom board?</p>
<p>Do you have an FPGA JTAG pod? Can you run Xilinx's chipscope and capture the bus cycles from your test? That would confirm it (allowing rather direct inspection at the pin input), though you have a pretty good test case.</p>
<p>It sounds like we may need to issue you an RMA. If you send an email to <a class="email" href="mailto:orders@criticallink.com">orders@criticallink.com</a> you can initiate this process, please reference this forum post if you need to.</p>
<p>I am sorry for the inconvenience. Such a failure should not have made it though our automated factory tests.</p>
<p>-Mike</p> FPGA Development: Broken i_ema_a<8>http://support.criticallink.com/redmine/boards/12/topics/35052014-01-07T06:52:29ZŁukasz Dałekluk0104@gmail.com
<p>Hello,<br />My FPGA has a little problem with modules detection,<br />Linux driver and controlling program always double-detect them.<br />So I've tested address lines with this simple VHDL file:</p>
<p><code><br />o_nmi_n <= '1';<br />o_int <= (others => '0');<br />io_ema_d <= i_ema_a & i_ema_ba when i_ema_cs5_n = '0' else (others=>'Z');<br />io_ema_wait_n <= (others=>'Z');<br /></code></p>
<p>and C program:</p>
<p>fd = open("/dev/mem", O_RDWR);<br />...</p>
<p>mem = mmap(NULL, 0x4000000 /* 64 kB */, PROT_READ | PROT_WRITE,<br /> MAP_SHARED, fd, 0x66000000);<br />...</p>
<p>fpga = (volatile uint16_t *)mem;<br />log = fopen("emifatest.log", "w");<br />...</p>
<p>for (i = 0 ; i < 0x10000 / 2 ; ++i) {<br /> fprintf(log, "{ 0x%04X , 0x%04X }, // [%s]\n",<br /> i << 1, fpga[i], ((i << 1)!=fpga[i])?"NOK":"OK");<br />}</p>
<p>fclose(log);<br />munmap((void *)mem, 0x4000000);</p>
<p>And It showed up that 8th address line is broken:
{ 0xFFFE , 0xFBFE }, // [NOK]</p>
<p>the same file on working board:
{ 0xFFFE , 0xFFFE }, // [OK]</p>
<p>0xfffe 0y1111111111111110<br />0xfbfe 0y1111101111111110</p>
<p>And my question is if there is any chance, that this problem exists<br />because of misconfiguration?</p>
<p>Best regards,<br />Lukasz Dalek</p> FPGA Development: RE: Driving DVI-D with Spartan6 LX45 Fpgahttp://support.criticallink.com/redmine/boards/12/topics/3404?r=3406#message-34062013-11-30T07:29:29ZMichael Williamson
<p>The issue cannot be resolved without redesigning the PCB.</p>
<p>If you are using an LX-45, you cannot use the DVI interface on the dev kit. Why Xilinx did not bond out these pins remains a mystery.</p>
<p>I am sorry for any inconvenience.</p>
<p>-Mike</p> FPGA Development: Driving DVI-D with Spartan6 LX45 Fpgahttp://support.criticallink.com/redmine/boards/12/topics/34042013-11-30T02:03:36ZNaveen K.Semb_software@system-controls.com
<p>From the following discussion, it is said that Spartan6 LX45 FPGA based MityDSP-L138F SOM cannot drive DVI-D on Industrial IO boards. Is this case true now also or this issue resolved??<br />Kindly reply as soon as possible.</p>
<p>Thanks in Advance<br />Naveen K.S</p>
<p>""DVI Output with MityDSP-L138F w/6SLX45 FPGAs</p>
<p>Added by Wade Calcutt about 1 year ago</p>
<p>Based on the datasheet, models of the MityDSP-L138F SOM that have the 6SLX45 FPGA installed (L138-FI-225-RC, L138-DI-225-RI, and L138-FI-236-RL) have no connects on pins 154, 156, 158, 160, 162, 164, 170, and 172. Since some of these pins pass signals that are used for the DVI interface on the industrial I/O board, I presume that those models aren't capable of providing DVI video output. Can you verify this is the case?</p>
<p>Thanks.</p>
<p>Replies (1)<br />Comment<br />RE: DVI Output with MityDSP-L138F w/6SLX45 FPGAs - Added by Michael Williamson about 1 year ago</p>
<p>Wade,</p>
<p>Yes. The LX45 models cannot use the DVI interface as provided on the Industrial I/O boards.</p>
<p>The Industrial I/O board was developed prior to the LX45 SOM offerings came into existence, and because of the bonding issues with those pins we would have had to pick an interface that would have been sacrificed. So we elected to leave it "as is".</p>
<p>I am sorry for the inconvenience.""</p>
<p>-Mike</p>
<p>(1-1/1)</p>
<p>Reply</p> FPGA Development: RE: JFFS2 driver errorshttp://support.criticallink.com/redmine/boards/12/topics/3391?r=3394#message-33942013-11-23T15:34:35ZMichael Williamson
<p>You can do it in the DSP using tcDspSyscfg::SetMasterPriority() in the dsp core library.</p>
<p>-Mike</p> FPGA Development: RE: JFFS2 driver errorshttp://support.criticallink.com/redmine/boards/12/topics/3391?r=3393#message-33932013-11-23T13:30:40ZSteven Hillsteven@shscientific.com
<p>Thanks for those suggestions, Mike. According to Table 11-2, the default priority for EDMA is 0 (highest) and for ARM instruction and data is 2 (lower). When I look at these registers in debug mode (DSP), I see these default priorities in SYSCFG0DSP:MSTPRI0 and SYSCFG0DSP:MSTPRI1 Would you suggest making the ARM priority equal to 0 as well, or switching the priorities (ARM instruction/data = 0, EDMA = 2)? And how would I change these registers? Can I write directly to them? According to the literature, access is only available in privileged mode - how to I get into that mode?</p> FPGA Development: RE: JFFS2 driver errorshttp://support.criticallink.com/redmine/boards/12/topics/3391?r=3392#message-33922013-11-23T08:40:01ZMichael Williamson
<p>Hi Steven,</p>
<p>Is the DMA priority configured higher than the ARM data access priority in the Master Priority Configuration registers (see the OMAP-L138 Technical Reference Manual regarding DMA bus mastering priority)?</p>
<p>We have seen FPGA DMA's interfering with the linux NAND based driver (they share the same bus), one work-around has been to lower the DMA priority to allow the NAND driver cleaner access to the EMIFA bus.</p>
<p>If this is not an option, there is a patch that can be made to the linux kernel that may resolve the issue at the potential cost of lower NAND performance.</p>
<p>-Mike</p> FPGA Development: JFFS2 driver errorshttp://support.criticallink.com/redmine/boards/12/topics/33912013-11-22T23:12:50ZSteven Hillsteven@shscientific.com
<p>I'm seeing some errors similar to those mentioned in the following thread:<br /><a class="external" href="http://support.criticallink.com/redmine/boards/12/topics/2954">http://support.criticallink.com/redmine/boards/12/topics/2954</a><br /> I am using the CL FPGA modules for EMIF, etc with no changes and making DMA transfers from the FPGA. I don't know if I should be concerned about these errors, or if my DMA transfers are being compromised as well...I'm seeing errors like:</p>
<blockquote>
<p><code>root@mityomapl138:/mnt/user_nand# mtd->read(0x984 bytes from 0x3768c18) returned ECC error<br />Data CRC failed on REF_PRISTINE data node at 0x03768c18: Read 0xd5ffae84, calculated 0x533eb09a<br />mtd->read(0xa18 bytes from 0x376bdec) returned ECC error<br />Data CRC failed on REF_PRISTINE data node at 0x0376bdec: Read 0x031b1385, calculated 0x333e2d9f<br />mtd->read(0x898 bytes from 0x376f794) returned ECC error<br />Data CRC failed on REF_PRISTINE data node at 0x0376f794: Read 0x7fb3eadc, calculated 0x755c84f8</code></p>
</blockquote>
<p>At one point when I was running the application automatically on boot-up there were so many errors that it was not possible to log in and I had to re-flash the file system. Are there some changes that can be made to the EMIF configuration to deal with these issues?</p> FPGA Development: RE: uPP receive issueshttp://support.criticallink.com/redmine/boards/12/topics/3275?r=3337#message-33372013-11-05T07:05:30ZMichael Williamson
<p>Yes, this is the issue. The pin-muxed OMAP-L138 net that includes the UPP_CHB_CLOCK is not connected to a GCLK pin. We didn't have the routing resources (or the clock pins) to connect every possible clock pin on the OMAP-L138 to a GCLK pin on the FPGA.</p>
<p>As the message says, you can force the placer to use the assignment anyway with the constraint mentioned above.</p>
<p>We have done this on several designs and in all cases have been able to close timings. The SDR max frequency for the UPP clock is only 75 MHz, so the routing skew from a non-clock pin to a clock net is usually very small compared to the overall period and pad to clock requirements.</p>
<p>-Mike</p> FPGA Development: RE: uPP receive issueshttp://support.criticallink.com/redmine/boards/12/topics/3275?r=3336#message-33362013-11-05T06:18:27Zminh tungtungdm@viettel.com.vn
<p>I have resolve that problems. Maybe I was wrong to select uPP clock sources (PLL1_SYSCLK2).</p>
<p>But, when my FPGA sytem is bigger. I have an other bugs when mapping the logic.</p>
<p>Place:1108 - A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock<br /> IOB / BUFGMUX site pair. The clock IOB component <io_upp_chb_clock> is placed at site <PAD296>. The corresponding<br /> BUFG component <io_upp_chb_clock_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y11>. There is only a select set of IOBs<br /> that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this<br /> problem exists and correct it. If this sub optimal condition is acceptable for this design, you may use the<br /> CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to<br /> continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is<br /> recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock<br /> placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule.<br /> < NET "io_upp_chb_clock" CLOCK_DEDICATED_ROUTE = FALSE; ></p>
<p>Maybe, the reasons is that the io_upp_chb_clock pin is not come from GCLK pin.</p>
<p>I have no chipscope license.</p> FPGA Development: RE: uPP receive issueshttp://support.criticallink.com/redmine/boards/12/topics/3275?r=3288#message-32882013-10-25T08:10:00ZMichael Williamson
<p>Do you know which two byes you are missing? Are they consistently the same two bytes?</p>
<p>Do you have a chipscope license?</p> FPGA Development: RE: uPP receive issueshttp://support.criticallink.com/redmine/boards/12/topics/3275?r=3276#message-32762013-10-23T08:25:11Zminh tungtungdm@viettel.com.vn
<p>I have updated my source code</p>
<p>This is my *.ucf file<br />NET "o_upp_2xtxclk" LOC = "F4" | IOSTANDARD = LVCMOS18; <br />NET "io_upp_chb_clock" LOC = "T1" | IOSTANDARD = LVCMOS18; <br />NET "io_upp_chb_start" LOC = "T2" | IOSTANDARD = LVCMOS18 | PULLDOWN;<br />NET "io_upp_chb_enable" LOC = "M3" | IOSTANDARD = LVCMOS18 | PULLDOWN;<br />NET "io_upp_chb_wait" LOC = "P3" | IOSTANDARD = LVCMOS18 | PULLUP;<br />NET "io_upp_cha_clock" LOC = "H7" | IOSTANDARD = LVCMOS18; <br />NET "io_upp_cha_start" LOC = "C1" | IOSTANDARD = LVCMOS18 | PULLDOWN; <br />NET "io_upp_cha_enable" LOC = "H5" | IOSTANDARD = LVCMOS18 | PULLDOWN; <br />NET "io_upp_cha_wait" LOC = "L5" | IOSTANDARD = LVCMOS18;</p>
<ol>
<li>Littel Endian<br />NET "upp_core_0_i_upp_chb_d_pin<7>" LOC = "M1" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_i_upp_chb_d_pin<6>" LOC = "L2" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_i_upp_chb_d_pin<5>" LOC = "H2" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_i_upp_chb_d_pin<4>" LOC = "L1" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_i_upp_chb_d_pin<3>" LOC = "K2" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_i_upp_chb_d_pin<2>" LOC = "H1" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_i_upp_chb_d_pin<1>" LOC = "K1" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_i_upp_chb_d_pin<0>" LOC = "J1" | IOSTANDARD = LVCMOS18;<br />NET "upp_core_0_i_upp_chb_d_pin<15>" LOC = "F3" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_i_upp_chb_d_pin<14>" LOC = "D3" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_i_upp_chb_d_pin<13>" LOC = "M5" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_i_upp_chb_d_pin<12>" LOC = "D2" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_i_upp_chb_d_pin<11>" LOC = "E3" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_i_upp_chb_d_pin<10>" LOC = "D1" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_i_upp_chb_d_pin<9>" LOC = "E4" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_i_upp_chb_d_pin<8>" LOC = "F1" | IOSTANDARD = LVCMOS18;</li>
</ol>
<p>NET "upp_core_0_o_upp_cha_d_pin<7>" LOC = "L4" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_o_upp_cha_d_pin<6>" LOC = "H4" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_o_upp_cha_d_pin<5>" LOC = "P1" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_o_upp_cha_d_pin<4>" LOC = "P2" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_o_upp_cha_d_pin<3>" LOC = "H3" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_o_upp_cha_d_pin<2>" LOC = "N1" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_o_upp_cha_d_pin<1>" LOC = "N2" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_o_upp_cha_d_pin<0>" LOC = "G3" | IOSTANDARD = LVCMOS18;<br />NET "upp_core_0_o_upp_cha_d_pin<15>" LOC = "F5" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_o_upp_cha_d_pin<14>" LOC = "F6" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_o_upp_cha_d_pin<13>" LOC = "G6" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_o_upp_cha_d_pin<12>" LOC = "L6" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_o_upp_cha_d_pin<11>" LOC = "J6" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_o_upp_cha_d_pin<10>" LOC = "H6" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_o_upp_cha_d_pin<9>" LOC = "K5" | IOSTANDARD = LVCMOS18; <br />NET "upp_core_0_o_upp_cha_d_pin<8>" LOC = "L7" | IOSTANDARD = LVCMOS18;</p> FPGA Development: uPP receive issueshttp://support.criticallink.com/redmine/boards/12/topics/32752013-10-23T08:03:22Zminh tungtungdm@viettel.com.vn
<p>Hi,<br />I am using Upp to transfer data between FPGA and OMAP.<br />The data send from FPGA to OMAP is OK. But FPGA can not receive exactly data from OMAP.<br />FPGA has missed 2 byte from OMAP.<br />in FPGA design, i have used clock from OMAP to receive data and store in fifo( write and read clock are different).<br />I didn't used any contrains between data and clock input.</p>
<p>Can you give some advice to bypass this issues or give me example upp interface.</p>
<p>(I have follow from this instruction :http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/UPP_Design_Considerations)</p> FPGA Development: RE: BUSY and AWAKE LEDshttp://support.criticallink.com/redmine/boards/12/topics/3184?r=3185#message-31852013-09-17T12:35:02ZMichael Williamson
<p>D2 (AWAKE) is connected to pin P15 of the FPGA. Drive high to light.<br />D3 (BUSY) is connected to pin P16 of the FPGA. Drive high to light.</p>
<p>-Mike</p> FPGA Development: BUSY and AWAKE LEDshttp://support.criticallink.com/redmine/boards/12/topics/31842013-09-17T12:21:47ZStewart Cobbstu@ikarenetwork.com
<p>On my L138-DI-225-RI board, I observe two LEDs labeled "BUSY" and "AWAKE". These are located next to the "DONE" LED which is obviously connected to the DONE pin of the FPGA. Are the other two LEDs connected to the FPGA? If so, what pins are they connected to? My project could really use a blinking light to let the operators know it's alive.</p> FPGA Development: RE: Problem programming FPGA with Linux driverhttp://support.criticallink.com/redmine/boards/12/topics/3081?r=3088#message-30882013-08-15T14:50:17ZSteven Hillsteven@shscientific.com
<p>I guess I spoke too soon. I am still having this problem - with working FPGA code, sometimes I can get the cores to enumerate using echo "3" and sometimes it will not work. Small changes in the code of my custom core that appear to have no relationship with the base module or emifa module will cause the loading process to give a PROGRAM FAIL response even though (according to signals on the scope) it is working fine. Wilinx shows all signals routed and all constraints met with no timing errors. The only warning that I think might have some relevance (I am a novice in VHDL coding) is the following:<br />Place:1109 - A clock IOB / BUFGMUX clock component pair have been found<br /> that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock<br /> IOB component <i_ema_clk> is placed at site <T8>. The corresponding BUFG<br /> component <emaclk_inst> is placed at site <BUFGMUX_X2Y3>. There is only a<br /> select set of IOBs that can use the fast path to the Clocker buffer, and they<br /> are not being used. You may want to analyze why this problem exists and<br /> correct it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE<br /> constraint was applied on COMP.PIN <i_ema_clk.PAD> allowing your design to<br /> continue. This constraint disables all clock placer rules related to the<br /> specified COMP.PIN. The use of this override is highly discouraged as it may<br /> lead to very poor timing results. It is recommended that this error condition<br /> be corrected in the design.</p>
<p>Any assistance would be welcome...</p> FPGA Development: RE: Problem programming FPGA with Linux driverhttp://support.criticallink.com/redmine/boards/12/topics/3081?r=3086#message-30862013-08-15T12:34:04ZSteven Hillsteven@shscientific.com
<p>I think I figured out the source of the problem myself. Although I didn't change anything in the module files for base and emifa, in my top module port map for the base module I had disabled the "i_irq_map" and "o_irq_output" connections. When I enabled them the enumeration worked.</p> FPGA Development: RE: Problem programming FPGA with Linux driverhttp://support.criticallink.com/redmine/boards/12/topics/3081?r=3084#message-30842013-08-14T18:57:48ZSteven Hillsteven@shscientific.com
<p>I am using the Critical Link framework - the base module and the EMIFA interface are untouched.</p> FPGA Development: RE: Problem programming FPGA with Linux driverhttp://support.criticallink.com/redmine/boards/12/topics/3081?r=3083#message-30832013-08-14T18:08:07ZMichael Williamson
<p>If you are not using our framework (the base module, specifically), then the state will report failed as it is probing the base module for valid versioning information. Are you using the base module or have you implemented your own EMIFA interface?</p>
<p>-Mike</p> FPGA Development: Problem programming FPGA with Linux driverhttp://support.criticallink.com/redmine/boards/12/topics/30812013-08-14T16:06:23ZSteven Hillsteven@shscientific.com
<p>I'm having a problem programming the FPGA using the Linux driver. I am generating a core bin file using IMPACT, and the sequence of loading the file seems to execute with no problems - the "DONE" LED goes on, and I can see with a scope that the FPGA is loaded and seems to be running properly. The problem is that echo "3" does not enumerate the cores and <br />cat /sys/devices/fpga_ctrl/state returns 3: PROGRAM FAIL. When I run ARM software that tries to mmap the core it fails. Any idea what could be causing this?</p> FPGA Development: RE: Programming FPGA on power up issueshttp://support.criticallink.com/redmine/boards/12/topics/3054?r=3072#message-30722013-08-13T22:48:44Zminh tungtungdm@viettel.com.vn
<p>Hi,<br />We have resolved that issues.</p>
<p>We used EDK system to develop FPGA and we modified bitgen.ut below:</p>
<p>-g TdoPin:PULLNONE<br />#-g StartUpClk:JTAGCLK<br />-g DriveDone:YES</p>
<p>before that: we use -g StartUpClk:JTAGCLK and -g TdoPin:PULLNONE command only</p>
<p>I think the reasons is that: when use configure JTAGCLK to start up FPGA, CPU cannot boot up FPGA.</p> FPGA Development: RE: Programming FPGA on power up issueshttp://support.criticallink.com/redmine/boards/12/topics/3054?r=3070#message-30702013-08-13T18:33:23ZMichael Williamson
<p>Hi,</p>
<p>Sorry for the delay, are you still having issue here? Or have you solved the issue?</p>
<p>Can you dump your u-boot text when you try to program?</p>
<p>-Mike</p> FPGA Development: RE: Programming FPGA on power up issueshttp://support.criticallink.com/redmine/boards/12/topics/3054?r=3056#message-30562013-08-06T07:21:44Zminh tungtungdm@viettel.com.vn
<p>I have done 2 way CPU,Linux and u-Boot. But result is the same.</p> FPGA Development: RE: Programming FPGA on power up issueshttp://support.criticallink.com/redmine/boards/12/topics/3054?r=3055#message-30552013-08-06T07:15:12ZMichael Williamson
<p>How are you loading via CPU, linux or via u-Boot?</p> FPGA Development: Programming FPGA on power up issueshttp://support.criticallink.com/redmine/boards/12/topics/30542013-08-06T06:45:02Zminh tungtungdm@viettel.com.vn
<p>Hi,<br />I am using MityDSP-<abbr title="LX16 FPGA">L138F</abbr> and Carrier Board.<br />I developed new FPGA system that included only Upp Interface, DCM (Input clock: 100MHz, output clock 75MHz) (I removed base_module, emif interface ,...) can be connect with OMAPL138.<br />First,I using JTAG to program FPGA, the system run fine and DONE LED was light up.<br />Second, when I try to create .bin file and loading via CPU. It cannot run and DONE LEN wasn't light up.</p>
<p>(I follow instruction:<br />(1)http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Overview<br />(2)http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA<br />)<br />But, When I using industrialio_top.bit (MDK_2011-12-05\examples\industrial_io\fpga\build_dvi_rev_a_b) to create industrialio_top.bin and loading via CPU (Do the same way as befor) and there is DONE LED.</p>
<p>Can you give me some instruction to find out the problems in my program?</p>
<p>I am looking forward for your replying.</p>
<p>Thank,</p> FPGA Development: RE: EMA_WAIT and bus contention on L138Fhttp://support.criticallink.com/redmine/boards/12/topics/2954?r=3014#message-30142013-07-22T15:52:09ZMostafa Afgani
<p>Hi Mike, relevant definitions from the header:</p>
<pre>
# define AEMIF_BASE 0x68000000
# define AEMIF_AWCCR *( volatile Uint32* )( AEMIF_BASE + 0x04 )
# define AEMIF_A1CR *( volatile Uint32* )( AEMIF_BASE + 0x10 )
# define AEMIF_A2CR *( volatile Uint32* )( AEMIF_BASE + 0x14 )
# define AEMIF_A3CR *( volatile Uint32* )( AEMIF_BASE + 0x18 )
# define AEMIF_A4CR *( volatile Uint32* )( AEMIF_BASE + 0x1C )
</pre>
<p>this matches the register addresses given in the OMAP-L138 datasheet.</p>
<p>-Mostafa</p> FPGA Development: RE: EMA_WAIT and bus contention on L138Fhttp://support.criticallink.com/redmine/boards/12/topics/2954?r=3013#message-30132013-07-22T14:11:56ZMichael Williamson
<p>Just for sanity,</p>
<p>Have you confirmed you are writing to the correct AEMIF registers? CE3 is the NAND, and you are hitting "AEMIF_A3CR" in the above. I get a little confused about the register numbering vs. the CS numbering. Just want to make sure that you aren't whacking the NAND timings instead of the two FPGA chip selects (CS4 and CS4)....</p>
<p>-Mike</p> FPGA Development: RE: EMA_WAIT and bus contention on L138Fhttp://support.criticallink.com/redmine/boards/12/topics/2954?r=3012#message-30122013-07-22T13:42:01ZMostafa Afgani
<p>Hi Mike,</p>
<p>I've now also tried setting unused I/O to float and increasing both the TA and Read Hold to 4 cycles. I've verified the timing change with ChipScope but unfortunately it has had no effect on the JFFS2 warnings.</p>
<p>Attaching a copy of the bare-bones ISE project I am using to debug the EMIF interface. The CS4 and CS5 configs are currently:</p>
<pre><code>AEMIF_A3CR = (0 << 31) | /* Select Strobe <strong>/<br /> (0 << 30) | /</strong> Extended Wait <strong>/<br /> (0 << 26) | /</strong> Write Setup-1 in EMA_CLK <strong>/<br /> (0 << 20) | /</strong> Write strobe-1 in EMA_CLK <strong>/<br /> (0 << 17) | /</strong> Write Hold-1 in EMA_CLK <strong>/<br /> (0 << 13) | /</strong> Read Setup-1 in EMA_CLK <strong>/<br /> (4 << 7) | /</strong> Read Strobe-1 in EMA_CLK <strong>/<br /> (2 << 4) | /</strong> Read Hold-1 in EMA_CLK <strong>/<br /> (3 << 2) | /</strong> Turn-Around in EMA_CLK <strong>/<br /> (1); /</strong> Bus Width (16 bits data bus) */</code></pre>
<pre><code>AEMIF_A4CR = (0 << 31) | /* Select Strobe <strong>/<br /> (0 << 30) | /</strong> Extended Wait <strong>/<br /> (0 << 26) | /</strong> Write Setup-1 in EMA_CLK <strong>/<br /> (0 << 20) | /</strong> Write strobe-1 in EMA_CLK <strong>/<br /> (0 << 17) | /</strong> Write Hold-1 in EMA_CLK <strong>/<br /> (0 << 13) | /</strong> Read Setup-1 in EMA_CLK <strong>/<br /> (4 << 7) | /</strong> Read Strobe-1 in EMA_CLK <strong>/<br /> (2 << 4) | /</strong> Read Hold-1 in EMA_CLK <strong>/<br /> (3 << 2) | /</strong> Turn-Around in EMA_CLK <strong>/<br /> (1); /</strong> Bus Width (16 bits data bus) */</code></pre>
<p>Thanks for taking a look. Do you see anything out of place?</p>
<p>Best regards,<br />Mostafa</p> FPGA Development: RE: EMA_WAIT and bus contention on L138Fhttp://support.criticallink.com/redmine/boards/12/topics/2954?r=2986#message-29862013-07-18T12:30:45ZMichael Williamson
<p>One thought:</p>
<p>Is it possible the tri-state drive logic for the data lines off the FPGA is creating bus contention? Perhaps there is a bug in the EMIFA interface that is not parking/tri-stating the data lines soon enough after OE is deasserted? Wondering if you need to set a higher TA in the EMIFA configuration.</p>
<p>-Mike</p> FPGA Development: RE: EMA_WAIT and bus contention on L138Fhttp://support.criticallink.com/redmine/boards/12/topics/2954?r=2985#message-29852013-07-18T12:24:09ZMostafa Afgani
<p>Hi Mike,</p>
<p>Thanks for the suggestions.</p>
<p>Not sure I understand what you mean by FPGA access bandwidth. It is being used to implement the frontend of a high speed wireless communication system so we are using the the bus pretty much continuously. It is being used to transfer 16bit words with the OMAP running at 456MHz. I understand that the access by NAND and FPGA cannot be truly concurrent since it is a shared bus but I would have thought that when the processor switches over to a CS line (say 4), data on the EMIF or the state of the WAIT line should not have any effect on peripherals on the other CS lines (e.g., 3).</p>
<p>We did try making the pins outputs tied to a constant 'Z' but that still caused the JFFS2 driver to report CRC/Read errors during periods of heavy FPGA activity -- and that is something which is baffling us completely. The constraint file is also free of any PULLDOWN/PULLUP directives on the WAIT lines. Haven't tried setting unused I/O to float yet so will give that a go and report back.</p>
<p>Best regards,<br />Mostafa</p> FPGA Development: RE: EMA_WAIT and bus contention on L138Fhttp://support.criticallink.com/redmine/boards/12/topics/2954?r=2957#message-29572013-07-17T07:38:57ZMichael Williamson
<p>Hello,</p>
<p>How much bandwidth are you using for the FPGA accesses? Have you looked with any sort of bus analyzer (perhaps in chip scope) to assess the access logic? If the WAIT pin is getting hit, the slowdown could also be the ECC logic and error handling in the NAND driver. You of course are sharing a common data bus, so there will be a slow down of either NAND or FPGA activity while the other is occurring (you can't do both access concurrently, they are queued transactions by the EMIFA controller, of course).</p>
<p>For the WAIT pins, you need to ensure to disable the pull-downs completely on the WAIT lines and make those pins high impedance ('Z's). The FPGA pull downs/ups are fairly strong and the NAND likely tri-states when not asserting WAIT (I need to confirm this). If you interfere with the WAIT logic at all, it will create problems with the ECC logic and the NAND access state machine. Do not pull them up or down, leave them tri-stated with no pullup options and it should work ok.</p>
<p>Make sure that your constraints file does not include a PULLDOWN or PULLUP option on those pins and that you <strong>float</strong> unused IOBs in the bitstream generation options in the event that the logic is stripped from your design by the synthesis/place and route tools.</p>
<p>You should be able to support what you are trying to do (we've done it here on several occasions).</p>
<p>-Mike</p> FPGA Development: EMA_WAIT and bus contention on L138Fhttp://support.criticallink.com/redmine/boards/12/topics/29542013-07-16T12:07:35ZMostafa Afgani
<p>We have a project which uses CS4 and CS5 to write and read data from a pair of FPGA FIFOs respectively. CS4 is used exclusively for writing while CS5 is used exclusively for reading. The config register settings are:</p>
<pre><code>/* CS4 config <strong>/<br /> AEMIF_A3CR = (0 << 31) | /</strong> Select Strobe <strong>/<br /> (0 << 30) | /</strong> Extended Wait <strong>/<br /> (0 << 26) | /</strong> Write Setup-1 in EMA_CLK <strong>/<br /> (0 << 20) | /</strong> Write strobe-1 in EMA_CLK <strong>/<br /> (0 << 17) | /</strong> Write Hold-1 in EMA_CLK <strong>/<br /> (0 << 13) | /</strong> Read Setup-1 in EMA_CLK <strong>/<br /> (4 << 7) | /</strong> Read Strobe-1 in EMA_CLK <strong>/<br /> (0 << 4) | /</strong> Read Hold-1 in EMA_CLK <strong>/<br /> (0 << 2) | /</strong> Turn-Around in EMA_CLK <strong>/<br /> (1); /</strong> Bus Width (16 bits data bus) */</code></pre>
<pre><code>/* CS5 config <strong>/<br /> AEMIF_A4CR = (0 << 31) | /</strong> Select Strobe <strong>/<br /> (0 << 30) | /</strong> Extended Wait <strong>/<br /> (0 << 26) | /</strong> Write Setup-1 in EMA_CLK <strong>/<br /> (0 << 20) | /</strong> Write strobe-1 in EMA_CLK <strong>/<br /> (0 << 17) | /</strong> Write Hold-1 in EMA_CLK <strong>/<br /> (0 << 13) | /</strong> Read Setup-1 in EMA_CLK <strong>/<br /> (4 << 7) | /</strong> Read Strobe-1 in EMA_CLK <strong>/<br /> (0 << 4) | /</strong> Read Hold-1 in EMA_CLK <strong>/<br /> (0 << 2) | /</strong> Turn-Around in EMA_CLK <strong>/<br /> (1); /</strong> Bus Width (16 bits data bus) */</code></pre>
<p>Given that we don't use WAIT, both WAIT_0 and WAIT_1 were ignored from the design and the FPGA automatically configured them as inputs with pull-down. With this, CS4 and CS5 transfers worked perfectly but we noticed a significant slowdown in data transfer to/from the NAND flash (CS3) whenever there was concurrent data transfer to/from the FPGA. The reason for this must be WAIT_0 being an active low signal and pulling it down sets it to always active.</p>
<p>To fix this, we tried two things:<br /> 1. Leave the WAIT signals tri-stated on the FPGA,<br /> 2. Set them low (i.e., active) when CS4 or CS5 is active, tri-stated otherwise.</p>
<p>However, in both cases, the JFFS2 driver spits out a whole bunch of warnings and CRC errors whenever there is concurrent access to the bus -- seemingly indicating contention. We just can't figure our why this should happen.</p>
<p>Any suggestions? Thanks in advance.</p> FPGA Development: RE: Hardware Resethttp://support.criticallink.com/redmine/boards/12/topics/2885?r=2891#message-28912013-07-02T10:51:29ZMichael Williamson
<p>On the MityDSP-L138F, RESET_IN pin is fed into a TPS3808G33DBVR reset monitor circuit. It is not connected to the FPGA or the OMAP-L138 directly. The output RESET of the TPS3808 is fed to the RESET pin on the OMAP-L138. The OMAP-L138 RESETOUT# signal (ball T17) is connected via a transistor (Q1 on clip of the schematic below) to the PROGRAM pin on the FPGA.</p>
<p><img src="http://support.criticallink.com/redmine/attachments/download/3472/L138_FPGA_PROGRAM.png" alt="" /></p> FPGA Development: RE: Hardware Resethttp://support.criticallink.com/redmine/boards/12/topics/2885?r=2890#message-28902013-07-02T10:06:41ZCraig Littlecraig.little@fmcti.com
<p>Hi Mike,</p>
<p>In effect yes. I was wondering if the device/circuit which drives the reset pin of the OMAP processor is also<br />connected to the FPGA and if yes, which pin.</p>
<p>Regards,<br />Steven.</p> FPGA Development: RE: Hardware Resethttp://support.criticallink.com/redmine/boards/12/topics/2885?r=2889#message-28892013-07-01T19:49:40ZMichael Williamson
<p>When there is a power on reset, the FPGA will be re-initialized (the program pin is pulled low) and will require reprogramming.</p>
<p>Are you looking for an additional pin that may be used to reset just the FPGA?</p>
<p>-Mike</p> FPGA Development: Hardware Resethttp://support.criticallink.com/redmine/boards/12/topics/28852013-07-01T10:48:09ZCraig Littlecraig.little@fmcti.com
<p>Hi There,</p>
<p>Is there a pin on the MityDSP-L138F processor board FPGA which is attached to a <br />dedicated power-on/hardware reset source which can be used to initialise/reset registers?</p>
<p>Kind regards,<br />Steven Bremner.</p> FPGA Development: RE: Problem building IndustrialIO project build_lcd_rev_chttp://support.criticallink.com/redmine/boards/12/topics/2866?r=2879#message-28792013-06-26T14:19:10ZSteven Hillsteven@shscientific.com
<p>I found the solution to the problem. I had to remove the Xilinx device that was in the iMPACT window (left over from the original IndustrialIO example project .ipf file, I assume) and the add a new device which is done by selecting the bit file from the project. Then I chose a PROM size large enough to hold the .bit file and generated the .bin file and it worked. Next I will see if I can program the FPGA in UBoot...</p> FPGA Development: RE: Problem building IndustrialIO project build_lcd_rev_chttp://support.criticallink.com/redmine/boards/12/topics/2866?r=2878#message-28782013-06-26T13:57:48ZMichael Williamson
<p>OK clearly it's not finding the file (according to the log). Looks like you have spaces in your path to the bit file, that may be the problem. You might try to copy the bit file to a local path and see if it can open it up. Also, make sure that your prom size is auto-selected or is large enough to hold the image.</p>
<p>You might try the Xilinx web forums for help on this, they are pretty good about supporting their tools. (I've not had any problem like this with projects here).</p>
<p>-Mike</p> FPGA Development: RE: Problem building IndustrialIO project build_lcd_rev_chttp://support.criticallink.com/redmine/boards/12/topics/2866?r=2877#message-28772013-06-26T13:54:43ZSteven Hillsteven@shscientific.com
<p>That does not seem to work. WHen I double click on "Generate File" I get a big red "Generate Failed" box. The word "bypass" under the XILINX device should change to the file name and it doesn't. I have attached a snapshot of the impact window showing the console output...</p> FPGA Development: RE: Problem building IndustrialIO project build_lcd_rev_chttp://support.criticallink.com/redmine/boards/12/topics/2866?r=2876#message-28762013-06-26T13:31:54ZMichael Williamson
<p>Not having the tools up in front of me. I think you can put more than one bit file into a configuration PROM (to support chained programming). Once you select the first part, just click cancel for additional parts and move onto the file generation process.</p>
<p>-Mike</p> FPGA Development: RE: Problem building IndustrialIO project build_lcd_rev_chttp://support.criticallink.com/redmine/boards/12/topics/2866?r=2875#message-28752013-06-26T13:22:34ZSteven Hillsteven@shscientific.com
<p>I built a simple project based on files for GPIO_Test from Conor O in the post "Xilinx design suite 14.2 and MDK_2012-08-10" in this forum. This project built with no errors. I imported the .ipf file from the build_lcd_rev_c example and renamed it GPIO_Test, then double-clicked on Manage Configuration Project (following instructions from the "Programming FPGA" post (the first post in this forum). After changing the process options to use this .ipf file, I right clicked on the xc6slx16 device and chose :Assign new configuration file" and then chose the .bit file from the selection window and clicked "Open". A small "OK" window appears and I clicked on that, but was then taken back to the file selection window. This loop could go on forever... I can't get the device to accept the bit file, and there is no information or log file to tell me what is going on...so at this point I have a project that synthesized properly with no errors, but I can't create a proper .bin file to program the FPGA with. Any ideas?</p> FPGA Development: RE: Problem building IndustrialIO project build_lcd_rev_chttp://support.criticallink.com/redmine/boards/12/topics/2866?r=2874#message-28742013-06-26T09:02:23ZGregory Gluszek
<p>Hi Steven,</p>
<p>The issue here is that entity description for the i2c component has changed since the Rev A and B boards. All the code in the "rev_ab : if BOARD_REV = "A" or BOARD_REV = "B" generate" statement is going to be ultimately ignored if you are building for the Rev C. However, even though that code is going to not be generated, the vhdl compiler still does some basic checking of it, hence the compilation failure. So, if you remove all the Rev A and B specific code everything still should build fine. I also did a quick check and just removed the generic map for the i2c component and the build_lcd_rev_c project synthesized correctly, so that is another option if you don't want to risk accidentally removing some code you weren't supposed to.</p>
<p>Please let us know if you have any further issues.</p>
<p>Thanks,<br />\Greg</p> FPGA Development: Problem building IndustrialIO project build_lcd_rev_chttp://support.criticallink.com/redmine/boards/12/topics/28662013-06-25T16:02:44ZSteven Hillsteven@shscientific.com
<p>Following on from a similar question in the forum "Creating FPGA Base-Project - core manager problem" I am trying to build the "build_lcd_rev_c" project. I have used the .vhd files from MDK_2013-05-15/fpga/vhdl and the netlist (.ngc) files from MDK_2013-05-15/fpga/cores/build_spartan6, but the project will not build. The synthesis errors and warnings are attached in a png file.<br />I am tempted to modify IndustrialIO_top.vhd by commenting out all the generation steps based on board revs A and B, but really have no idea what the implications might be.<br />Can anyone help out?</p> FPGA Development: Core Creation Guidelineshttp://support.criticallink.com/redmine/boards/12/topics/28322013-06-23T16:51:12ZSteven Hillsteven@shscientific.com
<p>The link to "FPGA Core Creation Guidelines" appears to be broken in the Wiki - can anyone point me to the relevant information?</p> FPGA Development: RE: Issues programming FPGA using Linux driverhttp://support.criticallink.com/redmine/boards/12/topics/2793?r=2795#message-27952013-06-14T16:35:29ZLars MajlofLars.Majlof@bluehillsconsulting.com
<p>Thanks for the quick reply!<br />I am indeed using a BIN file. It is entirely possible that it is not bit-swapped, it was generated months ago. I will regenerate it to make sure it is formatted properly. <br />Thanks,<br />Lars</p>