Cache and Memory


The MityDSP-L138 / MityDSP-6748 modules include 128MB of DDR RAM. This RAM is located from address 0xC000000 to address 0xC800000. In the 6748 module, all of this memory can be used by the DSP. In the L138 module, this memory must be divided up between the DSP and ARM processor cores.

The Critical Link supplied .tci files include default sets of settings for these platforms. The L138 module sets the memory map to reserve 96MB for the ARM from 0xC0000000 to 0xC5FFFFFF, and 32MB for the DSP from 0xC6000000 to 0xC7FFFFFF. The .tci file includes reasonable starting points for allocation of the DSPLINK memory, as well as the more standard memory blocks required by DSPBios and the TI compiler tools.

The L138 also includes internal RAM resources which can be used by the DSP. These include internal RAM (IRAM section), which is defaulted to 128k, and is located from 0x11800000 to 0x1181FFFF, and "shared RAM" which is 128k and located at 0x80000000 to 0x8001FFFF. Both of these memories are very fast and should be used as working data areas for DSP operations.


To get anything like the performance the DSP is capable of providing, it is critically important to have cache enabled and set up properly. In addition, the user must correctly manage cache coherency.

The cacheability of memory is controlled in the DSP by the MAR registers. These are one-bit registers which indicate whether a given block of memory is to be cached. In most, if not all, instances, the DSP should cache all DDR RAM. The MAR registers are set up to defaults in the .tci file (and can be overridden in the .tcf file). The value in the TCF file is a compacted version of the actual DSP registers, where each 16 MAR registers are compressed into a single word. (It is important to note that the bits in the .tcf MAR register are ordered so that the LSB is the lowest numbered MAR register and the MSB is the highest!) The MAR registers are set using the following commands in the .tcf file:

prog.module("GBL").C64PLUSMAR192to223 = 0xFFFFFFFF ; // all of DDR RAM
prog.module("GBL").C64PLUSMAR128to159 = 0x00000001 ; // shared memory

Any L2 RAM set aside for use as RAM (as opposed to cache) appears to automatically use L1 caching. On the other hand, the internal "shared RAM" does not default to using cache, so we enable cache in this area, as well, in our default .tci file.

Cache Coherency Management

Cache coherency is very important in the C674x core (as in most DSP systems). Data moved around in DDR or internal ram by DMA is typically written and read behind the back of L2 cache. In order for the processor to "see" this data, the processor must invalidate the cache which maps to this area. This is done using the BCACHE_inv() function of DSPBios. Similarly, if data is written by the processor to DDR and you then wish to DMA this data somewhere (to an FPGA, perhaps), you must call BCACHE_wb(). If you can do it, it is best to kick off the invalidate as soon as you can, do some preliminary processing which doesn't access the data, and then call BCACHE_wait() to make sure the cache is all invalidated before you access the data for processing. Cache coherency is also important for DSPLink data, but (I believe) this is taken care of in the DSPLink library.

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