FPGA Interfacing and Interrupts

MityDSP FPGA Interrupt Scheme

The MityDSP FPGA framework includes multiple cores routed through a base module. The base module provides an interrupt controller to manage multiple levels of interrupts within the FGPA. The base module has two sets of interrupt registers, which correspond to two sets of interrupt pins. The pins on the OMAP which are used as interrupt inputs are Bank 6, Pin 12 for interrupt 0 (normally ARM interrupts), and Bank 6, Pin 13 for interrupt 1 (normally DSP interrupts). The FPGA provides IRQ enables for up to 16 levels of interrupt events per interrupt pin, along with an interrupt status register ("INTx Masked IRQs") for each of these levels. When an event occurs for which the enable is set, the FPGA will assert (active high) the OMAP pin for that interrupt, and the corresponding event bit will be set in the IRQ status register. The status bit (and interrupt pin) stays high until the processor interaction with the FPGA causes the interrupt source to clear.

In software, the DSP must map the input pin event to an interrupt vector and plug the dispatcher with an FPGA dispatcher function. This function needs to read the IRQ status register and call the appropriate callbacks. All of this is implemented in our core library.

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