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uPP Design Considerations

This page was created to list a few considerations for designs that incorporate the Universal Parallel Port (uPP). In previous projects certain design choices have led to undesirable behaviors in the uPP. This page should help you to avoid these issues or at least offer insight into what problems may arise if the suggestions below prove to be too restrictive.

uPP Transmit Clocking

When a uPP channel is setup in transmit mode one of three clocks can be selected to run the transmit portion of the unit. It is recommend that PLL0_SYSCLK2 be used, while UPP_2xTXCLK and PLL1_SYSCLK2 be avoided.

The reason for this is that false Underrun or Overflow (UOR) Event triggers are possible as well as potential system lockups when using UPP_2xTXCLK. Similar behavior seen for PLL1_SYSCLK2.

This affects the design in that by using PLL0_SYSCLK2, the transmit clock will be restricted to being a division of 1/4 of the OMAP CPU speed. For example the OMAP CPU is typically run at 300 MHz, resulting in a transmit clock of 75/(N+1) MHz where N must be between 0 and 15. If a transmit clock rate is required that cannot be achieved through use of this divisor, it is advised to use a dual clocked FIFO in the FPGA to achieve the desired transmit rate. One end of the FIFO should be connected to the uPP output, with logic added to pull the uPP wait pin high when FIFO in filled beyond a certain threshold. (Note that the uPP must be setup to honor the wait signal). The other end of the FIFO can be read out at the desired transmit rate, keeping in mind that data must be written into the FIFO faster than it is read out.

UPP Throughput

The maximum bandwidth that Critical Link has utilized the UPP interface at is 75Mhz in single channel mode at 2bytes so 150MB/s.

It is possible to use it in dual channel mode effectively doubling the data rate to 300MB/s. That would allow you a total of 12-channels of 16-bit 10MS/s into the FPGA. Note that the DDR2 memory on for the module is limited to 600 MB/sec (2.4 Gbits/sec) burst throughput. If you do use dual-channel mode than you would need to make sure you are using MII for the Ethernet interface as some of the RMII pins conflict with bits DATA[15:8] of the UPP.

It is reported that it MAY be possible to increase the UPP clock rate up to 25% of the L138 processor speed which could get you to (456 MHz/4) 114MHz but TI currently only states that they actively support the 75MHz clock rate. The following white paper (http://www.criticallink.com/wp-content/uploads/2014/01/sphy007a.pdf) from an SDR that Critical Link was involved in discusses some UPP considerations.

UPP Timing

Timing considerations between the Spartan 6 and L138 should be addressed. This is of primary concern when running at the full data rate (75MHz). Specifically, ensure the data is being registered in the IOB; do not count on the synthesizer to do this automatically. One way to do this is to instantiate an ODDR2 for the output:

out_data : ODDR2
generic map
(
    DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 
    INIT => '0', -- Sets initial state of the Q output to '0' or '1'
    SRTYPE => "SYNC" -- Specifies "SYNC" or "ASYNC" set/reset
)
port map 
(
    Q  => o_upp_cha_data(i), -- 1-bit output data
    C0 => s_o_uPP_cha_clk, -- 1-bit clock input
    C1 => s_o_uPP_cha_clk_n, -- 1-bit clock input
    CE => '1',  -- 1-bit clock enable input
    D0 => s_upp_cha_data(i),   -- 1-bit data input (associated with C0)
    D1 => s_upp_cha_data(i),   -- 1-bit data input (associated with C1)
    R => '0',    -- 1-bit reset input
    S => '0'     -- 1-bit set input
);

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