MitySOM-5CSX Altera Cyclone V: FPGA Developmenthttp://support.criticallink.com/redmine/http://support.criticallink.com/redmine/redmine/favicon.ico?16338348402023-11-16T15:02:12ZCritical Link Support
Redmine FPGA Development: Clock frequency pinshttp://support.criticallink.com/redmine/boards/47/topics/65472023-11-16T15:02:12ZMohammad Hassan Adeli
<p>Hello,</p>
<p>We have this module (<a class="external" href="https://www.criticallink.com/product/mitysom-5csx/">https://www.criticallink.com/product/mitysom-5csx/</a> ) board on our project board and also I have this development kit with the same controller (<a class="external" href="https://www.criticallink.com/product/mitysom-5csx-dev-kit/">https://www.criticallink.com/product/mitysom-5csx-dev-kit/</a>). <br />I tried the Y13 pin with 100MHz for clock frequency. It is working now on the development kit and output is what I expected. However, when I download the same file on the controller itself, in the signal tap logic analyzer I am facing the status of "Waiting for Clock" strangely. In our project board, I powered the circuit with 5V and 3.3V to the corresponding pins. I am assuming the clock frequency is provided internally.</p>
<p>Do you have any idea about this issue? Should I boot the clock externally for the module?</p>
<p>Thanks,<br />Hassan</p> FPGA Development: RE: Link missing on System Design Overview wiki page http://support.criticallink.com/redmine/boards/47/topics/6528?r=6532#message-65322023-10-27T18:10:51ZDaniel Vincelettedvincelette@criticallink.com
<p>Thank you for bringing this to our attention, I've updated the text on that wiki page so it now links to our reference project.</p>
<p>Dan</p> FPGA Development: Link missing on System Design Overview wiki page http://support.criticallink.com/redmine/boards/47/topics/65282023-10-26T02:24:00ZThomas Catalinotom.catalino@criticallink.com
<p>(posted on behalf of a customer)</p>
<p>on this URL:</p>
<p><a class="external" href="https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/System_Design_Overview">https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/System_Design_Overview</a></p>
<p>it says:</p>
<p>"Create a new project or start from the Critical Link MityARM-5CSX reference project <link to file here>"</p>
<p>Note, it says "<link to file here>", but there is no link. Can you please let me know what that project link is?</p> FPGA Development: RE: Differences in 5CSE-L2-3Y8-RC production runs?http://support.criticallink.com/redmine/boards/47/topics/6175?r=6176#message-61762022-03-16T20:21:16ZDaniel Vincelettedvincelette@criticallink.com
<p>Hi Lucas,</p>
<p>That is an interesting finding, I'm not aware of any reports of lot to lot clock instabilities. Are you passing the HPS user clock to the FPGA as your main clock source for your FPGA design or is your FPGA being clocked by an external oscillator that is passed in from your baseboard? If you are feeding a clock from the HPS to the fabric and using that to drive a PLL, Intel does have an application note saying that they don't advise doing so because they did not characterize this case.</p>
<p>Here is the Guidance from Intel AN796</p>
<blockquote>
<p>Cascading PLLs between the FPGA and HPS has not been characterized. Unless you perform the jitter analysis, do not chain the FPGA and HPS PLLs together as a stable clock coming out of the last PLL in the FPGA cannot be guaranteed. Output clocks from the HPS are not intended to be fed into PLLs in the FPGA.</p>
</blockquote>
<p>Does your ADC have a test pattern that it could output, which would help narrow down the issue to the digital interface?</p>
<p>The other thing that I could see change with different SOMs is the FPGA lot, which can have slightly different timing. These different routing delays are handled by quartus in tandem with the project timing constraints. I've run into cases where I messed up my timing constraints (or didn't have any all together) for external interfaces, which made my design work fine on one SOM but have artifacts in the data on another.</p>
<p>Along those lines, in the past I've also run my design in a temperature chamber (both on a "good" unit and "bad" unit) and see if at the high or low end I can change the behaviors.</p>
<p>Dan</p> FPGA Development: Differences in 5CSE-L2-3Y8-RC production runs?http://support.criticallink.com/redmine/boards/47/topics/61752022-03-16T19:33:31ZLucas Uecker
<p>Hello. We've been doing some troubleshooting on prototype units that use the 5CSE-L2-3Y8-RC for DSP on the FPGA end and further treatment on the ARM CPU side and were puzzled by two units with fairly similar behavior on the analog front end have fairly different behavior in final output. At some point we joked about swapping SOM modules to test for differences... and then it turned out that the 'good' and 'meh' results traveled with the SOM modules after all. After some testing with our inventory of 5CSE-L2-3Y8-RC modules, we've found:</p>
<p>Rev C 'batch' 21-06-25: excellent output<br />Rev B 'batch' 19-06-24: not good output<br />Rev C 'batch' 21-08-08: not good output<br />Rev C 'batch' 22-01-07: close to 21-06-25 batch, but not quite as good<br />Rev C 'batch' 20-01-05: similar to 22-01-07<br />Rev C 'batch' 21-04-02: good output</p>
<p>As an example of "good":<br />!MicrosoftTeams-image%20(2).png!</p>
<p>Versus "bad":<br />!MicrosoftTeams-image%20(3).png!</p>
<p>The only reasonable explanation of a difference between modules that I can think of is clock stability as our application involves a lock-in amplifier to monitor power levels at fairly specific frequencies. Any insight would be helpful.</p>
<p>Thanks.</p> FPGA Development: RE: U-Boot Network Setup (MitySOM-5CSX-H6-42A)http://support.criticallink.com/redmine/boards/47/topics/6164?r=6168#message-61682022-01-11T06:17:12ZJose Berlioz
<p>That did it.<br /><pre>
MitySOM-5CSx # ping 192.168.1.1
designware_board_phy_init: enter
Waiting for PHY auto negotiation to complete. done
ENET Speed is 100 Mbps - FULL duplex connection
Using mii0 device
host 192.168.1.1 is alive
</pre></p>
<p>Thanks,<br />Jose</p> FPGA Development: RE: U-Boot Network Setup (MitySOM-5CSX-H6-42A)http://support.criticallink.com/redmine/boards/47/topics/6164?r=6167#message-61672022-01-10T15:10:48ZZachary Millerzmiller@criticallink.com
<p>Hi Jose,</p>
<p>You can make the following changes to the U-Boot environment to enable Ethernet:</p>
<pre>
initphy=gpio clear 28; gpio set 28; sleep 1
preboot=run initphy; run setup_usb; ab1805 cs ${rtccal}
</pre>
<p>You'll also need to set the <code>ipaddr</code> environment variable to assign a static IP to the board.</p>
<p>Note that although the sleep in <code>initphy</code> is only one second, it may take another few seconds for the PHY to actually come up. After that, you should be able to ping/TFTP.</p>
<p>Zach</p> FPGA Development: RE: U-Boot Network Setup (MitySOM-5CSX-H6-42A)http://support.criticallink.com/redmine/boards/47/topics/6164?r=6166#message-61662022-01-10T07:32:24ZJose Berlioz
<p>Hey Mike,<br />Yes, I have a 300Mbps switch, but I can test it in a faster one. I am also testing it in the devkit, not the custom board.</p>
<p>When yocto comes up, it looks like it is able to get to 100Mbps:<br /><pre>
socfpga-dwmac ff702000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx
</pre></p>
<p>and is able to ping too:<br /><pre>
root@mitysom-c5:~# ping 192.168.1.1
PING 192.168.1.1 (192.168.1.1) 56(84) bytes of data.
64 bytes from 192.168.1.1: icmp_seq=1 ttl=64 time=1.35 ms
</pre></p>
<p>I also had issues with my image so I was trying this with the SD Card image given in the CriticalLink website for the 5CSX-42A. The only thing that was changed were adding the ip address environment variables. Can you post the script in here since I can't seem to find it? I can add it manually.</p>
<p>-Jose</p> FPGA Development: RE: U-Boot Network Setup (MitySOM-5CSX-H6-42A)http://support.criticallink.com/redmine/boards/47/topics/6164?r=6165#message-61652022-01-10T03:37:21ZMichael Williamson
<p>Hi Jose,</p>
<p>Are you using a MitySOM-5CSX Development kit board, or a custom carrier board?</p>
<p>The first couple of lines:</p>
<pre>
aiting for PHY auto negotiation to complete............. TIMEOUT!
ENET Speed is 10 Mbps - HALF duplex connection
</pre>
<p>are very suspicious. I assume you are using a switch that is at least 100 Mbps?</p>
<p>This could be because the ethernet reset line is not being asserted or released correctly, or it could indicate other issues with the PHY MII interface to the SOM. I thought that our default u-Boot scripts included GPIO commands to toggle the ethernet reset pin as part of the bootcmd script to ensure the PHY reset with the correct boostrap options (after the SOM was powered). I am not seeing that in your environment. There should be an "initphy" or "initeth" u_boot script command in the stock environment.</p>
<p>-Mike</p> FPGA Development: U-Boot Network Setup (MitySOM-5CSX-H6-42A)http://support.criticallink.com/redmine/boards/47/topics/61642022-01-10T02:27:40ZJose Berlioz
<p>Hello,<br />I was trying to load the kernel and fpga files through a TFTP server. I have to use a static IP for this as a requirement (cant use dhcp).<br />Is there any setup I have to do besides establishing environment variables on U-boot? I can't seem to be able to ping my server or my gateway (192.168.1.1) from my devkit, even though I am able to ping it from Yocto.</p>
<p>I am using a 5CSX-H6-42A Mitysom with the standard CriticalLink image.<br />This is the console message I get when I use ping:</p>
<p>MitySOM-5CSx # ping 192.168.1.1<br />designware_board_phy_init: enter<br />Waiting for PHY auto negotiation to complete............. TIMEOUT!<br />ENET Speed is 10 Mbps - HALF duplex connection<br />Using mii0 device<br />ping failed; host 192.168.1.1 is not alive</p>
<p>This is the environment variables loaded on U-boot:<br />MitySOM-5CSx # printenv<br />autoload=no<br />axibridge=ffd0501c<br />axibridge_handoff=0x00000004<br />baudrate=115200<br />bootargs=console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait<br />bootcmd=run mmcload; run mmcboot<br />bootdelay=5<br />bridge_disable=mw $fpgaintf 0; mw $fpga2sdram 0; go $fpga2sdram_apply; mw $axibridge 0; mw $l3remap 0x1</p>
<p>bridge_enable_handoff=mw $fpgaintf ${fpgaintf_handoff}; go $fpga2sdram_apply; mw $fpga2sdram ${fpga2sdr<br />am_handoff}; mw $axibridge ${axibridge_handoff}; mw $l3remap ${l3remap_handoff}<br />clmodelnum=5CSX-H6-42A-RC<br />ethact=mii0<br />ethaddr=c4:ff:bc:70:39:fd<br />filesize=0x6aebe4<br />fpga=0<br />fpga2sdram=ffc25080<br />fpga2sdram_apply=3ff76598<br />fpga2sdram_handoff=0x00000000<br />fpgaintf=ffd08028<br />fpgaintf_handoff=0x00000000<br />fpgaload=run bridge_disable;fpga load 0 ${loadfpgaaddr} ${loadfpgasize}; run bridge_enable_handoff<br />gatewayip=192.168.1.1<br />ipaddr=192.168.1.103<br />l3remap=ff800000<br />l3remap_handoff=0x00000019<br />loadfdtaddr=0x00000100<br />loadfpgaaddr=0x2000000<br />loadfpgasize=0x700000<br />loadinitramfsaddr=0x3000000<br />loadkerneladdr=0xA000<br />mmcboot=run mmcsetbootargs;run fpgaload;bootz ${loadkerneladdr} - ${loadfdtaddr}<br />mmcextpart=3<br />mmcfatpart=1<br />mmcfdtloc=/boot/socfpga_mitysom5csx_devkit.dtb<br />mmcfpgaloc=/dev_5cs.rbf<br />mmckernelloc=/boot/zImage<br />mmcload=mmc rescan;run mmcloadkernel;run mmcloadfdt;run mmcloadfpga<br />mmcloadfdt=ext2load mmc 0:${mmcextpart} ${loadfdtaddr} ${mmcfdtloc}<br />mmcloadfpga=fatload mmc 0:${mmcfatpart} ${loadfpgaaddr} ${mmcfpgaloc}<br />mmcloadkernel=ext2load mmc 0:${mmcextpart} ${loadkerneladdr} ${mmckernelloc}<br />mmcloadpart=2<br />mmcroot=/dev/mmcblk0p3<br />mmcsetbootargs=setenv bootargs console=ttyS0,115200 root=${mmcroot} rw rootwait<br />netmask=255.255.255.0<br />preboot=run setup_usb; ab1805 cs ${rtccal}<br />qspiboot=run qspisetbootargs;run fpgaload;bootz ${loadkerneladdr} ${loadinitramfsaddr} ${loadfdtaddr}<br />qspifdtloc=0x50000<br />qspifdtsize=0x6000<br />qspifpgaloc=0x8E0000<br />qspiinitfsramloc=0x0<br />qspiinitfsramsize=0x1000000<br />qspikernelloc=0xe0000<br />qspikernelsize=0x600000<br />qspiload=run qspiloadkernel;run qspiloadfdt;run qspiloadfpga;run qspiloadinitramfs<br />qspiloadfdt=sf probe 0; sf read ${loadfdtaddr} ${qspifdtloc} ${qspifdtsize}<br />qspiloadfpga=sf probe 0; sf read ${loadfpgaaddr} ${qspifpgaloc} ${loadfpgasize}<br />qspiloadinitramfs=sf probe 1; sf read ${loadinitramfsaddr} ${qspiinitfsramloc} ${qspiinitfsramsize}<br />qspiloadkernel=sf probe 0; sf read ${loadkerneladdr} ${qspikernelloc} ${qspikernelsize}<br />qspisetbootargs=setenv bootargs console=ttyS0,115200 root=/dev/ram0<br />rtccal=0<br />setup_usb=gpio set 0<br />stderr=serial<br />stdin=serial<br />stdout=serial<br />verify=n</p>
<p>Environment size: 2616/4092 bytes</p>
<p>Thanks,<br />-Jose</p> FPGA Development: RE: U-boot Error Messagehttp://support.criticallink.com/redmine/boards/47/topics/6142?r=6163#message-61632022-01-07T15:54:55ZJose Berlioz
<p>Hey Zach,<br />Thanks for your reply! That worked. I was under the impression I only needed to rebuild the Preloader and U-boot if I changed the HPS.<br />Thanks for clarifying that.</p>
<p>-Jose</p> FPGA Development: RE: U-boot Error Messagehttp://support.criticallink.com/redmine/boards/47/topics/6142?r=6162#message-61622022-01-06T19:38:45ZZachary Millerzmiller@criticallink.com
<p>Hi Jose,</p>
<p>The issue is device tree nodes for FPGA peripherals that don't exist in your FPGA. As a quick-fix, I'm attaching a precompiled device tree you can include in the filesystem to make your SD card boot. You'll want put the device tree in your build location at the path <code>overlay/boot/socfpga_mitysom5csx_devkit.dtb</code>. Then when you run make_sd.sh, add the options <code>-r overlay</code>. So for example the full command would be:</p>
<pre>
./make_sd.sh -d CycloneV -p preloader-mkpimage.bin -u u-boot.img -e ubootenv.bin -f dev_5cs.rbf -r overlay mitysom-image-base-mitysom-c5.tar.gz
</pre>
<hr />
<p>To recompile the device tree yourself, you can follow the instructions here: <a class="wiki-page" href="http://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_kernel_181">Building_kernel_181</a>. Before building the device trees, you'll need to change four lines in <code>arch/arm/boot/dts/socfpga_mitysom5csx_devkit.dts</code>: either delete or comment out the <code>status = "okay";</code> lines for the <code>&can0</code>, <code>&can1</code>, <code>&hps_lw_bus</code>, and <code>&gmac1</code> blocks. I'm also attaching this file with the required changes.</p> FPGA Development: RE: U-boot Error Messagehttp://support.criticallink.com/redmine/boards/47/topics/6142?r=6161#message-61612022-01-06T16:19:26ZJose Berlioz
<p>Hey Zach, <br />I included all three in the SD Card when I rebuild the SD Card. Also, the SOM yellow LED turns off and the green LED turns on.</p>
<p>Sure, I can do that. I am including a zip file with the SD Card Image and the individual files and the make_sd.sh script used.</p>
<p>-Jose</p> FPGA Development: RE: U-boot Error Messagehttp://support.criticallink.com/redmine/boards/47/topics/6142?r=6160#message-61602022-01-05T20:13:19ZZachary Millerzmiller@criticallink.com
<p>Hi Jose,</p>
<p>Thanks for the info. When you rebuilt your SD card image, you included your all three of your new preloader, U-Boot, and FPGA, correct? If there's a mismatch between those three binaries it can cause the kernel to hang like this, particularly when the bridges to the HPS have been changed.</p>
<p>As another sanity check, when it gets to trying to boot the kernel, does the yellow LED on the SOM turn off? (There should still be a green LED next to it that stays on.) Based on your log, I expect the yellow LED to turn off, but if it doesn't, then the FPGA isn't loading properly (which could also cause this hang).</p>
<p>Would it also be possible to zip up your SD card image that hangs and post it here for us to take a look?</p>
<p>Zach</p> FPGA Development: RE: U-boot Error Messagehttp://support.criticallink.com/redmine/boards/47/topics/6142?r=6159#message-61592022-01-05T16:21:54ZJose Berlioz
<p>Hey Zachary,<br />Thanks for your help. Yes, that's as far as it goes. I flashed on a different SD Card and it has the same issue. Also, I can flash it with a working SD card img from criticalLink and that one loads.</p>
<p>Answering your questions:<br />1) I use the xubuntu VM given by criticalLink to run build the preloader and uboot and run the make_sd.sh script. I use Windows to work on Quartus and use the bsp-editor for the handoff, and I use Win32DiskImager to load the image to the SD Card.<br />2) I am using Quartus 18.1<br />3) I rebuilt the fpga and added a 32 bit lwbridge and an 128-bit AXI bus to the HPS, <br />plus the U-boot and preloader following <a class="external" href="https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_uboot_181">https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_uboot_181</a>. Maybe I miss something given that I changed the HPS?</p>
<p>-Jose</p> FPGA Development: RE: U-boot Error Messagehttp://support.criticallink.com/redmine/boards/47/topics/6142?r=6158#message-61582022-01-04T21:07:36ZZachary Millerzmiller@criticallink.com
<p>Great, I'm glad that helped!</p>
<p>Is "starting kernel" as far as it boots? As a quick sanity check, could you try flashing a fresh SD card from the pre-built image on our wiki? There are download links here: <a class="wiki-page" href="http://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Wiki#Variant-Specific">wiki</a> (based on your U-Boot environment, it looks like you want the "5CSX-H6-42A SD Card" link).</p>
<p>Assuming that works, we should be able to work backward and figure out what piece is causing the issue. Could you please also describe your build setup a bit? Namely:</p>
<ol>
<li>Are you on Windows or Linux?</li>
<li>What version of Quartus are you using?</li>
<li>What components of the SD card have you rebuilt (preloader, U-Boot, FPGA)?</li>
</ol> FPGA Development: RE: U-boot Error Messagehttp://support.criticallink.com/redmine/boards/47/topics/6142?r=6157#message-61572022-01-03T22:17:56ZJose Berlioz
<p>Hey Zach,<br />Thanks for the ubootenv.bin file, that seem to have done the trick and I was able to load the fpga image. I seem to have issues with the kernel though.</p>
<p>The console freezes at the end and Yocto never loads. I am using the mitysom-image-base-mitysom-c5.tar.gz provided on the website.</p>
<p>Console Log:<br />U-Boot 2013.01.01 (Dec 02 2021 - 17:38:31) Critical Link MitySOM-5CSx</p>
CPU : Altera SOCFPGA Platform<br />BOARD : Critical Link MitySOM-5CSx Module<br />I2C: ready<br />DRAM: 1 GiB<br />MMC: ALTERA DWMMC: 0<br />In: serial<br />Out: serial<br />Err: serial<br />Net: mii0<br />gpio: pin 0 (bank/mask = 0/0x00000001)<br />gpio: pin 0 (gpio 0) value is 1<br />Hit any key to stop autoboot: 0<br />4078608 bytes read in 235 ms (16.6 MiB/s)<br />21795 bytes read in 36 ms (590.8 KiB/s)<br />reading /dev_5cs.rbf<br />7007204 bytes read in 330 ms (20.2 MiB/s)
<ol>
<li>Starting application at 0x3FF75598 ...</li>
<li>Application terminated, rc = 0x0</li>
<li>Starting application at 0x3FF75598 ...</li>
<li>Application terminated, rc = 0x0</li>
<li>Flattened Device Tree blob at 00000100<br /> Booting using the fdt blob at 0x00000100<br /> Loading Device Tree to 03ff7000, end 03fff522 ... OK</li>
</ol>
<p>Starting kernel ...</p> FPGA Development: RE: U-boot Error Messagehttp://support.criticallink.com/redmine/boards/47/topics/6142?r=6154#message-61542021-12-16T16:08:09ZZachary Millerzmiller@criticallink.com
<p>Hi Jose,</p>
<p>I think your U-Boot environment may have become corrupted somehow: the "bad partition specification" error can occur when the partition number doesn't parse correctly. Since it <em>looks</em> right in the error message, I suspect there may be invisible control characters in the <code>mmcextpart</code> variable.</p>
<p>You'll most likely need to reflash your SD card (or at least the U-Boot environment: <a class="wiki-page" href="http://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_sd_181#Updating-the-U-Boot-environment">Building_sd_181</a>). It looks like you're using our stock U-Boot environment, so I'm attaching a known-good <code>ubootenv.bin</code> you can use for reflashing.</p>
<p>If you were editing environment variables at all from U-Boot (with <code>editenv</code> or <code>setenv</code>), this could also have happened by hitting a key U-Boot doesn't handle well (e.g., the function keys).</p>
<p>Zach</p> FPGA Development: RE: U-boot Error Messagehttp://support.criticallink.com/redmine/boards/47/topics/6142?r=6146#message-61462021-12-14T17:21:59ZJose Berlioz
<p>Hey Daniel,<br />Thanks for the help.</p>
<p>This is the full log:</p>
<blockquote>
<p>U-Boot SPL 2013.01.01 (Nov 17 2021 - 15:25:35)<br />BOARD : Critical Link MitySOM-5CSx Module<br />CLOCK: EOSC1 clock 25000 KHz<br />CLOCK: EOSC2 clock 25000 KHz<br />CLOCK: F2S_SDR_REF clock 0 KHz<br />CLOCK: F2S_PER_REF clock 0 KHz<br />CLOCK: MPU clock 800 MHz<br />CLOCK: DDR clock 400 MHz<br />CLOCK: UART clock 100000 KHz<br />CLOCK: MMC clock 50000 KHz<br />CLOCK: QSPI clock 400000 KHz<br />RESET: COLD<br />INFO : Watchdog enabled<br />SDRAM: Initializing MMR registers<br />SDRAM: Calibrating PHY<br />SEQ.C: Preparing to start memory calibration<br />SEQ.C: CALIBRATION PASSED<br />SDRAM: 1024 MiB<br />SDRAM: Initializing SDRAM ECC<br />SDRAM: ECC initialized successfully with 1510 ms<br />SDRAM: ECC Enabled<br />ALTERA DWMMC: 0</p>
<p>U-Boot 2013.01.01 (Nov 17 2021 - 15:27:31) Critical Link MitySOM-5CSx</p>
<p>CPU : Altera SOCFPGA Platform<br />BOARD : Critical Link MitySOM-5CSx Module<br />I2C: ready<br />DRAM: 1 GiB<br />MMC: ALTERA DWMMC: 0<br />In: serial<br />Out: serial<br />Err: serial<br />Info - Didn't find block<br />Net: mii0<br />gpio: pin 0 (bank/mask = 0/0x00000001)<br />(gpio 0) value is 1<br />Hit any key to stop autoboot: 0<br />*<strong>Bad partition specification mmc 0:3<br /></strong>*Bad partition specification mmc 0:3<br />" not definedcloadfpga<br />" not definedcboot</p>
</blockquote>
<p>I posted the UbootEnv.txt file. This is the print env output.</p>
<blockquote>
<p>MitySOM-5CSx # printenv<br />autoload=no<br />axibridge=ffd0501c<br />axibridge_handoff=0x00000004<br />baudrate=115200<br />bootargs=console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait<br />bootcmd=run mmcload; run mmcboot<br />bootdelay=5<br />bridge_disable=mw $fpgaintf 0; mw $fpga2sdram 0; go $fpga2sdram_apply; mw $axibr<br />idge 0; mw $l3remap 0x1<br />bridge_enable_handoff=mw $fpgaintf ${fpgaintf_handoff}; go $fpga2sdram_apply; mw<br />$fpga2sdram ${fpga2sdram_handoff}; mw $axibridge ${axibridge_handoff}; mw $l3re<br />map ${l3remap_handoff}<br />clmodelnum=5CSX-H6-42A-RC<br />ethact=mii0<br />ethaddr=c4:ff:bc:70:41:48<br />fpga=0<br />fpga2sdram=ffc25080<br />fpga2sdram_apply=3ff75598<br />fpga2sdram_handoff=0x00000000<br />fpgaintf=ffd08028<br />fpgaintf_handoff=0x00000000<br />fpgaload=run bridge_disable;fpga load 0 ${loadfpgaaddr} ${loadfpgasize}; run bri<br />dge_enable_handoff<br />l3remap=ff800000<br />l3remap_handoff=0x00000019<br />loadfdtaddr=0x00000100<br />loadfpgaaddr=0x2000000<br />loadfpgasize=0x700000<br />loadinitramfsaddr=0x3000000<br />loadkerneladdr=0xA000<br />mmcboot=run mmcsetbootargs;run fpgaload;bootz ${loadkerneladdr} - ${loadfdtaddr}<br />mmcextpart=3<br />mmcfatpart=1<br />mmcfdtloc=/boot/socfpga_mitysom5csx_devkit.dtb<br />mmcfpgaloc=/dev_5cs.rbf<br />mmckernelloc=/boot/zImage<br />mmcload=mmc rescan;run mmcloadkernel;run mmcloadfdt;run mmcloadfpga<br />mmcloadfdt=ext2load mmc 0:${mmcextpart} ${loadfdtaddr} ${mmcfdtloc}<br />mmcloadfpga=fatload mmc 0:${mmcfatpart} ${loadfpgaaddr} ${mmcfpgaloc}<br />mmcloadkernel=ext2load mmc 0:${mmcextpart} ${loadkerneladdr} ${mmckernelloc}<br />mmcloadpart=2<br />mmcroot=/dev/mmcblk0p3<br />mmcsetbootargs=setenv bootargs console=ttyS0,115200 root=${mmcroot} rw rootwait<br />preboot=run setup_usb; ab1805 cs ${rtccal}<br />qspiboot=run qspisetbootargs;run fpgaload;bootz ${loadkerneladdr} ${loadinitramf<br />saddr} ${loadfdtaddr}<br />qspifdtloc=0x50000<br />qspifdtsize=0x6000<br />qspifpgaloc=0x8E0000<br />qspiinitfsramloc=0x0<br />qspiinitfsramsize=0x1000000<br />qspikernelloc=0xe0000<br />qspikernelsize=0x600000<br />qspiload=run qspiloadkernel;run qspiloadfdt;run qspiloadfpga;run qspiloadinitram<br />fs<br />qspiloadfdt=sf probe 0; sf read ${loadfdtaddr} ${qspifdtloc} ${qspifdtsize}<br />qspiloadfpga=sf probe 0; sf read ${loadfpgaaddr} ${qspifpgaloc} ${loadfpgasize}<br />qspiloadinitramfs=sf probe 1; sf read ${loadinitramfsaddr} ${qspiinitfsramloc} $
{qspiinitfsramsize}<br />qspiloadkernel=sf probe 0; sf read ${loadkerneladdr} ${qspikernelloc} ${qspikern<br />elsize}<br />qspisetbootargs=setenv bootargs console=ttyS0,115200 root=/dev/ram0<br />rtccal=0<br />setup_usb=gpio set 0<br />stderr=serial<br />stdin=serial<br />stdout=serial<br />verify=n</p>
<p>Environment size: 2567/4092 bytes</p>
</blockquote>
<p>-Jose</p> FPGA Development: RE: U-boot Error Messagehttp://support.criticallink.com/redmine/boards/47/topics/6142?r=6143#message-61432021-12-10T20:30:46ZDaniel Vincelettedvincelette@criticallink.com
<p>Hi Jose,</p>
<p>I'm going to need a bit more info to help you get further. Can you provide your full console log? Also is the ubootenv you provided a copy and pasted from the uBootMMCEnv.txt file or is it the print out of running "print env" from u-boot? If it's a copy and paste from the text file could you also provide the output of running "print env" in your console log.</p>
<p>Thank you!<br />Dan</p> FPGA Development: U-boot Error Messagehttp://support.criticallink.com/redmine/boards/47/topics/61422021-12-07T21:27:35ZJose Berlioz
<p>Hello,<br />I am new to the HPS system and I was going through the guide for making U-boot and SD card provided after creating a design file in Quartus, but I always get the error message attached below. Have you encountered this error and can you provide some guidance?</p>
<p>Here's my UbootEnv:<br />autoload=no<br />bootdelay=5<br />baudrate=115200<br />bootargs=console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait<br />bootcmd=run mmcload; run mmcboot<br />verify=n<br />preboot=run setup_usb; ab1805 cs ${rtccal}<br />setup_usb=gpio set 0<br />loadfdtaddr=0x00000100<br />loadkerneladdr=0xA000<br />loadinitramfsaddr=0x3000000<br />loadfpgaaddr=0x2000000<br />loadfpgasize=0x700000<br />fpgaload=run bridge_disable;fpga load 0 ${loadfpgaaddr} ${loadfpgasize}; run bridge_enable_handoff<br />fpga=0<br />mmcboot=run mmcsetbootargs;run fpgaload;bootz ${loadkerneladdr} - ${loadfdtaddr}<br />mmcextpart=3<br />mmcfatpart=1<br />mmcsetbootargs=setenv bootargs console=ttyS0,115200 root=${mmcroot} rw rootwait<br />mmcload=mmc rescan;run mmcloadkernel;run mmcloadfdt;run mmcloadfpga<br />mmcloadkernel=ext2load mmc 0:${mmcextpart} ${loadkerneladdr} ${mmckernelloc}<br />mmcloadfdt=ext2load mmc 0:${mmcextpart} ${loadfdtaddr} ${mmcfdtloc}<br />mmcloadfpga=fatload mmc 0:${mmcfatpart} ${loadfpgaaddr} ${mmcfpgaloc}<br />mmcloadpart=2<br />mmcroot=/dev/mmcblk0p3<br />mmcfdtloc=/boot/socfpga_mitysom5csx_devkit.dtb<br />mmckernelloc=/boot/zImage<br />mmcfpgaloc=/dev_5cs.rbf<br />qspiboot=run qspisetbootargs;run fpgaload;bootz ${loadkerneladdr} ${loadinitramfsaddr} ${loadfdtaddr}<br />qspisetbootargs=setenv bootargs console=ttyS0,115200 root=/dev/ram0<br />qspikernelloc=0xe0000<br />qspikernelsize=0x600000<br />qspifdtloc=0x50000<br />qspifdtsize=0x6000<br />qspifpgaloc=0x8E0000<br />qspiinitfsramloc=0x0<br />qspiinitfsramsize=0x1000000<br />qspiload=run qspiloadkernel;run qspiloadfdt;run qspiloadfpga;run qspiloadinitramfs<br />qspiloadkernel=sf probe 0; sf read ${loadkerneladdr} ${qspikernelloc} ${qspikernelsize}<br />qspiloadfdt=sf probe 0; sf read ${loadfdtaddr} ${qspifdtloc} ${qspifdtsize}<br />qspiloadfpga=sf probe 0; sf read ${loadfpgaaddr} ${qspifpgaloc} ${loadfpgasize}<br />qspiloadinitramfs=sf probe 1; sf read ${loadinitramfsaddr} ${qspiinitfsramloc} ${qspiinitfsramsize}</p>
<p>clipboard-202112071514-ehzba.png</p> FPGA Development: RE: Using Signal Tap with the L2-3Y8 dev kithttp://support.criticallink.com/redmine/boards/47/topics/6064?r=6065#message-60652021-04-30T14:01:58ZDaniel Vincelettedvincelette@criticallink.com
<p>Hi Travis,</p>
<p>I'm sorry for the long delay, are still seeing issues with SignalTap? My normal flow for SignalTap debug especially if the HPS is accessing cores on the bridges is to convert my SOF to a RBF and have u-boot program it on boot. After that I then signal tap connect instead of using it to program the FPGA.</p>
<p>Also please note that we have found an issue with some JTAG pods reseting the HPS on connection. In order to fix this problem you might need to cut off one of the pins on the JTAG adapter board that we supply with the dev kit. For more information on that please take a look at the following wiki: <a class="external" href="https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Module_Debug_Connection#JTAG-Only-Adapter-80-000616">https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Module_Debug_Connection#JTAG-Only-Adapter-80-000616</a></p>
<p>Best regards,<br />Dan</p> FPGA Development: Using Signal Tap with the L2-3Y8 dev kithttp://support.criticallink.com/redmine/boards/47/topics/60642021-04-19T22:17:05ZTravis Rawson
<p>Hello,</p>
<p>I am trying to get Signal Tap working on the my system, but I keep running into failures. I am able to connect a usb-blaster device to the JTAG pins on the white connector. I am also able to find the hardware (usb-blaster) and the device (@1: 5CSE(BA2|MA2)/5CSXFC2C6) inside of Signal Tap. Whenever I go to download the sof onto the board, the FPGA seems like it gets reprogrammed only when I stop the dev board from fully booting. Even when it seems like it programs correctly, Signal Tap always comes back with an error of some kind.</p>
<p>My questions are: <br />1) Is there some state I need to put the dev board in to work with Signal Tap, or letting it fully boot is fine?<br />2) Are there some setting I need to do in Signal Tap to make it work with the Cyclone V/MitySOM dev board, or do I need to seek out some other source to help with the Signal Tap errors?</p>
<p>Thanks for all the help so far!</p> FPGA Development: RE: Coldstart problem. Loading FPGA through Linux.http://support.criticallink.com/redmine/boards/47/topics/6062?r=6063#message-60632021-04-19T16:08:34ZDaniel Vincelettedvincelette@criticallink.com
<p>Hello,</p>
<p>I don't believe the RTC error message is related to the FPGA not programming. Can you post a boot log when trying to boot at -40°C? Also just to double-check are you using an industrial temp SD card?</p>
<p>Best regards,<br />Dan</p> FPGA Development: Coldstart problem. Loading FPGA through Linux.http://support.criticallink.com/redmine/boards/47/topics/60622021-04-19T15:09:50ZSergey Volkovoy
<p>Hello everyone,</p>
<p>we use the MitySOM module in our project. In works perfectly fine down to -40°C but only if the FPGA is booted at the ambient temperature above 0°C. The HPS part is not used in the project, it`s needed only for booting from SD card. <br />I connected the cable to UART0 of the HPS and I found that if the ambient temperature is lower then 0°C we have an error with RTC.</p>
<p>mousedev: PS/2 mouse device common for all mice␍␊<br />rtc-ab18xx: probe of 0-0069 failed with error -5␍␊<br />i2c /dev entries driver␍␊<br />lm73 0-004c: sensor 'lm73'␍␊</p>
<p>and further:</p>
<p>hwclock: can't open '/dev/misc/rtc': No such file or directory</p>
<p>could it be that because of this we have an issue with downloading or starting the FPGA part?</p>
<p>we use the industry grade module and the RTC is not really needed for the proper operation.</p> FPGA Development: RE: HSMC Control http://support.criticallink.com/redmine/boards/47/topics/6055?r=6057#message-60572021-02-19T16:40:26ZTravis Rawson
<p>Wow, I can't believe I overlooked that. Yes, I had it on the wrong HSMC connector. All is working perfectly now.</p>
<p>Thanks for the help!</p> FPGA Development: RE: HSMC Control http://support.criticallink.com/redmine/boards/47/topics/6055?r=6056#message-60562021-02-17T20:59:40ZDaniel Vincelettedvincelette@criticallink.com
<p>Hi Travis,</p>
<p>We don't have a module or IP for the HSMC connectors. Though in the mitysom-5csx-ref project, all of HSMC pins do go to soft GPIO controllers that can be toggled from the processor.</p>
I have a few things to double check/try:
<ul>
<li>In the pin planner, verify that HSMC1_RX13 is going to PIN_T11</li>
<li>Is the daughter card connected to the HSMC connector on the dev kit that says Full HSMC connector?</li>
<li>Does the pin number on the daughterboard HSMC schematic match the number on our dev kit? I only ask because I've seen some manufactures have slightly different number schemes.</li>
</ul>
<p>Dan</p> FPGA Development: HSMC Control http://support.criticallink.com/redmine/boards/47/topics/60552021-02-17T19:24:55ZTravis Rawson
<p>Hello,</p>
<p>I am trying to control the HSMC on my dev board(5csx). We have a in house created daughter board that we would like to control, but I am having a hard time controlling the HSMC. Is there some module for the Platform Designer or IP that I can download and use? The end goal is to read from an ADC on the board, but at this point I am simply trying to turn a pin on/off so I can use the test points we have.</p>
<p>I am using the "mitysom-5csx-ref" project as a base at the moment, and inside I have tried the following to no luck:<br />HSMC1_RX13 <= '1';</p>
<p>We have pins 13-16(both p and n) directly attached to test points.</p>
<p>Any help would be great!</p> FPGA Development: RE: I2C Controllerhttp://support.criticallink.com/redmine/boards/47/topics/5361?r=6054#message-60542021-02-08T22:09:33ZEvgeny Galyaev
<p>Dear Harrison -<br />We are having the same issues, cannot find it.<br />What was the problem with your scripts, would you please share - maybe it will help.</p>
<p>Thank you, best -<br />Evgeny.</p> FPGA Development: RE: Problem when programming FPGA from HPShttp://support.criticallink.com/redmine/boards/47/topics/5793?r=6049#message-60492020-12-24T12:16:51ZVladislav Borchsh
<p>Confirmed. After rebuilding Kernel (tested on 3.16 and 4.9.78 versions) and disabling gpio_altera modules FPGA programming is able without HPS stucking.</p>
<p>Thanks.</p> FPGA Development: RE: Problem when programming FPGA from HPShttp://support.criticallink.com/redmine/boards/47/topics/5793?r=6048#message-60482020-12-23T07:00:54ZVladislav Borchsh
<p>Hello Daniel,</p>
<p>Yes, I have. Ok, I'll try to do your recommendation, thanks.</p> FPGA Development: RE: Problem when programming FPGA from HPShttp://support.criticallink.com/redmine/boards/47/topics/5793?r=6047#message-60472020-12-22T23:29:30ZDaniel Vincelettedvincelette@criticallink.com
<p>Hello,</p>
<p>In your design do you have kernel drivers that are accessing FPGA cores using the HPS to FPGA lightweight bridge? If so then you will need to have these drivers built as kernel modules and unload them before you try to reprogram the FPGA. For example, the reference designs for our SOMs use soft PIO cores that use drivers that are built into the kernel, the kernel would need to be updated to build the Intel PIO driver as a module instead.</p>
<p>Dan</p> FPGA Development: RE: Problem when programming FPGA from HPShttp://support.criticallink.com/redmine/boards/47/topics/5793?r=6046#message-60462020-12-22T07:16:05ZVladislav Borchsh
<p>Dear colleagues,</p>
<p>Are there any solutions of issue with "hot" JTAG FPGA programming? This feature very useful for me, as FPGA developer.</p>
<p>I faced with exactly the same issue: when I start loading FPGA, HPS will stucked. No matter how I do it: through JTAG or HPS fpga manager. No matter the bridges status.<br />In other hand, I have a few Altera evaluation boards (de0, de10, socrates) and there are no problem with FPGA loading on-fly for each of them.</p>
<p>PS. I've used the same version: MitySOM-5CSX-H6-42A with additional DDR for FPGA. And I tried different designs: first - default version of project, and second version - just pure HPS with exactly the same periphery & sdram settings.</p>
<p>Thanks.</p> FPGA Development: RE: Quartus v20.1 errors building mitysom 5csx projecthttp://support.criticallink.com/redmine/boards/47/topics/6036?r=6039#message-60392020-09-09T23:43:40ZAlexander Blockalex.block@criticallink.com
<p>Tristan,</p>
<p>I wanted to let you know that I installed Quartus Lite 20.1 and attempted to build the FPGA project per our Wiki instructions. I got to the same exact point and error as you. It appears, in my case, that if I manually run the Nios II Command Shell from a CMD prompt I am notified that 'wsl' is not recognized, see attached image.</p>
<p>If your issue is the same as mine then you need to be using an updated version of Windows 10 and install the WSL tools per this instruction from Intel (<a class="external" href="https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/tools/2019/how-do-i-install-the-windows--subsystem-for-linux---wsl--on-wind.html">https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/tools/2019/how-do-i-install-the-windows--subsystem-for-linux---wsl--on-wind.html</a>). At that point you can reboot and try the build again.</p>
<p>Unfortunately it appears that WSL is not supported in Windows 7.</p>
<p>Let me know if you still hit a road block further along the build process.</p>
<p>Alex</p> FPGA Development: RE: Quartus v20.1 errors building mitysom 5csx projecthttp://support.criticallink.com/redmine/boards/47/topics/6036?r=6038#message-60382020-09-09T21:49:54ZTristan Aldinger
<p>I also get these errors when generating the Platform Designer VHDL:<br />Info: m0: "fpga_ddr" instantiated altera_mem_if_ddr3_afi_mux "m0" <br />Error: s0: Error during execution of "{C:/intelfpga/20.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally<br />Error: s0: Execution of command "{C:/intelfpga/20.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed<br />Error: s0: child process exited abnormally<br />Error: s0: Cannot find sequencer/sequencer.elf<br />Error: s0: An error occurred<br /> while executing<br />"error "An error occurred"" <br /> (procedure "_error" line 8)<br /> invoked from within<br />"_error "Cannot find $seq_file"" <br /> ("if" then script line 2)<br /> invoked from within<br />"if {[file exists $seq_file] == 0} {<br /> _error "Cannot find $seq_file" <br /> }" <br /> (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)<br /> invoked from within<br />"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"" <br /> invoked from within<br />"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]" <br /> ("if" then script line 2)<br /> invoked from within<br />"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {<br /> set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..." <br /> (procedure "generate_qsys_sequencer_sw" line 943)<br /> invoked from within<br />"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..." <br /> invoked from within<br />"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..." <br /> ("if" else script line 2)<br /> invoked from within<br />"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {<br /> set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..." <br /> (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)<br /> invoked from within<br />"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}" <br /> invoked from within<br />"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]" <br /> (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)<br /> invoked from within<br />"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH" <br /> invoked from within<br />"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] {<br /> set file_name [file tail $genera..." <br /> (procedure "generate_synth" line 8)<br /> invoked from within<br />"generate_synth mitysom_5csx_dev_board_fpga_ddr_s0" <br />Info: s0: "fpga_ddr" instantiated altera_mem_if_ddr3_qseq "s0" <br />Error: Generation stopped, 250 or more modules remaining<br />Info: mitysom_5csx_dev_board: Done "mitysom_5csx_dev_board" with 86 modules, 75 files<br />Error: qsys-generate failed with exit code 1: 6 Errors, 11 Warnings</p> FPGA Development: Quartus v20.1 errors building mitysom 5csx projecthttp://support.criticallink.com/redmine/boards/47/topics/60362020-09-09T21:40:46ZTristan Aldinger
<p>I am trying to load the provided DEV_5CSX_H6_42A project in Quartus v20.1 Standard and compile the design to insert my own FPGA code.</p>
<p>However, I cannot get past these errors related to the Qsys/Platform designer:<br />Error (12006): Node instance "s0" instantiates undefined entity "dev_5csx_h6_42a_fpga_ddr_s0". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "dmaster" instantiates undefined entity "dev_5csx_h6_42a_fpga_ddr_dmaster". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "c0" instantiates undefined entity "dev_5csx_h6_42a_fpga_ddr_c0". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "oct0" instantiates undefined entity "altera_mem_if_oct_cyclonev". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "dll0" instantiates undefined entity "altera_mem_if_dll_cyclonev". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mm_interconnect_0" instantiates undefined entity "dev_5csx_h6_42a_fpga_ddr_mm_interconnect_0". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "fpga_interfaces" instantiates undefined entity "dev_5csx_h6_42a_hps_0_fpga_interfaces". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "hps_io" instantiates undefined entity "dev_5csx_h6_42a_hps_0_hps_io". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mm_clock_crossing_bridge_0_s0_translator" instantiates undefined entity "altera_merlin_slave_translator". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "hps_0_h2f_axi_master_agent" instantiates undefined entity "altera_merlin_axi_master_ni". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mm_clock_crossing_bridge_0_s0_agent" instantiates undefined entity "altera_merlin_slave_agent". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mm_clock_crossing_bridge_0_s0_agent_rsp_fifo" instantiates undefined entity "altera_avalon_sc_fifo". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mm_clock_crossing_bridge_0_s0_agent_rdata_fifo" instantiates undefined entity "altera_avalon_sc_fifo". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "router" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_0_router". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "router_001" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_0_router". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "router_002" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_0_router_002". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mm_clock_crossing_bridge_0_s0_burst_adapter" instantiates undefined entity "altera_merlin_burst_adapter". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "cmd_demux" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_0_cmd_demux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "cmd_demux_001" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_0_cmd_demux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "cmd_mux" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_0_cmd_mux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "rsp_demux" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_0_rsp_demux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "rsp_mux" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_0_rsp_mux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "rsp_mux_001" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_0_rsp_mux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "agent_pipeline" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "agent_pipeline_001" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_001" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_002" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_003" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "avalon_st_adapter" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_0_avalon_st_adapter". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "sysid_qsys_control_slave_translator" instantiates undefined entity "altera_merlin_slave_translator". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "pio_0_s1_translator" instantiates undefined entity "altera_merlin_slave_translator". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "pio_1_s1_translator" instantiates undefined entity "altera_merlin_slave_translator". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "pio_2_s1_translator" instantiates undefined entity "altera_merlin_slave_translator". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "pio_3_s1_translator" instantiates undefined entity "altera_merlin_slave_translator". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "hps_0_h2f_lw_axi_master_agent" instantiates undefined entity "altera_merlin_axi_master_ni". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "sysid_qsys_control_slave_agent" instantiates undefined entity "altera_merlin_slave_agent". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "sysid_qsys_control_slave_agent_rsp_fifo" instantiates undefined entity "altera_avalon_sc_fifo". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "sysid_qsys_control_slave_agent_rdata_fifo" instantiates undefined entity "altera_avalon_sc_fifo". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "pio_0_s1_agent" instantiates undefined entity "altera_merlin_slave_agent". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "pio_0_s1_agent_rsp_fifo" instantiates undefined entity "altera_avalon_sc_fifo". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "pio_0_s1_agent_rdata_fifo" instantiates undefined entity "altera_avalon_sc_fifo". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "pio_1_s1_agent" instantiates undefined entity "altera_merlin_slave_agent". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "pio_1_s1_agent_rsp_fifo" instantiates undefined entity "altera_avalon_sc_fifo". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "pio_1_s1_agent_rdata_fifo" instantiates undefined entity "altera_avalon_sc_fifo". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "pio_2_s1_agent" instantiates undefined entity "altera_merlin_slave_agent". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "pio_2_s1_agent_rsp_fifo" instantiates undefined entity "altera_avalon_sc_fifo". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "pio_2_s1_agent_rdata_fifo" instantiates undefined entity "altera_avalon_sc_fifo". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "pio_3_s1_agent" instantiates undefined entity "altera_merlin_slave_agent". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "pio_3_s1_agent_rsp_fifo" instantiates undefined entity "altera_avalon_sc_fifo". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "pio_3_s1_agent_rdata_fifo" instantiates undefined entity "altera_avalon_sc_fifo". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "router" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_1_router". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "router_001" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_1_router". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "router_002" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_1_router_002". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "router_003" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_1_router_002". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "router_004" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_1_router_002". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "router_005" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_1_router_002". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "router_006" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_1_router_002". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "hps_0_h2f_lw_axi_master_wr_limiter" instantiates undefined entity "altera_merlin_traffic_limiter". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "hps_0_h2f_lw_axi_master_rd_limiter" instantiates undefined entity "altera_merlin_traffic_limiter". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "sysid_qsys_control_slave_burst_adapter" instantiates undefined entity "altera_merlin_burst_adapter". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "pio_0_s1_burst_adapter" instantiates undefined entity "altera_merlin_burst_adapter". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "pio_1_s1_burst_adapter" instantiates undefined entity "altera_merlin_burst_adapter". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "pio_2_s1_burst_adapter" instantiates undefined entity "altera_merlin_burst_adapter". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "pio_3_s1_burst_adapter" instantiates undefined entity "altera_merlin_burst_adapter". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "cmd_demux" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_1_cmd_demux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "cmd_demux_001" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_1_cmd_demux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "cmd_mux" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_1_cmd_mux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "cmd_mux_001" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_1_cmd_mux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "cmd_mux_002" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_1_cmd_mux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "cmd_mux_003" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_1_cmd_mux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "cmd_mux_004" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_1_cmd_mux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "rsp_demux" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_1_rsp_demux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "rsp_demux_001" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_1_rsp_demux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "rsp_demux_002" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_1_rsp_demux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "rsp_demux_003" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_1_rsp_demux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "rsp_demux_004" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_1_rsp_demux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "rsp_mux" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_1_rsp_mux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "rsp_mux_001" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_1_rsp_mux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "limiter_pipeline" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "limiter_pipeline_001" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "limiter_pipeline_002" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "limiter_pipeline_003" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "agent_pipeline" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "agent_pipeline_001" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "agent_pipeline_002" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "agent_pipeline_003" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "agent_pipeline_004" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "agent_pipeline_005" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "agent_pipeline_006" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "agent_pipeline_007" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "agent_pipeline_008" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "agent_pipeline_009" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_001" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_002" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_003" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_004" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_005" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_006" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_007" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_008" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_009" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_010" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_011" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_012" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_013" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_014" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_015" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_016" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_017" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_018" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_019" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "avalon_st_adapter" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_0_avalon_st_adapter". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "avalon_st_adapter_001" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_0_avalon_st_adapter". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "avalon_st_adapter_002" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_0_avalon_st_adapter". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "avalon_st_adapter_003" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_0_avalon_st_adapter". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "avalon_st_adapter_004" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_0_avalon_st_adapter". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mm_clock_crossing_bridge_0_m0_translator" instantiates undefined entity "altera_merlin_master_translator". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "fpga_ddr_avl_translator" instantiates undefined entity "altera_merlin_slave_translator". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mm_clock_crossing_bridge_0_m0_agent" instantiates undefined entity "altera_merlin_master_agent". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "fpga_ddr_avl_agent" instantiates undefined entity "altera_merlin_slave_agent". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "fpga_ddr_avl_agent_rsp_fifo" instantiates undefined entity "altera_avalon_sc_fifo". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "router" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_2_router". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "router_001" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_2_router_001". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "cmd_demux" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_2_cmd_demux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "cmd_mux" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_2_cmd_mux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "rsp_demux" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_2_cmd_demux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "rsp_mux" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_2_rsp_mux". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "agent_pipeline" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "agent_pipeline_001" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "mux_pipeline_001" instantiates undefined entity "altera_avalon_st_pipeline_stage". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error (12006): Node instance "avalon_st_adapter" instantiates undefined entity "dev_5csx_h6_42a_mm_interconnect_0_avalon_st_adapter". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.<br />Error: Quartus Prime Analysis & Synthesis was unsuccessful. 134 errors, 2 warnings<br /> Error: Peak virtual memory: 4974 megabytes<br /> Error: Processing ended: Wed Sep 09 17:09:47 2020<br /> Error: Elapsed time: 00:01:31<br /> Error: Total CPU time (on all processors): 00:01:35</p> FPGA Development: RE: Quartus Device id for mitySOM 5CSE-H4-3YA-RI-NDhttp://support.criticallink.com/redmine/boards/47/topics/6034?r=6035#message-60352020-09-02T21:38:07ZDaniel Vincelettedvincelette@criticallink.com
<p>Hello,</p>
<p>The device type is 5CSEBA4U23I7</p>
<p>Dan</p> FPGA Development: Quartus Device id for mitySOM 5CSE-H4-3YA-RI-NDhttp://support.criticallink.com/redmine/boards/47/topics/60342020-09-02T21:30:42ZPablo Camacho
<p>What is the device id for Quartus for mitySOM 5CSE-H4-3YA-RI-ND?</p> FPGA Development: mitySom 5csx and opencl 19.1http://support.criticallink.com/redmine/boards/47/topics/60232020-06-17T09:04:41ZMatthieu Moretti
<p>Hello,</p>
<p>I have a MitySom 5csx and I am trying to run the opencl helloworld program described here:</p>
<p><a class="external" href="https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/MitySOM-5CSX_DevKit_OpenCL_BSP">https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/MitySOM-5CSX_DevKit_OpenCL_BSP</a>,</p>
<p>The version I want to use is <a href="https://fpgasoftware.intel.com/opencl/19.1/?edition=standard&download_manager=direct" class="external">Intel FPGA SDK for OpenCL standard 19.1</a></p>
<p>I saw on your tutorial that the release support opencl 16 and 17, what kind of modification I have to do in order to make it works with opencl 19.1 ?</p>
<p>Thank you,</p>
<p>Matthieu</p> FPGA Development: RE: FPGA programming problemshttp://support.criticallink.com/redmine/boards/47/topics/6004?r=6018#message-60182020-05-27T15:33:23ZDario Russo
<p>I will do that.<br />Thank you very much Dan.</p>
<p>Dario</p> FPGA Development: RE: FPGA programming problemshttp://support.criticallink.com/redmine/boards/47/topics/6004?r=6017#message-60172020-05-27T14:33:34ZDaniel Vincelettedvincelette@criticallink.com
<p>Hi Dario,</p>
<p>You could also try using the "sync" linux command after you copy the rbf over. That should flush anything out to the SD card. I normally do a sync and a reboot after updating the RBF. Seeing as the filesystem is read/write doing a "nice" power off is always recommended to make sure you don't get into situations like you current are with files partially written or worse file systems corrupted. A "nice" power is with a "poweroff" or "reboot" command.</p>
<p>Dan</p> FPGA Development: RE: FPGA programming problemshttp://support.criticallink.com/redmine/boards/47/topics/6004?r=6016#message-60162020-05-27T14:15:04ZDario Russo
<p>Hi Dan,<br />Don't worry, I really appreciate your help. <br />Yes, running “reboot” works and it is the only way to change the FPGA configuration without rebooting the system multiple times. Indeed, even if I change the rbf and then I turn the board off and on, the FPGA configuration doesn’t change. As you said, the problem is that the rbf is not completely written by the file system. Is there any way to fix it?</p>
<p>Best regards,<br />Dario</p> FPGA Development: RE: FPGA programming problemshttp://support.criticallink.com/redmine/boards/47/topics/6004?r=6015#message-60152020-05-27T12:53:11ZDaniel Vincelettedvincelette@criticallink.com
<p>Hi Dario,</p>
<p>My apologizes for the later reply, it was a long holiday weekend in the states.</p>
<p>So by running "reboot" after copying over the RBF fixed your problem?</p>
<p>Dan</p> FPGA Development: RE: FPGA programming problemshttp://support.criticallink.com/redmine/boards/47/topics/6004?r=6011#message-60112020-05-25T08:39:56ZDario Russo
<p>Hi Dan,<br />thank you very much for helping me with this problem.<br />Attacched you can find the boot logs for the three cases required.<br />The checksum verification it is ok by comparing the linux checksum with the PC file. Instead there is no md5sum command in uboot. Can you give me an example for uboot checksum?<br />I think you are right, it seems that rebooting the system with the linux command after changing the rbf file works.</p>
<p>Best regards,<br />Dario</p> FPGA Development: RE: FPGA programming problemshttp://support.criticallink.com/redmine/boards/47/topics/6004?r=6010#message-60102020-05-22T17:08:27ZDaniel Vincelettedvincelette@criticallink.com
<p>Hi Dario,</p>
<p>Thank you for the bootlog and answering my questions.</p>
<p>If you are seeing the yellow led toggle in u-boot then the FPGA is reloaded from what is on the file system. There is a small chance that the file system didn't fully write out the RBF change if you don't cleanly reboot the SOM (using the linux reboot command) and on reboot linux fixes the file system from the journal so that's why it works on next boot.</p>
<p>Have you done a md5sum of the RBF either in linux or uboot (preferably in uboot) after you update it and compare it with the file on your PC? This will help us verify that the file system correctly sees the updated image.</p>
Can you send a continuous bootlog of the following:
<ul>
<li>Boot old RBF</li>
<li>Booting new RBF but still sees old RBF</li>
<li>Booting new RBF and you see it actually load correctly</li>
</ul>
<p>Also can you also post your u-boot environment by breaking into u-boot and running the "print".</p>
<p>With best regards,<br />Dan</p> FPGA Development: RE: FPGA programming problemshttp://support.criticallink.com/redmine/boards/47/topics/6004?r=6009#message-60092020-05-22T07:59:57ZDario Russo
<p>Hi Dan,<br />yes, I still have the multiple boots problem.<br />1) I'm not changing the SDRAM bridge configuration between builds. I'm only changing the vhdl code.<br />2) If I copy a new rbf file and reboot the system, the fpga will be programmed with the old configuration. Sometime it is necessary to reboot the system twice, sometimes more. In some cases, I had to use the linux command and then reboot the system.<br />3) Yes the yellow led toggles, so uboot programs the FPGA.<br />4) Attacched you can find the boot log.<br />5) I simply used a register in the FPGA fixed at a value (that I manually change over compilations). I read this register from HPS and display its value on the terminal.</p>
<p>Thank you Dan.</p>
<p>Dario</p> FPGA Development: RE: FPGA programming problemshttp://support.criticallink.com/redmine/boards/47/topics/6004?r=6008#message-60082020-05-21T13:01:33ZDaniel Vincelettedvincelette@criticallink.com
<p>Hi Dario,</p>
<p>If you are still seeing it take multiple boots to load the "new" rbf from u-boot then it shouldn't be a device-tree issue. Also if you're using u-boot to program it will handle opening the correct bridges, so those warnings can be ignored.</p>
<p>1) Are you changing any of the SDRAM bridge parameters or enabling/disabling any of the bridges between build to build? If so that is handled by u-boot/preloader.</p>
<p>2) Do you only see this "old" version persist with reboots? If you copy over your new rbf and do a full power off do you still see the old rbf being loaded?</p>
<p>3) During reboot do you see the yellow FPGA config light toggle?</p>
<p>4) Could you post a full boot log with you updating the rbf and the multiple boots it takes to load the new "one"?</p>
<p>5) How are you verifying which rbf is loaded? Are you using a qsys sys id core?</p>
<p>Thank you Dario, having to reboot multiple times definitely sounds frustrating and I'd like to help you get this resolved.</p>
<p>Dan</p> FPGA Development: RE: FPGA programming problemshttp://support.criticallink.com/redmine/boards/47/topics/6004?r=6007#message-60072020-05-21T08:18:21ZDario Russo
<p>I checked the preloader and uboot and are updated. I noticed that in the bootlog the bridges are not initialized:</p>
<p>altera_hps2fpga_bridge soc:fpgabridge@0: fpga bridge [hps2fpga] registered as device hps2fpga<br />altera_hps2fpga_bridge soc:fpgabridge@0: init-val not specified<br />altera_hps2fpga_bridge soc:fpgabridge@1: fpga bridge [lwhps2fpga] registered as device lwhps2fpga<br />altera_hps2fpga_bridge soc:fpgabridge@1: init-val not specified<br />altera_hps2fpga_bridge soc:fpgabridge@2: fpga bridge [fpga2hps] registered as device fpga2hps<br />altera_hps2fpga_bridge soc:fpgabridge@2: init-val not specified</p>
<p>Is it possibile that the device tree is missing something?</p> FPGA Development: RE: FPGA programming problemshttp://support.criticallink.com/redmine/boards/47/topics/6004?r=6006#message-60062020-05-17T19:07:34ZDario Russo
<p>Hi Mike,<br />thank you for the detailed answer. I don’t used interruputs and UART or SPI, but I use the sdram bridge. The preloader should be updated (I will check it to be sure). I agree with you, it is better to change the rbf file and reboot the system so that uboot loads the FPGA bitsteam.. However, the problem of updating the rbf file is present even if I don’t use the linux command (but it is necessary to reboot the system at least twice).</p> FPGA Development: RE: FPGA programming problemshttp://support.criticallink.com/redmine/boards/47/topics/6004?r=6005#message-60052020-05-17T11:44:58ZMichael Williamson
<p>Hi Dario,</p>
<p>In your FPGA project, did you modify any of the HPS peripheral settings over your standard load? For example, did you enable or disable a UART or SPI port, or change the SDRAM bridge configurations?</p>
<p>If you did, you will need to rebuild the preloader and reinstall it and reboot. The preloader sets up the IO boundary between the ARM memory subsystem and the FPGA interconnect. If you don't keep that consistent with your FPGA image, you will have problems. There is no way to hot-swap a bitstream that requires the FPGA/ARM/DDR boundaries to be in a different configuration. This is a common problem.</p>
<p>If none of the FPGA <-> ARM or FPGA <-> DDR peripheral interconnect has changed, then here are some other things that I have had trouble with when trying to install / load an FPGA image on the fly:</p>
<p>1) Watch any interrupts that could be generated by the FPGA fabric. If you are generating interrupts from the FPGA and have a linux kernel interrupt handler installed and then reset/reload the bitstream, it is likely that the interrupt connection can activate. I have seen the linux kernel driver try to handle FPGA interrupts during the load and basically not function properly with random behavior.</p>
<p>2) Ensure nothing on the ARM is trying to access any of the FPGA memory bridges (hps2fpga lightweight bus, etc.) during the load. This can also create hangs.</p>
<p>3) You will need to disable the DDR bridges exposed to the FPGA if you reconfigure while linux is running. I believe there are sysfs entries in linux to enable/disable these crossbars. If you reprogram and FPGA image that uses the DDR interface (e.g., fpga2sdram), it is possible that during the bitstream load the bridge interface could be put into an unknown state and lock up the DDR bridge controller (causing trouble for the ARM).</p>
<p>In general, we try to avoid "hot-swapping" FPGA bitstreams and load our target bitstream during uBoot.</p>
<p>-Mike</p> FPGA Development: FPGA programming problemshttp://support.criticallink.com/redmine/boards/47/topics/60042020-05-17T07:17:29ZDario Russo
<p>Hi,<br />I’m working with MitySOM-5CSX-H6-42A development kit and I would like to solve some annoying problems. After generating a new rbf file for programming the FPGA and uploading it to the SD card through sftp, it is necessary to reboot the board at least two times before the new configuration is effectively loaded. Moreover, programming the FPGA through linux command often causes a freeze of the processor and requires a reset. Why is this happening? It seems that it still has the old rbf somewhere and only replaces it after few reboots.</p>
<p>Dario</p> FPGA Development: RE: MitySOM-5CSX-H6-42A files generation issueshttp://support.criticallink.com/redmine/boards/47/topics/5920?r=5922#message-59222020-02-13T13:06:21ZDario Russo
<p>Hi Alex,<br />attached you can find two files with the boot log and the environment variables.</p>
<p>Thanks,<br />Dario</p> FPGA Development: RE: MitySOM-5CSX-H6-42A files generation issueshttp://support.criticallink.com/redmine/boards/47/topics/5920?r=5921#message-59212020-02-12T20:27:06ZAlexander Blockalex.block@criticallink.com
<p>Dario,</p>
<p>It sounds like you may need to modify some of your environment variables to properly boot from the new Kernel/device tree images you have created.</p>
<p>Can you please provide a complete boot log including the output of your environment variables?</p>
<p>We'll review those and provide further followup.</p>
<p>Thanks,</p>
<p>Alex</p> FPGA Development: MitySOM-5CSX-H6-42A files generation issueshttp://support.criticallink.com/redmine/boards/47/topics/59202020-02-07T17:55:19ZDario Russo
<p>Hi,<br />I recently bought a MitySOM-5CSX-H6-42A development kit and I have some problems to generate the files needed. First, I checked the configuration pin, that are set as described in the guide (0x05). I started by simply recompiling the example project and try to re-generate all the files (preloader, uboot, ubootenv, rbf) and write them in the SD card given with the kit (the dtb should be the same of the one stored in the SD card). I carefully followed the instruction in the Wiki links, checking the SDRAM_SCRUBBING and the PRELOADER_TGZ in the bsp-editor, downloading the “uboot-socfpga.tar.gz” for the uboot compilation and updating the single files to the SD card as described in <a class="external" href="https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_SD_Card_Image">https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_SD_Card_Image</a>. Unfortunately, linux doesn’t start and stuck on “starting kernel”. What am I doing wrong?<br />And when I modify the qsys, how can I generate the dtb? I don’t have the board xml file.</p>
<p>Thank you in advance.<br />Dario</p> FPGA Development: RE: Set timing constraintshttp://support.criticallink.com/redmine/boards/47/topics/5837?r=5838#message-58382019-07-03T11:04:42ZMichael Williamson
<p>Hi Davide,</p>
<p>You really need a constraints file for this to constrain the input timing signals properly based on the ADC datasheet specifications.</p>
<p>There are several (free) online courses available from Intel/Altera about writing timing constraints that I would recommend you take if you are not familiar with the techniques of specifying timing for FPGA design. Here is a link to the first of a starter series on basic timing analysis with Quartus.</p>
<p><a class="external" href="https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1115.html">https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1115.html</a></p>
<p>Where is your CLOCK_20 coming from? If it is from an external clock and being fed into the design you absolutely need a constraints file. At a minimum, you would need a clock spec in your SDC file similar to this:</p>
<pre>
create_clock -period "20 MHz" [get_ports CLOCK_20]
</pre>
<p>If you haven't specified the relationship of the input data signals to the clock edge you are using to latch the data, you may not be honoring setup/hold times of the input flip flops. At 20 Mhz, it should be easy to meet the specs. A common error is to sample on the same edge of the clock as the data is output (so you are trying to latch while the data is changing from the source). Often, particularly with slow data rates, simply changing the edge of the clock (inverting it) used to capture the data will resolve capture problems.'</p>
<p>Similarly for the output, if you are clocking the data out on the same clock edge as the DAC is trying to sample, you may cause problems with the DAC.</p>
<p>If you need further assistance, we could support you with a small contract.</p>
<p>-Mike</p> FPGA Development: Set timing constraintshttp://support.criticallink.com/redmine/boards/47/topics/58372019-07-03T09:20:46ZDavide Vaccaro
<p>Dear all,</p>
<p>I have a MitySOM 5CSX-H6-4YA with a Cyclone V SoC installed on a custom board with ADCs and DACs. What I'm trying to do is to digitize an input sinusoid via the ADC and storing it in the internal FPGA RAM via a the RAM 2-PORT Altera IP, so that I can output it back again through a DAC via port A and save the digitized data to a .txt file via port B, using a C program controlled by the embedded processor.<br />The VHDL instantiation of the 2-PORT RAM is the following:</p>
<p>port map(<br />address_a => ADDR_COUNTER, //10-bit counter increasing by 1 each clock cycle<br />clock_a => CLOCK_20, //20 MHz clock signal<br />enable_a => REG_1_HPS(11),<br />data_a => ADC_READ, //16-bit input signal from ADC<br />wren_a => REG_1_HPS(12),<br />q_a => RAM2DAC_OUT, //16-bit output signal to a DAC<br />address_b => REG_1_HPS(9 downto 0),<br />clock_b => REG_1_HPS(10),<br />enable_b => not REG_1_HPS(11),<br />data_b =>REG_1_HPS(31 downto 16),<br />wren_b => REG_1_HPS(13),<br />q_b => REG_0_HPS(15 downto 0),<br />);</p>
<p>The two 32-bit registers REG_1_HPS (output) and REG_0_HPS (input) are connected in Platform Designer as Avalon MM Slaves to the H2F_AXI_MASTER to interface with the processor.<br />The problem is that after each compilation the timings of the I/Os of the program are substantially changed in an apparent random way, and this affects how the input sinusoid is reconstructed (see the attached pictures).</p>
<p>I tried to apply the "Fast Input Register" assignment in Quartus to the registers of each ADC bit signal, but this is not doing the trick. How can I set timing constraints so that the signal is correctly reconstructed? Do I need to write an .sdc file from scratch? If so, how can I do it? Is there a tutorial/example?</p>
<p>Thanks in advance,</p>
<p>Davide</p> FPGA Development: RE: FPGA programminghttp://support.criticallink.com/redmine/boards/47/topics/5809?r=5811#message-58112019-04-30T10:34:39ZDavide Vaccaro
<p>Dear Zachary,</p>
<p>that worked perfectly, thank you so much!</p>
<p>Best,</p>
<p>Davide</p> FPGA Development: RE: FPGA programminghttp://support.criticallink.com/redmine/boards/47/topics/5809?r=5810#message-58102019-04-29T21:48:00ZZachary Millerzmiller@criticallink.com
<p>Hi Davide,</p>
<p>If your FPGA is based on the one from the support site (in particular, if it includes PIO cores), you'll need to rebuild the kernel with the GPIO driver as a module instead of built in.</p>
<p>You can follow the instructions at <a class="wiki-page" href="http://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Linux_Kernel">Linux Kernel</a>, and in menuconfig change <code>Device Drivers -> GPIO Support -> Altera GPIO</code> to <code>M</code> for module. Then copy the <code>uImage</code> and <code>socfpga_mitysom5csx_devkit.dtb</code> to the 5CSx and replace the old ones in <code>/boot</code>, copy the modules into the 5CSx's <code>/lib/modules</code> folder, and reboot.</p>
<p>Unload the gpio driver if it's already loaded (you can check with <code>lsmod</code>):<br /><pre>
rmmod gpio-altera
</pre></p>
<p>Then you should be able to follow the same procedure you tried before to program the FPGA. You can then reload the GPIO driver:<br /><pre>
modprobe gpio-altera
</pre></p> FPGA Development: FPGA programminghttp://support.criticallink.com/redmine/boards/47/topics/58092019-04-29T15:43:18ZDavide Vaccaro
<p>Hi everyone,</p>
<p>I'm having troubles programming the FPGA from HPS in the Linux environment. In particular, after I scp my rbf file to my sd card and disable the bridges, I try to program the FPGA issuing the dd if =file.rbf of=/dev/fpga0 bs=1M command. When I do so, the system freezes and the following screen appears:</p>
<p>INFO: rcu_sched self-detected stall on CPU { 0} (t=2100 jiffies g=193 c=192 q=23)<br />CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.16.0-g2067793 #1<br />[<8001864c>] (unwind_backtrace) from [<800132c0>] (show_stack+0x20/0x24)<br />[<800132c0>] (show_stack) from [<804fd5c8>] (dump_stack+0x8c/0x9c)<br />[<804fd5c8>] (dump_stack) from [<80076664>] (rcu_check_callbacks+0x470/0x908)<br />[<80076664>] (rcu_check_callbacks) from [<80033ab4>] (update_process_times+0x50/0x70)<br />[<80033ab4>] (update_process_times) from [<80082324>] (tick_sched_timer+0x80/0x23c)<br />[<80082324>] (tick_sched_timer) from [<80049970>] (_<em>run_hrtimer+0x90/0x1bc)<br />[<80049970>] (</em>_run_hrtimer) from [<8004a3f8>] (hrtimer_interrupt+0x140/0x310)<br />[<8004a3f8>] (hrtimer_interrupt) from [<80016e3c>] (twd_handler+0x44/0x54)<br />[<80016e3c>] (twd_handler) from [<8006eedc>] (handle_percpu_devid_irq+0x90/0x124)<br />[<8006eedc>] (handle_percpu_devid_irq) from [<8006ac60>] (generic_handle_irq+0x3c/0x4c)<br />[<8006ac60>] (generic_handle_irq) from [<8000fbd8>] (handle_IRQ+0x50/0xa0)<br />[<8000fbd8>] (handle_IRQ) from [<80008644>] (gic_handle_irq+0x3c/0x6c)<br />[<80008644>] (gic_handle_irq) from [<80013ec0>] (_<em>irq_svc+0x40/0x50)<br />Exception stack(0x8075de30 to 0x8075de78)<br />de20: 00000001 ffffab8f 00000000 00000000<br />de40: 8075ab30 0000001d 00000282 fee00100 80504ef4 8079fd70 00000000 8075dedc<br />de60: 807a2d40 8075de78 807a2d40 8002b734 200f0113 ffffffff<br />[<80013ec0>] (</em>_irq_svc) from [<8002b734>] (_<em>do_softirq+0xe0/0x318)<br />[<8002b734>] (</em>_do_softirq) from [<8002bc0c>] (irq_exit+0x88/0xc0)<br />[<8002bc0c>] (irq_exit) from [<8000fbdc>] (handle_IRQ+0x54/0xa0)<br />[<8000fbdc>] (handle_IRQ) from [<80008644>] (gic_handle_irq+0x3c/0x6c)<br />[<80008644>] (gic_handle_irq) from [<80013ec0>] (_<em>irq_svc+0x40/0x50)<br />Exception stack(0x8075df38 to 0x8075df80)<br />df20: bf7d0440 00000000<br />df40: 000285f8 00000000 8075c000 ffffffff 807a0324 8076446c 80504ef4 8079fb7a<br />df60: 00000000 8075df8c 8075df90 8075df80 8000ff50 8000ff54 600f0013 ffffffff<br />[<80013ec0>] (</em>_irq_svc) from [<8000ff54>] (arch_cpu_idle+0x3c/0x40)<br />[<8000ff54>] (arch_cpu_idle) from [<80062308>] (cpu_startup_entry+0x124/0x1ec)<br />[<80062308>] (cpu_startup_entry) from [<804f9420>] (rest_init+0x84/0x88)<br />[<804f9420>] (rest_init) from [<806f9c5c>] (start_kernel+0x394/0x3a0)</p>
<p>Can someone enlighten me about this matter?</p>
<p>Best,<br />Davide</p> FPGA Development: RE: Problem when programming FPGA from HPShttp://support.criticallink.com/redmine/boards/47/topics/5793?r=5799#message-57992019-03-27T09:53:03ZDavide Vaccaro
<p>I attach the simple block diagram-based Quartus project that takes in input a 100 MHz differential clock and outputs a single-ended 25 MHz clock. It makes not use of Qsys and it isn't changing the HPS subsystem, but nonetheless I'm facing the problems aforementioned. I also tried to program the FPGA with the dev_5csx_h6_42a.qpf project (both with the .sof via JTAG or the .rbf from Linux) and the exact same problems manifest.</p>
<p>In the past I used the DE1-SoC from Altera and programming via JTAG worked just fine (the Linux system did not reboot), so I'm quite puzzled about the difficulty of doing the same thing here. Hope you can help.</p>
<p>Best regards,</p>
<p>Davide</p> FPGA Development: RE: Problem when programming FPGA from HPShttp://support.criticallink.com/redmine/boards/47/topics/5793?r=5798#message-57982019-03-26T17:23:49ZMichael Williamson
<p>Can attach a copy of your reference project? Is it based off of the one on our support site?</p>
<p>-Mike</p> FPGA Development: RE: Problem when programming FPGA from HPShttp://support.criticallink.com/redmine/boards/47/topics/5793?r=5797#message-57972019-03-26T16:55:30ZDavide Vaccaro
<p>So, I tried all the methods listed in <a class="external" href="https://rocketboards.org/foswiki/view/Documentation/GSRD131ProgrammingFPGA">https://rocketboards.org/foswiki/view/Documentation/GSRD131ProgrammingFPGA</a>, but none is working. In particular:</p>
<ul>
<li>I'm not successful in configuring the FPGA from the Preloader because I'm not being able to write the preloader, FPGA and U-boot image to the QSPI: when I try to do it using fatload, I get a "U-boot error: <strong>* Unrecognized filesystem type *</strong>" message. Changing the fylesistem type of the partition of the SD card explicitly to ext3 or ext4 did not solve the problem.</li>
<li>I had already tried to configure the FPGA from U-boot or Linux, but (as described in my first post) that does not work.</li>
<li>According to the instructions, stopping the U-boot after warm reset and issuing the <em>run mmcload</em> and <em>run mmcboot</em> commands should make the system boot, without configuring the FPGA, so that the <em>cat /sys/class/fpga/fpga0/status</em> command should result in "configuration phase". However, when I try to do so, the FPGA still gets programmed: the yellow led shuts off and the status of fpga0 is "user mode".</li>
</ul>
<p>Isn't there any way to force the system NOT to reboot when I program the FPGA via JTAG?</p> FPGA Development: RE: Problem when programming FPGA from HPShttp://support.criticallink.com/redmine/boards/47/topics/5793?r=5796#message-57962019-03-25T15:11:36ZDavide Vaccaro
<p>Hi Mike,</p>
<p>in the "final" Quartus program I will indeed need to change the configurations you mentioned, but for a start I decided to use a very simple Quartus project, which does not touch the HPS subsystem (a basic bdf that turns a differential clock into a single ended one and reduces its speed with a PLL). However, also in this case the problems I previously described do manifest.</p>
<p>I generated a new preloader anyway, as you suggested, carefully following the instructions in the link. I verified that I need to check the SDRAM_SCRUBBING box in the bsp-editor: however, after having updated the preloader and the uboot environment, the SD card does not boot at all. I also tried enabling the boot FAT support (assigning the partition #3), but that didn't help.</p>
<p>This behaviour persists regardless of the u-boot being updated or not. The problem thus seems indeed to lie in the preloader, but evidently I'm doing something wrong when rebuilding it. Perhaps there's an option I need to check/uncheck in the bsp-editor that I'm not thinking to?</p>
<p>Regards,</p>
<p>Davide</p> FPGA Development: RE: Problem when programming FPGA from HPShttp://support.criticallink.com/redmine/boards/47/topics/5793?r=5794#message-57942019-03-19T15:40:54ZMichael Williamson
<p>Hi Davide,</p>
<p>Are you enabling or changing the configuration of the FPGA to SDRAM (fpga2sdram) or HPS AXI crossbars in the HPS configuration or enabling additional peripherals in the HPS subsystem?</p>
<p>If you are, then you will need to generate a new preloader image and program it into the micro-SD card. The preloader configures the multiplexed pin interface between the FPGA fabric and the HPS subsystem (including the SDRAM bridges). If the preloader configuration doesn't match what the FPGA (or the kernel) is expecting, the result can be that the bus will hang. I have seen this multiple times. The flow to build the preloader is described <a href="https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_u-Boot_and_Preloader" class="external">here</a> and the instructions for updating the preloader can be found <a href="https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_SD_Card_Image" class="external">here</a>.</p>
<p>The symptoms you are describing sound like that is the problem -- I have had this happen to me more than once!</p>
<p>-Mike</p> FPGA Development: Problem when programming FPGA from HPShttp://support.criticallink.com/redmine/boards/47/topics/57932019-03-19T15:25:02ZDavide Vaccaro
<p>Hi everyone,</p>
<p>I looked at previous posts but the solutions outlined does not seem to work in my case, so I'm writing as well in hope to solve the problem I'm experiencing.</p>
<p>I am using a Critical Link Development Kit with a MitySOM-5CSX-H6-42A module. In broad terms, what I want to do is to configure the FPGA with a configuration file generated in Quartus and then execute a C program, loaded into the SD card with Linux, to interact with the FPGA after it is configured with my file. I generate the .rbf file from the .sof file in Quartus, selecting the Passive Parallel x16 mode. My MSEL, CSEL and BSEL configurations are, respectively 00000, 00 and 101 (0 means ON).</p>
<p>I first tried to program the FPGA via JTAG (using a USB Blaster cable) with the Quartus Programmer tool, but each time I start the process the Linux system reboots, cancelling the programming process.</p>
<p>I then followed the instructions contained in <a class="external" href="https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Programming_the_FPGA">https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Programming_the_FPGA</a>, disabling the bridges before starting to program. However when I issue the "cat myfile.rbf > /dev/fpga0" command, the system freezes and the yellow led does not shut off (indicating that the FPGA is not programmed). The same happens using the "dd if=myfile.rbf of=/dev/fpga0 bs=1M" command.</p>
<p>I also tried to configure the FPGA from U-boot, by stopping the autoboot process and substituting the <em>mmcfpgaloc</em> environment variable (which by default is "/home/root/dev_5csx_h6_42a.rbf") with "/home/root/myfile.rbf", saving and then doing run mmcload and run mmcboot. After doing so, however, the boot process freezes at "Starting kernel ...".</p>
<p>The FPGA appears to be correctly programmed (I can verify that by probing at a pin I assigned in the Quartus project to a 25 MHz clock frequency) if:<br />1) I start the programming process via JTAG with Quartus Programmer, then stop the autoboot;<br />2) I stop the autoboot, modify the <em>mmcfpgaloc</em> environment variable in U-boot with "/home/root/myfile.rbf", then issue the commands "run mmcload" and "run fpgaload".</p>
<p>As far as I understood, the problem seems to lie in the way that the Linux kernel is started, as if it would need the "/home/root/dev_5csx_h6_42a.rbf" file. I am not an expert in FPGA programming and I could not find any solution to this (probably trivial) problem. Can someone suggest me a course of action?</p>
<p>Regards,</p>
<p>Davide</p> FPGA Development: RE: Load FPGA from Linux to MitySOM-5CSX-H6-4YAhttp://support.criticallink.com/redmine/boards/47/topics/5505?r=5507#message-55072017-11-07T10:22:41ZMathew Jones
<p>Thanks Dan,<br />That makes sense - it seems that the kernel does have several Altera drivers built in<br />(cat /lib/modules/$(uname -r)/modules.builtin | grep -i altera).</p>
<p>We do need the Lightweight bus, but instead of rebuilding the kernel without the Altera driver and loading the modules at Linux boot time, we've decided to load the FPGA image via U-Boot (re-loading from Linux was only intended for frequent development FPGA updates).</p> FPGA Development: RE: Load FPGA from Linux to MitySOM-5CSX-H6-4YAhttp://support.criticallink.com/redmine/boards/47/topics/5505?r=5506#message-55062017-11-02T16:40:39ZDaniel Vincelettedvincelette@criticallink.com
<p>Hi Matt,</p>
<p>If you're using the default device-tree and kernel then it would have the Altera GPIO and Altera sysid drivers using the FPGA, which would cause the ARM to hang like you're seeing.</p>
<p>If you aren't using PIO/sysid drivers then you can remove those nodes from hps_lw_bus: bus@0ff200000 in device tree. If you do need those drivers and will be reprogramming the FPGA from linux then you would need to change those drivers to modules and rmmod/insmod them when you reprogram the FPGA.</p>
<p>Dan</p> FPGA Development: Load FPGA from Linux to MitySOM-5CSX-H6-4YAhttp://support.criticallink.com/redmine/boards/47/topics/55052017-11-02T16:12:17ZMathew Jones
<p>Hi<br />Having looked at previous posts I was hoping to be able to program our .rbf firmware rbf from Linux but every time I try Linux just hangs.<br />(previous post was [[<a class="external" href="https://support.criticallink.com/redmine/boards/47/topics/3961]]">https://support.criticallink.com/redmine/boards/47/topics/3961]]</a>)</p>
<p>I boot to Linux from SD card, which also loads the FPGA, but then I cannot re-load either the same FPGA rbf file or another without Linux crashing.<br />My steps are:<br />"cat /sys/class/fpga/fpga0/status" - shows 'user mode'<br />Disable all bridges:<br />"echo 0 > /sys/class/fpga-bridge/fpga2hps/enable" <br />"echo 0 > /sys/class/fpga-bridge/hps2fpga/enable" <br />"echo 0 > /sys/class/fpga-bridge/lwhps2fpga/enable" <br />"cat /sys/class/fpga-bridge/*/enable" - shows 0, 0, 0 indicating that the bridges are disabled.<br />"cat {fpga_rbf_file} > /dev/fpga0" - causes the FPGA status LED to change from green to yellow, but does not change back to green and also Linux hangs, but does output some errors as shown in the attached file.</p>
<p>It doesn't matter whether the {fpga_rbf_file} is the default rbf from the CriticalLink SD card image, or our FPGA rbf.<br />The SD Card image we are using is I believe the latest and has minimal changes:<br />(05-11-2015 [[<a class="external" href="https://support.criticallink.com/redmine/attachments/download/9459/MitySOM_5CSX_H6_4YA_Dev_Kit_Release_1.zip]]">https://support.criticallink.com/redmine/attachments/download/9459/MitySOM_5CSX_H6_4YA_Dev_Kit_Release_1.zip]]</a>)</p>
<p>Is there something else that I'm missing, e.g. another Linux driver also needs disabling before reprogramming the FPGA?<br />Regards<br />Mat</p> FPGA Development: RE: I2C Controllerhttp://support.criticallink.com/redmine/boards/47/topics/5361?r=5365#message-53652017-07-13T15:29:42ZHarrison Barclay
<p>Thank you, this was resolved, turned out to be a problem with our build scripts.</p> FPGA Development: RE: I2C Controllerhttp://support.criticallink.com/redmine/boards/47/topics/5361?r=5362#message-53622017-07-12T12:06:33ZTim Iskanderiskander@criticallink.com
<p>Harrison<br />Whenever you change anything to do with HPS pin assignments, you will need to rebuild the preloader and update it on the boot media (SD card or ROM)</p>
<p><a class="external" href="https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_u-Boot_and_Preloader">https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_u-Boot_and_Preloader</a></p>
<p>cheers<br />/Tim</p> FPGA Development: I2C Controllerhttp://support.criticallink.com/redmine/boards/47/topics/53612017-07-11T17:51:22ZHarrison Barclay
<p>Hello,</p>
<p>Unsure whether to post this under the software or FPGA topic.</p>
<p>We are transitioning from a mostly working system developed on the Mitysom5CSX Devkit to a custom carrier board design (Cyclone V, 5CSX-H6-4YA-RC). In the previous system, we had used the I2C3 controller (at 0xffc07000, passed through the FPGA by selecting the FPGA option in Qsys) to communicate with a particular peripheral.</p>
<p>In the new design, we decided to use I2C1 (0xffc05000) on HPS pins (I/O set 0) to communicate with the same peripheral. The pin mux table seems correct and the pin assignments seem to agree with our schematic, at this point checked many times. However, when attempting to write data to the bus, there is absolutely no activity on those pins, and the I2C designware driver gives a "controller timed out". I2C0, which does not leave the SOM, seems to be working fine, even though the I2C1 configuration seems to be almost exactly analogous.</p>
<p>Other I2C controllers on the system passed through the FPGA fabric function as expected. We have checked for possible hardware-level problems such as pull-up value, layout, etc. The SCL and SDA lines sit at 3.3V and never move.</p>
<p>Please assist in choosing next steps for debugging. I would be glad to provide additional information if requested.</p>
<p>Thank you</p>
<p>Harrison Barclay</p> FPGA Development: RE: Power fail interruphttp://support.criticallink.com/redmine/boards/47/topics/5343?r=5346#message-53462017-06-20T17:59:19ZAlexander Blockalex.block@criticallink.com
<p>Clyde,</p>
<p>Offhand our recommendation would be to utilize an HPS GPIO and have it configured in the GPIO controller as an interrupt.</p>
<p>Additionally it would be pertinent to know how long you expect power to persist after this interrupt is triggered. A lot of our specific software recommendations depend on the time the module remains powered.</p>
<p>Can you please describe what you are trying to protect with these "necessary precautions". Are you trying to prevent data loss, allow your application to complete its current process, shut-down the OS completely or something else? With this information we can provide a more detailed response and recommendation.</p>
<p>Thank you,</p>
<p>Alex</p> FPGA Development: RE: Power fail interrupthttp://support.criticallink.com/redmine/boards/47/topics/5343?r=5345#message-53452017-06-20T17:14:45ZClyde Shappee
<p>What more is there to say, really? We have a low voltage supervisor in our design and when the power is going to fail, we would like to take the necessary precautions before power is completely gone.</p> FPGA Development: RE: Power fail interruphttp://support.criticallink.com/redmine/boards/47/topics/5343?r=5344#message-53442017-06-20T16:45:11ZDaniel Vincelettedvincelette@criticallink.com
<p>Hello Clyde,</p>
<p>Could you describe the situation a bit more?</p>
<p>Thanks!</p>
<p>Dan</p> FPGA Development: Power fail interruphttp://support.criticallink.com/redmine/boards/47/topics/53432017-06-20T14:05:09ZClyde Shappee
<p>What is the recommended input to the SOM for a power fail interrupt?</p>
<p>clyde</p> FPGA Development: RE: CLK2DDR signal on development boardhttp://support.criticallink.com/redmine/boards/47/topics/5154?r=5155#message-51552017-02-02T12:57:07ZAdam Dziedzicadam.dziedzic@criticallink.com
<p>Hello Franco,</p>
<p>Thanks for checking before committing to the board... The I/O standard does indeed sound like a mismatch!</p>
<p>The likely difference between the 2.5V I/O design building and a failing 3.3V I/O design is due to the (VPD) PreDriver voltage. This is handled internal to the MitySOM for each flexible Bank where an I/O voltage is supplied from the baseboard. With 2.5V I/O rails and lower, the PreDriver voltage fed to that bank is at 2.5V. When running a bank voltage higher than 2.5V, the predriver voltage matches the VIO voltage. The FPGA supports multiple voltage standards on inputs and the list of supported standards depends on a number of factors including the VPD. Note that Banks 3B and 4A share the same VPD and therefore, must both run the same VIO voltage when using 3.3V VIO for either bank.</p>
<p>1) To drive an output, yes - multiple input standards can be supported together, but there are very specific rules.</p>
<p>2) Possibly the LVDS thresholds are sufficient in this case to meet the SSTL135 input levels. There is likely a better approach.</p>
<p>3) For clarity, this clock input is only used to meet the timing requirements on the FPGA-DDR, not the HPS-DDR. The Quartus tools have advanced since the initial MitySOM design, so it is not completely ruled out. When defining the module, the task was monumental to meet the timing requirements for the FPGA DDR, without consuming the Bank4A/3B I/O pins (where most of the IOs are located). The one clock input that would meet the requirement was the Bank4A clock input, specifically the _P side that has a direct connection to the corner PLL.</p>
<p>4) You can change the clock input to a 3.3V source - this should be OK, but make sure the single-ended input is on the _P side of the clock input.</p>
<p>Please let us know if you would like a schematic review before finalizing your design. It benefits us both to have successful designs.</p>
<p>Thanks,<br />Adam</p> FPGA Development: CLK2DDR signal on development boardhttp://support.criticallink.com/redmine/boards/47/topics/51542017-02-02T11:47:48Zfranco spinellafranco.spinella@pi.infn.it
<p>Hi, I'm designing my own carrier card, but I've some doubts about the use of the bank 4A.<br />I need to connect the the mitysom module some parallel DACs with 3.3 volts single ended levels as outputs.<br />I need about 34 pins so I was planning to use the bank 4A, but:<br />- In the demo board the VCCIO-4A is connected to 2.5 volts. <br />- In the demo board design the CLK2DDR_P and CLK2DDR_N signals are connected to the bank 4A and comes from a SiT9120-2C3 100 MHz differential oscillator with LVDS levels, in the demo firmware design <br />it is defined only the pin Y13, connected to CLK2DDR_P and is defined as SSTL-135. <br />If I try to define all the 4A pins eccept Y13 as LVTTL3.3 the demo design does not compile, because of the presence of the SSTL-135 clk signal. <br />Here are my doubts:<br />1) I could be wrong but from the datasheet it seems that the STTL-135 signals needs a 1.35 v VCCIO, so I can't understand why it is compiling with all the other pins defined with a 2.5 v level ...<br />2) The SiT9120 has a lvds differential output, while in the demo firmware the Y13 pin is defined as single ended SSTL-135. How can it work ?<br />3) In my custom carrier card can I connect the clock for the DDR to another bank and leave the 4A empty so that I could connect the VCCIO4A to 3.3 volts and define all the bank pins as 3.3v lvttl ?<br />4) Does this clock has to come from a diffrential oscillator to garantee a correct operation for the DDR3 ?<br />Sorry if I was too long but I'm finalizing my card design and I would like to be sure that I don't do mistakes with the DDR ...<br />Thanks<br />Franco</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=5016#message-50162016-09-08T08:06:42ZStephen Snyderssnyder@continuuminnovation.com
<p>Hi Dan,</p>
<p>Thanks for posting the instructions and looking at the higher resolution operation. This is very useful as it's possible we'll want to support a resolution that needs greater than 4MB for a framebuffer. We'll be using these modifications as the base of starting our development.</p>
<p>Best,</p>
<p>Steve</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=5015#message-50152016-09-07T18:21:12ZDaniel Vincelettedvincelette@criticallink.com
<p>Alright, so I was able to get 1080p working. I had to make some changes to the defconfig for the hdmi example. I had to add support for CONFIG_CMA and CONFIG_DMA_CMA, which allowed the altera vip frame buffer driver to allocate enough contiguous memory to make the 1920x1080 framebuffer in ram.</p>
<p>I've updated my previous post about what to change in the example for different resolutions to include setting the max height/width in the hdmi_framereader qsys block as well.</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=5014#message-50142016-09-07T10:58:55ZDaniel Vincelettedvincelette@criticallink.com
<p>That's a good idea Mike, it looks like the kernel defaults vram to 4MB but for this framebuffer 8MB+ is required. I'll try setting it higher and see if I can get 1080p working today.</p>
<p>Thanks,</p>
<p>Dan</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=5013#message-50132016-09-06T20:21:32ZMichael Williamson
<p>Can you up the video ram buffer available for allocation using the kernel parameter of the format below?</p>
<pre>
vram=16M
</pre> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=5012#message-50122016-09-06T18:29:40ZDaniel Vincelettedvincelette@criticallink.com
<p>Alright my testing today wasn't as successful as I'd liked. I tried both 1920x1080 and 720x576. Doing 1920x1080 caused the kernel to crash when it tried to allocate the RAM for the frame buffer to use. 720x576 appeared to boot fine but my monitor said it couldn't support the output. I was using those resolutions because the hsync and vsync settings were documented by analog devices. Here is what I changed for the resolutions:</p>
Device tree: <strong>linux-socfpga/arch/arm/boot/dts/socfpga_mitysom5csx_devkit_hdmi.dts</strong><br /><pre>
hdmi_0: hdmi0x0100 {
compatible = "altr,vip-frame-reader-1.0";
reg = <0x0100 0x80>;
max-width = <0x500>;
max-height = <0x2d0>;
bits-per-color = <0x8>;
mem-word-width = <0x80>;
};
</pre><br />You would change max-width and max-height to the different resolution.<br />hdmi_out: <strong>qys Clocked Video Output</strong>
<ul>
<li>Update Image width/Image height</li>
<li>Separate Sync Only - Frame/Field 1 HSync/VSync settings</li>
<li>Pixel Fifo Size set to the width</li>
<li>Fifo level at which to start output set to the width - 1</li>
</ul>
hdmi_framereader: <strong>qsys Frame Reader</strong>
<ul>
<li>Update Maximum image width/height</li>
</ul> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=5011#message-50112016-09-06T09:38:12ZDaniel Vincelettedvincelette@criticallink.com
<p>Hi Steve,</p>
<p>I'm testing this now. Hopefully it's just the mods to the device tree/qsys project. I'll update once my build is finished and (fingers crossed) I'm able to get video.</p>
<p>Dan</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=5010#message-50102016-09-02T08:10:20ZStephen Snyderssnyder@continuuminnovation.com
<p>Hi Daniel,</p>
<p>I saw the project got pushed, thanks.</p>
<p>When do you think you can put together those instructions for updating the resolution?</p>
<p>Thanks a lot,</p>
<p>Steve</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=5006#message-50062016-08-24T09:59:22ZDaniel Vincelettedvincelette@criticallink.com
<p>Hi Steve,</p>
<p>I'll cleanup and push the project today. I'll also go through and write down what needs to be updated in order to change resolution, I think it will be qsys, device tree, and maybe the initialization code for the HDMI chip but I'll double check.</p>
<p>Dan</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=5005#message-50052016-08-23T15:52:29ZStephen Snyderssnyder@continuuminnovation.com
<p>Hi Dan,</p>
<p>So I'm still not getting any output on my monitors. However, I tried adjusting the monitor settings and I get a message saying out of range signal. I don't understand how I saw the yocto splash screen on this monitor at some point. I also don't fully understand why Windows can drive this display at 720p. Perhaps it's doing something "smart".</p>
<p>I think what would be most beneficial at this point would be if you could post an updated Quartus project, source files, etc that I can modify for different resolutions. I'll want to pickup the I2C stability changes that you solved. We'll eventually define a fixed resolution for our product and will expect a compatible display to be provided. Along with the updated sources, if you could point out where changes need to be made to change the resolution, that would be helpful. My understanding is it's in the Qsys project clocked video output peripheral and device tree. Anywhere else?</p>
<p>Thanks,</p>
<p>Steve</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=5004#message-50042016-08-23T14:18:10ZDaniel Vincelettedvincelette@criticallink.com
<p>Sorry about that, it's attached now</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=5003#message-50032016-08-23T13:41:14ZStephen Snyderssnyder@continuuminnovation.com
<p>Can you post that image for me to try?</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=5002#message-50022016-08-23T13:34:37ZDaniel Vincelettedvincelette@criticallink.com
<p>Awesome, I'll glad it did work on the TV!</p>
<p>I was able to recreate what I think you're seeing on your monitor. If I set my monitor's image size to auto instead of wide then it only showed up as a black screen. When I set it to wide I was able to get an image, though the resolution didn't look right. I was using the updated FPGA image with the correct porching timing.</p>
<p>Dan</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=5001#message-50012016-08-23T12:32:05ZStephen Snyderssnyder@continuuminnovation.com
<p>Awesome, thanks.</p>
<p>I tried a large screen Samsung HDTV and your latest build works.</p>
<p>I'm hoping that the HDTV's are a bit more forgiving with the back porch value than the monitors, and this latest build works on both.</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=5000#message-50002016-08-23T12:10:04ZDaniel Vincelettedvincelette@criticallink.com
<p>Good catch, I'm doing a build now with the those back porch values. I'll let you know when it's finished.</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=4999#message-49992016-08-23T12:00:55ZStephen Snyderssnyder@continuuminnovation.com
<p>One thing of note, based on the original qsys file from the wiki page, it seems the back porch values are not the same as those used in the AD9889B programming guide for 720p-60. See attached screenshots. It may be that the display's I'm using are more sensitive to the shorter back porch than yours. I will also try with a few more display's, specifically an HDTV.</p>
<p>Best,</p>
<p>Steve</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=4998#message-49982016-08-23T11:51:52ZStephen Snyderssnyder@continuuminnovation.com
<p>No luck, same result, just a black screen.</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=4997#message-49972016-08-23T11:14:48ZDaniel Vincelettedvincelette@criticallink.com
<p>Hi Steve,</p>
<p>Attached is a new image. The only thing I changed was that I updated the output delays for the data/control lines to match what the microtronix's example project used. It did work in my dev kit.</p>
<p>Let me know how it goes</p>
<p>Dan</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=4996#message-49962016-08-22T14:10:00ZStephen Snyderssnyder@continuuminnovation.com
<p>That's ok, thanks for the update Dan. Feel free to post an updated image anytime, even if you don't have a ton of testing. I don't mind being a guinea pig if it gets us to a working example a little bit sooner.</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=4995#message-49952016-08-22T14:07:18ZDaniel Vincelettedvincelette@criticallink.com
<p>Steve,</p>
<p>I'm terribly sorry for the radio silence. Unfortunately I've been travelling for the past week so I haven't been able put as much time towards this as I'd like. Thank you for providing the scope captures, the data looks to be pretty delayed from the clock edge. I took your suggestion and have merged in the hdmi cards example project's timing constraints into the project. I'll be back in the office tomorrow and will be able to make sure it still works on my dev kit and will try a few more monitors.</p>
<p>Sorry again for the delay</p>
<p>Dan</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=4994#message-49942016-08-22T07:43:00ZStephen Snyderssnyder@continuuminnovation.com
<p>Hi Dan,</p>
<p>Any update on this? Have you been able to review the scope shots?</p>
<p>Best,</p>
<p>Steve</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=4993#message-49932016-08-17T10:35:47ZStephen Snyderssnyder@continuuminnovation.com
<p>Hi Dan,</p>
<p>See attached. The index.txt file in the zip package describes each scope shot. Let me know what other measurements I can take.</p>
<p>I've read there is a Quartus reference design for the Microtronix card. Have you compared your own timing constraints with those from that design? I can't seem to find my CD that came with the card to look it over myself.</p>
<p>Thanks and Best,</p>
<p>Steve</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=4992#message-49922016-08-16T15:35:10ZStephen Snyderssnyder@continuuminnovation.com
<p>Hi Dan,</p>
<p>Sure thing, I can take these shots first thing in the morning and get them back to you.</p>
<p>Steve</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=4990#message-49902016-08-16T13:12:07ZDaniel Vincelettedvincelette@criticallink.com
<p>Hi Steve,</p>
<p>Hmm good point that it you've already vetted the monitor you're using. Seeing as you're getting the display to come out of standby and you're boot log didn't have any I2C errors, I'm going to assume the configuration of the transmitter is working as expected. Which makes me think this is more of a timing issue between the clock and data pins, we must be close to margin seeing is it works on my board but not yours.</p>
<p>Would you mind scoping the clock and data or hsync/vsync line on the AD9889B? They should be edge aligned and the clock should be 74.25Mhz. The data sheet is here: <a class="external" href="http://www.analog.com/media/en/technical-documentation/data-sheets/AD9889B.pdf">http://www.analog.com/media/en/technical-documentation/data-sheets/AD9889B.pdf</a></p>
<p>I could also just invert the output clock, which should increase the margin.</p>
<p>Dan</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=4989#message-49892016-08-16T07:39:59ZStephen Snyderssnyder@continuuminnovation.com
<p>Hi Dan,</p>
<p>Thanks for the detail on the I2C fix.</p>
<p>I've tested on two monitors. On one of them, I am certain it supports 1280x720 because I can set it to that resolution when driving it with my PC. Additionally, this monitor is the one that did display the splash screen <strong>sometimes</strong> with the previous HDMI SD image. I will try and scrounge up a HDTV just as another data point, but I suspect something else is causing the issue.</p>
<p>Let me know if there's any log files that may help or if you want me to scope some lines.</p>
<p>Best,</p>
<p>Steve</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=4986#message-49862016-08-15T15:11:51ZDaniel Vincelettedvincelette@criticallink.com
<p>Hi Steve,</p>
<p>Sorry for the delay, I was travelling Friday afternoon.</p>
<p>To fix for the I2C issue was that I resampled and debounced the I2C signals coming into the FPGA before feeding them to the HPS I2C master. I expected the HPS to take care of the debouncing but that feature might only be enabled if I'm not routing the signals through the fabric. I also cleaned up the timing constraints to make sure all the paths were constrained.</p>
<p>I've tested this on both a high res monitor and 720p TV. The HDMI transmitter is current hard set to output 1280x720, so when I used the 720p TV the output looked perfect. But when I tried using my normal high res monitor at my desk, I did see X and XFCE but the monitor didn't scale the image as I expected. This most likely is due to me forcing the HDMI transmitter into 720p resolution with the hdmi program. If you have a TV you can easily try, I would recommend giving that a try. I'll look into the HDMI transmitter setup to see if there is something off there.</p>
<p>Dan</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=4984#message-49842016-08-15T10:45:50ZStephen Snyderssnyder@continuuminnovation.com
<p>Hi Dan,</p>
<p>This image doesn't show anything on my monitor. Upon first booting it, right after the console printed "Setting Up HDMI Transmitter", the monitor came out of standby but the screen stayed black. After powering the system off, the monitor never went to standby. I then booted again and still saw a black screen.</p>
<p>Attached are the two logs of the console for each boot. Also some other log files that I thought could help. Let me know if there are others that would be useful.</p>
<p>Thanks,</p>
<p>Steve</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=4980#message-49802016-08-12T12:15:18ZStephen Snyderssnyder@continuuminnovation.com
<p>Hi Dan</p>
<p>Thanks for this. I can try the image on Monday and report back results.</p>
<p>Can you provide a little detail on the fix? Alternately if it is in Git (or will be there shortly), I can just look at the commit.</p>
<p>Best,</p>
<p>Steve</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=4979#message-49792016-08-12T11:56:33ZDaniel Vincelettedvincelette@criticallink.com
<p>Hello Steve,</p>
<p>I've created an alpha SD card image that from my testing has fixed the i2c failures. The filesystem also now has X11 and launches XFCE on boot (if you have a USB OTG cable a mouse/keyboard can be used)</p>
<p>The image should be attached to this post and should just need to be written to an SD card.</p>
<p>I'm hoping to get the project updated on the wiki in the beginning of next week.</p>
<p>If you wouldn't mind, can you let me know if you tried the new image and if it worked better for you?</p>
<p>Thanks!</p>
<p>Dan</p> FPGA Development: RE: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/4973?r=4975#message-49752016-08-09T10:30:01ZDaniel Vincelettedvincelette@criticallink.com
<p>Hello Steve,</p>
<p>There was a bit of stability issue with the I2C interface to the HDMI transmitter IC. I thought my newest build of the demo had the stability issue ironed out though, let me take try it here again and I'll post back with my findings.</p>
<p>Dan</p> FPGA Development: HDMI Output splash screen is intermittently displayed on boothttp://support.criticallink.com/redmine/boards/47/topics/49732016-08-09T09:43:03ZStephen Snyderssnyder@continuuminnovation.com
<p>Hello,</p>
<p>I'm trying to run the HDMI output image provided on the wiki. I haven't modified anything just written the image to an SD card.</p>
<p>When booting, the splash screen sometimes shows up, but usually doesn't. I'm also intermittently seeing the message "i2c_designware ffc06000.i2c: controller timed out" several times during boot and halt. This is preceeded by "i2c_designware ffc06000.i2c: i2c_dw_handle_tx_abort: lost arbitration". It looks like this is coming from the executable /home/root/hdmi that is used to configure the transmitter. I can't see a correlation between when I see the time out messages and when the splash screen works. Also, during halt, I always see the time out message.</p>
<p>I'd like to see this working consistently before beginning to develop off of this base. Some console log files are attached.</p>
<p>Thanks a lot,</p>
<p>Steve</p> FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)http://support.criticallink.com/redmine/boards/47/topics/4938?r=4942#message-49422016-07-11T09:41:53ZAdam Dziedzicadam.dziedzic@criticallink.com
<p>Hi Tom,</p>
<p>As the Root Port, the HPS will control the reset to the PCIe. This can be an HPS GPIO, loaned pin, or FPGA I/O. A bank 8A pin is acceptable.</p>
<p>- Adam</p> FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)http://support.criticallink.com/redmine/boards/47/topics/4938?r=4941#message-49412016-07-11T09:02:01ZThomas Carpenterthomas.carpenter@me.gatech.edu
<p>After a bit of rearranging, I've gained the use 179 (B8A_RX_T1_N/CLK7n) for the PERSTn. I believe that should work fine.</p>
<p>Thanks,<br />Tom.</p> FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)http://support.criticallink.com/redmine/boards/47/topics/4938?r=4940#message-49402016-07-11T08:37:42ZThomas Carpenterthomas.carpenter@me.gatech.edu
<p>Hi Adam,</p>
<p>Thanks, I hadn't realised that restriction was just on CvP. As we don't need that, you say that any IO can be used.</p>
<p>Would HPS_GPIO44 (pin244 on the MitySOM) be usable if I set up HPS loaning for that pin so that the FPGA can control it. We are basically using all of the I/O pin in the design bar 4 HPS pins (GPIO 44, 41, 40, and 37), so if the PERSTN pin can't be on pin 21, it would have to be one of those four. I suppose given that it is a very slow signal, it shouldn't be an issue.</p>
<p>Thanks,<br />Tom</p> FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)http://support.criticallink.com/redmine/boards/47/topics/4938?r=4939#message-49392016-07-11T08:11:56ZAdam Dziedzicadam.dziedzic@criticallink.com
<p>Hi Thomas,</p>
<p>The Cyclone V has a mode where it can be configured using CvP (Config via Protocol) - this configures the FPGA over the PCI Express bus interface. To use this mode, the PERSTN has only one option for the pin location. For the other use cases, the PERSTN pin can be assigned to other pin locations.</p>
<p>It sounds like you are planning to use the PCIe Root Port mode on the MitySOM. Please assign an available pin location in your design - I do not expect any issues.</p>
<p>Thanks,<br />Adam</p> FPGA Development: 5CSX-H6-53B-RC with PCIe Hard IP (Root)http://support.criticallink.com/redmine/boards/47/topics/49382016-07-09T22:22:22ZThomas Carpenterthomas.carpenter@me.gatech.edu
<p>Hi,</p>
<p>We are considering one of the MitySOM boards for use in one of the projects we are working on. I'm currently going over the pin mappings to make sure that we have enough pins.</p>
<p>I was reading through the design guide for the board but noticed something concerning about the PCIe connections. It states in that document that the PCIe reset (PERSTN) pin is on pin 21 (B5A_RX_B6_N), but says that this pin is not available for boards with 512MB or more of FPGA RAM.</p>
<p>Does this mean that it is not possible to use the PCIe root port on the 5CSX-H6-53B-RC board because it has 512MB of FPGA RAM?</p>
<p>We will require the 2GB of HPS RAM which only that version has, and we also need some FPGA RAM, but 64MB would be enough (I see there are some with 256MB which would also be fine). If it is not possible to use the PCIe port due to the conflicting pin requirements, is it possible to modify the MitySOM which has 512MB of FPGA RAM to only use 256MB of it (say remove the connection to the extra address bit) in order to allow the use of the PERSTN pin? Alternatively, is there a possibility to get a version of the MitySOM with 256MB of FPGA RAM, but 2GB of HPS RAM?</p>
<p>Thanks,<br />Tom.</p> FPGA Development: RE: HDMI Output and Quartus Versionshttp://support.criticallink.com/redmine/boards/47/topics/4904?r=4906#message-49062016-06-20T13:15:33ZAlexander Blockalex.block@criticallink.com
<p>Steve,</p>
<p>We have successfully rebuilt the <a href="https://support.criticallink.com/redmine/projects/5csxbase/wiki/HDMI_Output" class="external">HDMI example</a> using Quartus 14.1 however you will require a license to support the VIP Suite (Video and Image Processing Suite MegaCore Functions).</p>
<p>You can find out information about licensing from this page: <a class="external" href="https://www.altera.com/products/intellectual-property/ip/dsp/m-alt-vipsuite.html">https://www.altera.com/products/intellectual-property/ip/dsp/m-alt-vipsuite.html</a></p>
<p>Thank you,</p>
<p>Alex</p> FPGA Development: HDMI Output and Quartus Versionshttp://support.criticallink.com/redmine/boards/47/topics/49042016-06-20T11:07:55ZStephen Snyderssnyder@continuuminnovation.com
<p>Hi,</p>
<p>I noticed that the HDMI Output example you've posted was done in Quartus 15.1 but the VM with the toolchain installed is still on Quartus 14.x. What would you recommend for someone deriving a project from the HDMI example? Should we upgrade the Quartus version on the VM, install Quartus 15.1 on a separate machine and use the VM for software development, or build the project in 14.x?</p>
<p>Thanks,</p>
<p>Steve</p> FPGA Development: RE: LVDS transceiver for 1000Mb Ethernet MAC & 1000Base-X problemhttp://support.criticallink.com/redmine/boards/47/topics/4591?r=4597#message-45972016-01-15T14:57:34ZAdam Dziedzicadam.dziedzic@criticallink.com
<p>Hi Charles,</p>
<p>The GXB TX details can be found in Altera's documentation:<br /><a class="external" href="https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cyclone-v/cv_5v3.pdf">https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cyclone-v/cv_5v3.pdf</a></p>
<p>Are you using the on-chip biasing network and termination, or external termination?</p>
<p>Because the transmitter is a current mode output, it needs to have either the internal or external termination to create the differential voltage. As long as there is a reasonable termination network, the VCM should be 0.65V. It sounds like you are using the PCI Express connector for the GXB interface. These TX pairs are AC coupled on the Dev Board, so I assume you are using the on-chip biasing circuitry. Does the VCM and VOD look any better at the MitySOM side of the AC coupling caps on the bottom of the Dev Board (C208/C209)?</p>
<p>With the AC coupled link, the receiving end of the TX pair can run a different VCM than the Cyclone V GXB generates through the internal biasing network. That VCM depends on another set of termination resistors.</p>
<pre>
Programmable Transmitter VCM
The transmitter buffers have on-chip biasing circuitry to establish the required VCM at the transmitter
output. The circuitry supports a VCM setting of 0.65 V.
Note: On-chip biasing circuitry is available only if you select one of the Termination logic options in
order to configure OCT. If you select external termination, you must implement off-chip biasing
circuitry to establish the VCM at the transmitter output buffer.
Programmable Transmitter Differential OCT
The transmitter buffers support optional differential OCT resistances of 85, 100, 120, and 150 Ω . The
resistance is adjusted by the on-chip calibration circuit during calibration, which compensates for PVT
changes. The transmitter buffers are current mode drivers. Therefore, the resultant VOD is a function of
the transmitter termination value.
</pre>
<p>The waveform you posted does not look distorted, so the GXB outputs appear to be functioning fine. And I don't see any reason you would need dynamic transceiver configuration.</p>
<p>Hope this helps,<br />- Adam</p> FPGA Development: LVDS transceiver for 1000Mb Ethernet MAC & 1000Base-X problemhttp://support.criticallink.com/redmine/boards/47/topics/45912016-01-12T11:08:36ZCharles Garcia charles.garcia@vialight.de
<p>Hi,<br />I have been attempting to use the development kit to setup and implement a system which interfaces to an externally connected SFP module which I have connected via the SPIe connection to the dev board. I instantiated the TSE Ethernet core from Altera together with the pcs phy 1000Base x transceiver interface. All built well, however when I inspected the differential signals from the GXB io, the signal voltage levels look wrong. I can see my Ethernet packets being generated on the GXB Tx lines, however the common mode voltage is only 300mv and the differential voltage is only 270mv (signals measured using scope with a differential interface). I tried to vary the VoD setting to 1 or 2 in the qsf file however the fitter through a fit..<br />- is there a setting that I am missing?<br />- could I have somehow damaged the I0BANK_B0L or I0BANK_B1L banks (I have tried both)<br />- do I need to implement the dynamic transceiver configuration (yuck!!)</p>
<p>Thanks guys…</p> FPGA Development: RE: JTAG: No JTAG hardware availablehttp://support.criticallink.com/redmine/boards/47/topics/4555?r=4561#message-45612015-11-18T12:54:52ZAdam Dziedzicadam.dziedzic@criticallink.com
<p>Hi Darius,</p>
<p>To start, I'm not sure what your hardware setup is, so I will assume you are working with a Dev Board or a board that can boot from an SD Card. When that boots, there is a very brief preloader configuration, then uBoot starts and counts down from 5 seconds. Within that time, you can send a character through the console interface (connect serial terminal app with settings of 115200,8,N,1) to halt the boot process and wait at the uBoot command prompt. Assuming you are able to get to this point, you can follow the info on the Wiki to program the QSPI NOR Flash. Note that different BSEL (Boot Select) values are required to boot from SD v.s. QSPI NOR. On the Dev Board, simply adjust the DIP Switch settings in switch positions 10,9,8. For SD Card, use "101" by setting them Off,On,Off. For QSPI NOR, use "110" by setting them Off,Off,On respectively for positions 10,9,8.</p>
<p><a class="external" href="https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/U-Boot_on_the_MitySOM-5CSX#Booting-from-Quad-SPI-NOR-flash">https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/U-Boot_on_the_MitySOM-5CSX#Booting-from-Quad-SPI-NOR-flash</a></p>
<p>Please let us know if you run into more hurtles.</p>
<p>Thanks,<br />Adam</p>
<p>Other relevant Wiki pages:<br /><a class="external" href="https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Utilizing_QSPI_NOR_Memory">https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Utilizing_QSPI_NOR_Memory</a><br /><a class="external" href="https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Configuration">https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Configuration</a></p> FPGA Development: RE: JTAG: No JTAG hardware availablehttp://support.criticallink.com/redmine/boards/47/topics/4555?r=4560#message-45602015-11-18T11:19:24ZDarius Betheldjbethel12@gmail.com
<p>Adam,</p>
<p>Thank you for your reply. How would I need to go about configuring the flash via the console USB connector?</p>
<p>Darius</p> FPGA Development: RE: JTAG: No JTAG hardware availablehttp://support.criticallink.com/redmine/boards/47/topics/4555?r=4556#message-45562015-11-10T13:24:32ZAdam Dziedzicadam.dziedzic@criticallink.com
<p>Hi Darius,</p>
<p>The console USB connector is simply a UART interface. You can use this to talk to uBoot and the Linux console to configure the flash. If you want to go through JTAG, the white connector on the top of the MitySOM will accept the JTAG adapter card.</p>
<p>Thanks,<br />Adam</p> FPGA Development: JTAG: No JTAG hardware availablehttp://support.criticallink.com/redmine/boards/47/topics/45552015-11-10T11:42:16ZDarius Betheldjbethel12@gmail.com
<p>Hello all,</p>
<p>I am trying to to program QSPI using the hps programmer tool , via the j400 console usb, within the virtual box environment. Using jtagconfig in the Altera Embedded Command Shell, I receive a message that says, No JTAG hardware available. Am I using the wrong jtag for this operation? I have tried changing the 51-usbblaster.rules file to 92-usbblaster.rules, but to no avail. Any help would be appreciated. Thank you.</p> FPGA Development: HSMC1 in MityARM-5CSX Baseboardhttp://support.criticallink.com/redmine/boards/47/topics/45412015-09-30T05:56:56ZAlejandro Concepcióna.concepcion.rodriguez@gmail.com
<p>Hi,</p>
<p>I'm trying to use a HSMC-card (to be precise, the THDB-ADA A/D and D/A kit from TerasIC) with a MityARM-5CSX Baseboard. I made a design in order to test that the D/A pinout is correct, but the output it is not what I expect. The design is so simple (just a NCO generating a sine) that I suppose the mistake must be in the pinout. Could anyone verify if the pinout for the HSMC1 in the .xlsx is correct?</p>
<p>Thanks,</p>
<p>Alejandro</p> FPGA Development: RE: HSMC1 pinouthttp://support.criticallink.com/redmine/boards/47/topics/4434?r=4446#message-44462015-05-29T03:31:18ZFlorian Riegerflorian.rieger@ruag.com
<p>Alex,</p>
<p>thank you for clearing that up!</p>
<p>B) Just for the record, SMC1_SMSDA should be SoM pin 54 and HSMC1_SMSCL should be SoM pin 52.</p>
<p>C) Yes, the usage of those pins is quasi-static, they form part of a 9 bit configuration interface. Since you have offered your feedback/recommendations, I attached the pinout of the HSMC1 interface as I intend to use it. I'd be glad to hear your opinion on that.</p>
<p>Thanks,<br />Florian</p> FPGA Development: RE: HSMC1 pinouthttp://support.criticallink.com/redmine/boards/47/topics/4434?r=4444#message-44442015-05-28T11:08:44ZAlexander Blockalex.block@criticallink.com
<p>Floria,</p>
<p>A) We confirmed that the .tcl script is in fact incorrect for that pin-assignment.</p>
<p>Correct pin assignment (as you noted):</p>
<pre>
set_location_assignment PIN_AF27 -to HSMC1_SMSCL
set_location_assignment PIN_AF28 -to HSMC1_SMSDA
</pre>
<p>Note that we have more up to date examples and .tcl scripts in our example project GIT repos however the SCL/SDA pin swap is still present, but will be addressed in the next release/update.</p>
<table>
<tr>
<td> </td>
<td> <strong>On the Virtual Machine</strong> </td>
<td> <strong>On the Support git Server</strong> </td>
</tr>
<tr>
<td> <strong>5CSX Base</strong> </td>
<td> /home/user/mitysom_5csx_dev_board/base_project </td>
<td> <a class="external" href="http://support.criticallink.com/gitweb/?p=mitysom-5cs/mitysom_5csx_dev_board.git;a=summary">http://support.criticallink.com/gitweb/?p=mitysom-5cs/mitysom_5csx_dev_board.git;a=summary</a> </td>
</tr>
<tr>
<td> <strong>5CSE Expanded IO</strong> </td>
<td> /home/user/mitysom_5cse_dev_board/dev_exp_5cse_l2_3y8_base </td>
<td> <a class="external" href="http://support.criticallink.com/gitweb/?p=mitysom-5cs/mitysom_5cse_dev_board.git;a=summary">http://support.criticallink.com/gitweb/?p=mitysom-5cs/mitysom_5cse_dev_board.git;a=summary</a> </td>
</tr>
</table>
<p>B) Concerning the datasheet discrepancy it has HSMC1_SMSDA and HSMC1_SMSCL mapped to the proper HSMC pins however the SoM pin column is incorrect for these pins. HSMC1_SMSDA should be SoM pin 52 and HSMC1_SMSCL should be SoM pin 54. You are correct on the bank voltage 3B vs 4A discrepancies.</p>
<p>We have created action items for these discrepancies (the datasheet ones were already noted just not published yet unfortunately) and will get them addressed.</p>
<p>C) Concerning the direction change for the HSMC1 pins mentioned if your usage for them is low speed then that should be fine however if you are trying to do high speed, I.E. use the HSMC1_CLKOUT0 as a CLK input, you may run into issues. If you have further concerns about this please let us know what specific use case you have planned for each pin and we can provide some feedback and/or recommendations.</p>
<p>Thanks,</p>
<p>Alex</p> FPGA Development: HSMC1 pinouthttp://support.criticallink.com/redmine/boards/47/topics/44342015-05-26T03:54:06ZFlorian Riegerflorian.rieger@ruag.com
<p>Hi,</p>
<p>I am using the <a href="https://support.criticallink.com/redmine/boards/47/topics/3348?r=3352#message-3352" class="external">mityarm_5csx_dev_board_hsmc_setup.tcl</a> to define the pinout of the HSMC1 interface of my FPGA design, and found a discrepancy in the documentation. Based on the <a href="https://support.criticallink.com/redmine/attachments/download/5875/80-000578RC-4_SCH_RevA.PDF" class="external">schematic</a>, I assume the signals HSMC1_SMSDA/HSMC1_SMSCL need to be interchanged in mityarm_5csx_dev_board_hsmc_setup.tcl. The <a href="https://support.criticallink.com/redmine/attachments/download/5876/MitySOM-5CSX_Development_Kit_Datasheet.pdf" class="external">MitySOM-5CSX Development Kit</a> seems to be wrong on the documentation of the HSMC1_SMSCL signal too (BTW - HSMC1_CLKIN0, HSMC1_TX9_P and HSMC1_TX9_N are associated to a bank 3B instead of 4A).</p>
<p>The attached spreadsheet merges the information found in the documentation and shows the discrepancy. I suppose hat the HSMC1 pins 33 (HSMC1_SMSDA) and 34 (HSMC1_SMSCL) are connected to the FPGA pins AF28 and AF27 respectively, can you validate this assumption?</p>
<p>For my design, I would also like to reuse/reassign some output signals as inputs for the FPGA (i.e. HSMC1_SMSCL, HSMC1_PRSNTn, HSMC1_CLKOUT0), are there any limitations from the base board that I must consider if I flip the direction of these pins (except that my HSMC daughter card must reflect those changes)?</p>
<p>Thanks,<br />Florian</p> FPGA Development: RE: Example projecthttp://support.criticallink.com/redmine/boards/47/topics/4388?r=4389#message-43892015-04-09T09:26:47ZMichael Williamson
<p>Hi Malcom.</p>
<p>I will check on the memory init files issue. I seem to recall that those can be ignored, but I don't remember why off-hand.</p>
<p>The missing pin assignments will work (they are the HPS fixed pin assignments, and the fitter will assign the correct locations). You can run back-annotation from a compiled design to get the assignments and update the project QSF file. We have done that a couple of times since 13.1 but it looks like that example project didn't get updated to include the mappings. I will see that we update it.</p>
<p>Sorry for the confusion.</p>
<p>-Mike</p> FPGA Development: Example projecthttp://support.criticallink.com/redmine/boards/47/topics/43882015-04-09T08:20:18ZMalcolm Hartnell
<p>I've just started to evaluate the MitySOM-5CSX board and the first thing I did was install VirtualBox and the supplied Xubuntu image. After compiling the included example project in Quartus II 14.0 I noticed some critical warnings and some ignored assignments. I also tried the example project on this Wiki and that will not even compile without renaming one of the modules in qsys. Is there an example project available from Critical Link that is clean (and preferably uses Quartus II 14.0 or 14.1)?</p>
<p>Some example warnings:<br />Critical Warning (127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File /home/user/projects/mitysom_5csx_dev_board/base_project/build/hps_AC_ROM.hex -- setting all initial values to 0<br />Critical Warning (127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File /home/user/projects/mitysom_5csx_dev_board/base_project/build/hps_inst_ROM.hex -- setting all initial values to 0</p>
<p>Critical Warning (169085): No exact pin location assignment(s) for 83 pins of 279 total pins. <br />Critical Warning (174073): No exact pin location assignment(s) for 1 RUP, RDN, or RZQ pins of 2 total RUP, RDN or RZQ pins</p>
<p>Thanks,<br /> Malcolm</p> FPGA Development: RE: Load FPGA from uboothttp://support.criticallink.com/redmine/boards/47/topics/4290?r=4295#message-42952015-01-06T09:52:48ZDaniel Vincelettedvincelette@criticallink.com
<p>Hi Jack,</p>
<p>You would use the <strong>editenv</strong> command.</p>
<pre>
editenv fpgafile
</pre>
<p>Then to save this change to the SD card you would use <strong>saveenv</strong> or you will lose this change after a reboot.</p> FPGA Development: RE: Load FPGA from uboothttp://support.criticallink.com/redmine/boards/47/topics/4290?r=4292#message-42922015-01-05T16:46:30ZAnonymous
<p>Hi Dan,</p>
<p>How do I change the fpgaimage uboot variable?</p>
<p>Thanks,</p>
<p>Jack</p> FPGA Development: RE: Load FPGA from uboothttp://support.criticallink.com/redmine/boards/47/topics/4290?r=4291#message-42912015-01-05T16:28:21ZDaniel Vincelettedvincelette@criticallink.com
<p>Hi Jack,</p>
<p>That SD card image will automatically load the rbf file that is on the second partition at /home/root/mityarm_5csx_dev_board.rbf during uboot.</p>
<p>If you would like to boot a different rbf then you will need to update the <strong>fpgaimage</strong> uboot variable to point to the new image.</p>
<p>For example if you have a rbf file called <strong>new_image.rbf</strong> in <strong>/home/root</strong> you would need to change <strong>fpgaimage</strong> to <strong>/home/root/new_image.rbf</strong>.</p>
<p>The rocketboards guide is meant for an SD card that has a FAT partition, which the Critical Link does not have. Instead we load it directly from the ext root file system partition.</p> FPGA Development: Load FPGA from uboothttp://support.criticallink.com/redmine/boards/47/topics/42902015-01-05T15:28:09ZAnonymous
<p>Hi,</p>
<p>I tried to follow the instruction in "http://rocketboards.org/foswiki/Documentation/LoadingFPGAFromUBoot".</p>
<p>But I ran into difficulties where it complains that my file format is not correct.</p>
<p>The development kit sd card image I used is from <a class="external" href="http://support.criticallink.com/files/mitysom-5csx/sd_image_mitysom_5csx_rev1B.zip">http://support.criticallink.com/files/mitysom-5csx/sd_image_mitysom_5csx_rev1B.zip</a>.</p>
<p>I loaded my rbf FPGA file ("fpga.rbf") to the FAT partition (which is empty for some reason, about 250-260 MB).</p>
<p>I followed the instructions exactly as seen on the Rocket board webpage, and it returned the error complaining about format ("-4").</p>
<p>Thanks,</p>
<p>Jack</p> FPGA Development: 100MHz Input clock (CLK2 - DDR3) Issuehttp://support.criticallink.com/redmine/boards/47/topics/42792014-12-11T19:50:32ZAlexander Blockalex.block@criticallink.com
<p>A customer has the 100MHz DDR3 clock being fed into the module through Pins 117 and 119 on a custom carrier board and is using it to clock some ADC data. However after a little run-time it stops working as noted below:</p>
<pre>
I'm having a really weird problem with the DDR3 100Mhz clock. I included this in my design from your eval board, however I am not
using it as a clock for the FPGA RAM. I'm using it to clock out two ADC clocks. That aspect of the design works fine. Its when I use the
clock internally that I run into problems.
Case in point: I have a logic block that uses this clock as a count down to initiate a burst of a FIFO-full of ADC input data. With this clock,
I set a timer to fill the buffer full of data every 5 seconds. The frustrating part of this is that it WORKS for about 10-15 fifo-fuls of data but then
it stops. As best I can tell, the millisecond strobe I use based off this clock stops being registered by the logic so it sits in the idle stage.
When I used the 100Mhz HPS user 0 clock instead, it works like a charm.
The DDR3Clock goes through an altera_pll block with a multiplier of 1 so it just basically goes through.
Any idea how I can get this to work?
</pre> FPGA Development: RE: Writing to HPS memoryhttp://support.criticallink.com/redmine/boards/47/topics/4270?r=4271#message-42712014-11-25T07:46:39ZMichael Williamson
<p>I would recommend contacting your Arrow FAE or Altera for help with the device tree generation / sopcinfo file.</p>
<p>You will need to create a new preloader and uboot and device tree block. You may also need to rebuild the kernel with the correct drivers for their board enabled.</p>
<p>-Mike</p> FPGA Development: Writing to HPS memoryhttp://support.criticallink.com/redmine/boards/47/topics/42702014-11-25T07:39:56ZVidya Govindanvgovindan@tonboimaging.com
<p>Hi,</p>
<p>I'm want to use the hps_ddr_write_example design from critical link and test it on Arrow Terasic Cyclone V SOCKit .<br />I have changed the device and the HPS DDR3 parameters in the Quartus project.Also I'm using the Arrow kit's DDR3 pin assignments for the proper pin mapping.<br />I'm having problem with generating the Device tree for this project. There seems to be problem with the .sopcinfo file. I'm assuming since the hardware is changed I have to regenerate the software part.I have generated preloader and uboot.<br />Can anyone help me on the same?I'm new to OS porting and linux.</p> FPGA Development: RE: Modular SGDMAhttp://support.criticallink.com/redmine/boards/47/topics/4228?r=4248#message-42482014-11-07T14:22:53ZDaniel Vincelettedvincelette@criticallink.com
<p>Hi Jack,</p>
<p>We don't have any explicit examples of this but you will want to look into the userspace I/O driver. This should allow you to map in the FPGA interrrupts to a /dev/uio device.</p>
<p>I did a bit of searching and this looks like a good start: <a class="external" href="http://yurovsky.github.io/2014/10/10/linux-uio-gpio-interrupt/">http://yurovsky.github.io/2014/10/10/linux-uio-gpio-interrupt/</a>.</p>
<p>A quick example of a device tree entry for hooking up a UIO driver to FPGA IRQ 0 it would look something like:</p>
<p>uio0: uio0@20000000 { <br /> compatible = "uio,irq"; <br /> interrupts = <0 40 4>; <br />};</p>
<p>40 is the FPGA 0 IRQ, gotten from here <a class="external" href="http://www.altera.com/literature/hb/cyclone-v/cv_54006.pdf#unique_42">http://www.altera.com/literature/hb/cyclone-v/cv_54006.pdf#unique_42</a> and subtracted 32 from the value in the GIC Interrupt Number. The 4 means the interrupt will trigger when the line goes high.</p>
<p>Dan</p> FPGA Development: RE: Modular SGDMAhttp://support.criticallink.com/redmine/boards/47/topics/4228?r=4247#message-42472014-11-05T13:40:06ZAnonymous
<p>Hi Dan,</p>
<p>The issue seems to be with the polling. I brought out the empty signal to an oscilloscope and found that it is on, but for some reason I'm not reading that on the software side.</p>
<p>I think it's better to switch to interrupt to deal with the issue. Do you have an example of doing interrupt?</p>
<p>I tried adding the interrupt files in Altera found in the "embedded\ip\altera\hps\altera_hps\hwlib\include", but ran into various issues.</p>
<p>Thanks,</p>
<p>Jack</p> FPGA Development: RE: Modular SGDMAhttp://support.criticallink.com/redmine/boards/47/topics/4228?r=4230#message-42302014-10-20T16:34:19ZAnonymous
<p>Hi Dan,</p>
<p>I polling the FIFO empty signal for the both the dispatcher and write master to ensure that only when both FIFOs are empty when I will continue.</p>
<p>The delay varies, it's hard to predict.</p>
<p>Ideally we don't want to put any sleep there because we need the program to function. The code in between each time I call the write master is about 0.5 second. Does the write master and dispatcher not like to be flooded a stream requests?</p>
<p>Thanks,</p>
<p>Jack</p> FPGA Development: RE: Modular SGDMAhttp://support.criticallink.com/redmine/boards/47/topics/4228?r=4229#message-42292014-10-17T16:53:08ZDaniel Vincelettedvincelette@criticallink.com
<p>Hi Jack,</p>
<p>You could try polling the dispatcher's busy bit instead but I'm not quite sure if that would solve your issue. Any idea at how long the delay is for? Does the FIFO overflow because of it? Also you might want to put a bit of a sleep inside your infinite while loop just so the system doesn't lock up, if you haven't already.</p>
<p>Dan</p> FPGA Development: Modular SGDMAhttp://support.criticallink.com/redmine/boards/47/topics/42282014-10-17T15:57:08ZAnonymous
<p>Hi</p>
<p>I'm running into a difficulty with the Modular SGDMA that is used in the HPS Memory example.</p>
<p>I have to send dispatchers repeatedly in a infinite loop. I have it designed such that after I send the command to write the dispatcher, I wait until (on a white loop) I see both the FIFO for the dispatcher and the write master is empty and then I will proceed to the rest of my system and then back to writing the dispatcher.</p>
<p>However, I noticed that, in a rather random pattern, the system will just get stuck on the while loop waiting for the FIFO to be empty. The delay is rather random as well. Then after that the system continues on.</p>
<p>Any idea why there would be a delay for the FIFO in these systems to trigger the empty signal, especially when I only write my commands when they are empty.</p>
<p>Thanks,</p>
<p>Jack</p> FPGA Development: RE: HPS Memory Controllerhttp://support.criticallink.com/redmine/boards/47/topics/3382?r=4227#message-42272014-10-02T12:53:38ZAnonymous
<p>Hi,</p>
<p>Just raising this subject again. I'm going through the document for the sgdma_dispatcher, but do you guys have an example where you check to see if the dispatcher has finished transferring?</p>
<p>I tried reading the CSR Status register but not sure which one would precisely do the job. If it's the IRQ, don't I need a ISR to deal with that, if so do you have any examples of this or can I just poll it?</p>
<p>Thanks,</p>
<p>Jack</p> FPGA Development: RE: Load FPGA Timeout Errorhttp://support.criticallink.com/redmine/boards/47/topics/3551?r=4193#message-41932014-09-17T11:29:24ZAlexander Blockalex.block@criticallink.com
<p>Max,</p>
<p>Thank you for posting that.</p>
<p>You are correct that if VBAT is too low the module will either not boot at all and/or will not allow the FPGA to be programmed. We believe that on earlier development kits the ESD bags may have contacted the battery terminals on the bottom of the board and caused some amount of premature discharging. We now use some Kapton tape to cover these terminals to help prevent such discharge.</p>
<p>In the newest module designs we have added a diode-or circuit to the VBAT input which will allow the module to boot in the event that the RTC battery has failed.</p>
<p>We will post an VBAT/RTC wiki page to cover these concerns and apologize for the amount of time it took to determine the cause in your case.</p>
<p>Thanks,</p>
<p>Alex</p> FPGA Development: RE: Load FPGA Timeout Errorhttp://support.criticallink.com/redmine/boards/47/topics/3551?r=4192#message-41922014-09-17T10:41:39ZMassimo Burattomassimo.buratto@teamware.it
<p>Hi Dan,</p>
<p>I had similar problem last week. After two week I tried to run my development board loading the FPGA with JTAG and using Uboot.<br />JTAG was not able to connect and with Uboot the return message was:</p>
<p>altera_load: Failed with error code -1</p>
<p>After two hours I've discovered that the problem was the discharged battery connected to +3V_VBAT pin of the EVB SOM connector.<br />The battery is for the backup of security key registers. The pin must be always connected to a power source.</p>
<p>I've changed the battery and all run again.</p>
<p>Max</p> FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)http://support.criticallink.com/redmine/boards/47/topics/4078?r=4084#message-40842014-07-24T09:05:18ZAdam Dziedzicadam.dziedzic@criticallink.com
<p>Hi Nigel,</p>
<p>I don't believe there is a way to do it directly in QSYS. You may be able to patch your generated outputs to get over that hurdle. As you would expect, Altera has the normal minimum frequency requirement programmed in so users avoid the memory cells fading early due to longer clock cycles. If this is a need for your project and you would like some additional help, we could open a project contract to help get through the requirement. The simplest and most cost effective solution would be to run at 300MHz.</p>
<p>- Adam</p> FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)http://support.criticallink.com/redmine/boards/47/topics/4078?r=4083#message-40832014-07-24T07:59:28ZNigel Doendoe@tainstruments.com
<p>Hi Adam,</p>
<p>Thanks for the insights.</p>
<p>Do you know how to persuade qsys to run the DDR at a slower speed? In normal use it will not allow anything less than 300MHz.</p>
<p>Thanks,<br />Nigel.</p> FPGA Development: RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)http://support.criticallink.com/redmine/boards/47/topics/4078?r=4079#message-40792014-07-23T16:19:02ZAdam Dziedzicadam.dziedzic@criticallink.com
<p>Hi Nigel,</p>
<p>You are correct, the C8ES devices do not meet timing with the FPGA DDR according to Quartus. The ES silicon was not qualified to any faster speed grades than C8, though it does work according to our tests. We designed the SOM targeting the C7 speed grade devices and there is some margin with those devices. The C8ES modules are intended for evaluating the product and getting started on a design. The production devices have been built up and will provide more margin that is qualified by the Quartus build tools and device qualification. According to our internal test results, there is some margin on the FPGA DDR interface with the C8ES devices, though we have not quantified it.</p>
<p>There are two approaches to getting a Quartus build.</p>
<ol>
<li>You can run the build with the C8ES target device and ignore the timing violations for the FPGA DDR interface.</li>
<li>Alternatively, the Quartus project could target the C7 device and assume the C8ES will meet timing of a C7.</li>
</ol>
<p>Neither path is perfect, but we have used both with success.</p>
<p>One other comment... The FPGA DDR interface has the address and data buses split across two sides of the device. Because of this, the fractional PLL used is important and should match the example. The clock input is also called out in the schematic to have the proper clock input with a dedicated path feeding the fPLL needed by the FPGA DDR interface.</p>
<p>If you do Not need the bandwidth available, it is possible to run the DDR slower. Micron has some app notes covering the changes required to run the DDR3 memory at a slower clock speed. These are, in general, more refresh cycles to keep the memory cells active. With the slower clock speed, the time between refresh commands is maintained by calling refresh commands after fewer clock cycles.</p>
<p>Thanks,<br />Adam</p> FPGA Development: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)http://support.criticallink.com/redmine/boards/47/topics/40782014-07-23T13:27:23ZNigel Doendoe@tainstruments.com
<p>Although your reference design using FPGA DDR compiles as supplied, when I select the correct device (5CSXFC6C6U23C8ES) for my hardware I get timing violations on the FPGA DDR that I have been unable to fix.</p>
<p>I cannot create extra margin as I cannot lower the DDR clock below the 300MHz minimum and I cannot implement using the hard memory controller as the pin selection is not suitable.</p>
<p>Any suggestions on how to overcome this?</p>
<p>Nigel.</p> FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocolhttp://support.criticallink.com/redmine/boards/47/topics/3961?r=4006#message-40062014-07-03T17:14:20ZAdam Dziedzicadam.dziedzic@criticallink.com
<p>Hi Bill,</p>
<p>Sorry for the confusion. The latest image updated the Baud Rate to 115.2kbps to be consistent with the rest of the Critical Link modules.</p>
<p>- Adam</p> FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocolhttp://support.criticallink.com/redmine/boards/47/topics/3961?r=4005#message-40052014-07-03T17:05:04ZBill Leebill@1stsemi.com
<p>Hi,</p>
<p>I downloaded the sd_image_mitysom_5csx_rev1B.zip, and extracted out the .bin file. Then I typed "sudo dd if=sd_image_mitysom_5csx_rev1B.bin of=/dev/sdb bs=1M" into a brand new 8GB MicroSDHC sd card. Next, I typed "sync" as instructed in the ../wiki/Building_SD_Card_Image/ session. After that, I plug the sd card in the sd card slot of the dev. board. As usual, I brought up the terminal window with the setting of "baud rate=57600; data=8bits; parity=0; stopbits=1; flowcontrol=0". But the terminal showed unrecognize characters on the screen. Do I need to load in any other files in the SD card?</p>
<p>Thanks,</p> FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocolhttp://support.criticallink.com/redmine/boards/47/topics/3961?r=4000#message-40002014-07-02T21:27:52ZAlexander Blockalex.block@criticallink.com
<p>Information on how to make an SD card based upon the current Development Kit SD card image (Rev 1B) can be found on this wiki page (<a class="external" href="https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_SD_Card_Image">https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_SD_Card_Image</a>) in the "Development Kit SD Card Image" section.</p>
<p>-Alex</p> FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocolhttp://support.criticallink.com/redmine/boards/47/topics/3961?r=3998#message-39982014-07-02T18:17:08ZBill Leebill@1stsemi.com
<p>Mike,</p>
<p>I think you meant "memtool -32 0xFFD0501C=0x06" for brgmodrst register. The reset value of the register somehow shows "0x00000000". So, I set it to 0x7, then 0x6, to make sure the hps2fpga bridge get reset and release the reset.</p>
<p>We purchased the dev. kit last year. That may be the reason why the kernel version is out of date. I would prefer that I can get a up-to-date version of the SD card image from you. Please let me know when you found the new image.</p>
<p>By the way, if I use memtool to access fpga address space, what the address range should be? Can I use "memtool -32 0xc0000000 1" to access the first location of the FPGA region?</p>
<p>Thanks again,</p> FPGA Development: RE: How to access FPGA internal memory through AXI slave interface protocolhttp://support.criticallink.com/redmine/boards/47/topics/3961?r=3995#message-39952014-07-02T08:52:56ZMichael Williamson
<p>For reference on the reset register:</p>
<p><a class="external" href="http://www.altera.com/literature/hb/cyclone-v/hps.html#reg_default_component/register_rstmgr_brgmodrst.html">http://www.altera.com/literature/hb/cyclone-v/hps.html#reg_default_component/register_rstmgr_brgmodrst.html</a></p>