Configuring the QUP Ports (I2C, I3C, SPI and UART)¶

The MitySOM-QC can be configured to support a variety of serial interfaces.

Details on which QUP pins are accessible can be found in the MitySOM-QC Datasheet

Details on how the QUP pins can be configured can be found here

Changing the QUP Configuration¶

The default QUP configuration for the Critical Link BSP is setup to support protocols needed for the Development Kit operation, while leaving all other pins as GPIOs. Details on this configuration can be found here.

Making changes to the default QUP configuration consists of two parts:

1. That the kernel devicetree be updated
2. That the QUP serial engine firmware be properly loaded, which can happen in one of two ways:
   1. The first (and properly secure) option is to build the TrustZone firmware
      1. Note: The source for this firmware is not something Critical Link can distribute. You must make an account with Qualcomm and reach out about becoming a "Licensed developers with authorized access." See https://www.qualcomm.com/support/working-with-qualcomm for further details.
   2. The second option is to have Linux load the firmware for the QUP v3 serial engine
      1. Note: Critical Link has not personally validated this methodology as of yet. We will update this page when we have in case there are any caveats that should be known.

LPI QUP¶

NOTE: The LPI (Low Power Island) QUP pins are connected to the LPI subprocessor (see the 'Processor' section) and are not configurable the same way as other QUP pins (the LPI pins use the LPI TLMM as opposed to the regular TLMM). For this reason, it is recommend to design these into a project as QUP pins as a last option and to use the standard QUP pins first.

LPI QUP support is currently under investigation and this section will be updated with instructions as this is validated.

Issues¶

If you have any issue please make sure to post in the forums so that we can provide support.