The tcDspFpgaIir class may be used to provide access to a single IIR Filter core. Each instance of DspFpgaIir provides access to up to 4 individual filters. These filters are arranged in 1-4 parallel paths. The number of paths (NP) is application-specific. The number of filters (NF) cascaded along each path is configurable, as follows:
Each filter makes use of 5 coefficients (B0, B1, B2, A1, and A2) as described below:
/// Xin --->+---->(xB0)---->(+)---->(+)-------------->+---> Yout /// | ^ ^ | /// Z-1 | | Z-1 /// | | | | /// +---->(xB1)---->(+) (+)<----(xA1)<----+ /// | ^ ^ | /// Z-1 | | Z-1 /// | | | | /// +---->(xB2)------+ +------(xA2)<----+ ///
There is no limit to the number of instances of tcDspFpgaIir that may be created, aside from the design of the FPGA module.
This is a simple example of tcDspFpgaIir creation and usage:
{ unsigned int my_base_addr = 0xB0000180; tcDspAwg *myIir; int numPaths, numFilters; int B0, B1, B2, A1, A2; float fB0, fB1, fB2, fA1, fA2; // create an IIR interface myIir = new tcDspFpgaIir((void *)my_base_addr); // determine paths available numPaths = myIir->GetPaths(); // attempt to set two cascaded filters per set if (myIir->SetFilters(2) == false) { // failed... number of paths must not be what app expected printf("Couldn't set NF to 2, NP is %1d\r\n", numPaths); return; } // set all filter coes (pass-thru in this simple example) B0 = tcDspFpgaIir::gnCoeffScale; B1 = B2 = A1 = A2 = 0; myIir->SetCoeffs(0, 0, B0, B1, B2, A1, A2); myIir->SetCoeffs(0, 1, B0, B1, B2, A1, A2); // can also pass coes as floating point (-2 < x < 2) fB0 = 1.0f; fB1 = fB2 = fA1 = fA2 = 0.0f; myIir->SetCoeffs(1, 0, fB0, fB1, fB2, fA1, fA2); myIir->SetCoeffs(1, 1, fB0, fB1, fB2, fA1, fA2); ... }