The tcDspAwg class may be used to provide access to a Dual AWG core. Each instance of DspAwgDual provides the capability to output two arbitrary waveforms, as defined by a sample RAM of 512 16-bit values, which are 15-bit interpolated across 24-bits of phase. The phase increment per clock may also be configured. The AWG may be started upon software command, or via an external trigger.
When created, the constructor requires a valid base address for the AWG core. The AWG core is not enabled after construction. The Enable() method must be called at least once to enable the outputs.
Each waveform must be configured via the SetWaveformSamples method. In addition, the SetPhase and SetPhaseIncrement methods should be called to set the starting phase and phase increment per clock for each waveform.
There is no limit to the number of instances of tcDspAwgDual that may be created, aside from the design of the FPGA module.
This is a simple example of tcDspAwgDual creation and usage: