tcDspAwg

Introduction

The tcDspAwg class may be used to provide access to a single AWG core. Each instance of DspAwg provides the capability to output a single arbitrary waveform, as defined by a sample RAM of 512 16-bit values, which are 15-bit interpolated across 24-bits of phase. The phase increment per clock may also be configured. The AWG may be started upon software command, or via an external trigger.

When created, the constructor requires a valid base address for the AWG core. The AWG core is not enabled after construction. The Enable() method must be called at least once to enable the outputs.

Each waveform must be configured via the SetWaveformSamples method. In addition, the SetPhase and SetPhaseIncrement methods should be called to set the starting phase and phase increment per clock.

There is no limit to the number of instances of tcDspAwg that may be created, aside from the design of the FPGA module.

See also:

MityDSP::tcDspAwg Class Reference

Example

This is a simple example of tcDspAwg creation and usage:

 {
     unsigned int my_base_addr = 0xB0000180;
     tcDspAwg    *myAwg;

     // create an AWG interface
     myAwg = new tcDspAwg((void *)my_base_addr);

     // create sample values (a ramp)
     unsigned int values[tcDspAwg::gnNumSamples];
     for (int i=0; i<tcDspAwg::gnNumSamples; i++)
     {
         values[i] = i*32;
     }

     // load the waveform table
     myAwg->SetWaveformSamples(values, tcDspAwg::gnNumSamples);

     // set the starting phase (in degrees in this case)
     myAwg->SetPhase(180.0, tcDspAwg::eeDegrees);

     // set the phase increment (in radians in this case)
     myAwg->SetPhaseIncrement(0.001, tcDspAwg::eeRadians);

     // trigger internally (i.e. start immediately upon enable)
     myAwg->SetExtTrigger(false);

     // Enable the AWG to output the waveform
     myAwg->Enable(true);

     ...
 }