@section intro_sec Introduction The tcDspFpgaIir class may be used to provide access to a single IIR Filter core. Each instance of DspFpgaIir provides access to up to 4 individual filters. These filters are arranged in 1-4 parallel paths. The number of paths (NP) is application-specific. The number of filters (NF) cascaded along each path is configurable, as follows: @li NP=1, NF=1-4 @li NP=2, NF=1-2 @li NP=3, NF=1 @li NP=4, NF=1 Each filter makes use of 5 coefficients (B0, B1, B2, A1, and A2) as described below: <TT> @verbatim
/// Xin --->+---->(xB0)---->(+)---->(+)-------------->+---> Yout /// | ^ ^ | /// Z-1 | | Z-1 /// | | | | /// +---->(xB1)---->(+) (+)<----(xA1)<----+ /// | ^ ^ | /// Z-1 | | Z-1 /// | | | | /// +---->(xB2)------+ +------(xA2)<----+ ///
There is no limit to the number of instances of tcDspFpgaIir that may be created, aside from the design of the FPGA module.
This is a simple example of tcDspFpgaIir creation and usage: