The tcDspPwm class may be used to provide access to a single PWM core. Each instance of DspPwm provides access to as many as 5 configurable pulse outputs, and installs an ISR at the Core interrupt level in order to report completions of fixed cycle (or one shot) pulse outputs, when enabled.
When created, the constructor requires a valid base address for the PWM core. Optionally, the user may provide a pointer to a tcDspPwmConfig structure to provide pulse initialization parameters. This structure is not referenced (and may be deleted or freed) after initialization. The PWM core is not enabled after construction. The Enable() method must be called at least once to enable the outputs.
Each pulse may be configured to have a fixed initial delay from a trigger event, then have a continuous period with a fixed OnTime (which occurs at the beginning of the defined period). The configuration method is ConfigurePulse(). Note that the OnTime must not exceed the total period time. Each of the 5 pulse outputs maybe enabled/disabled using the EnablePulse() Command.
There is no limit to the number of instances of tcDspPwm that may be created, aside from the design of the FPGA module.
Note: PWM class is not thread safe. It is assumed that only one controlling thread will access any one PWM object. If multi-thread access is required, the application must provide serialization interlocks.
This is a simple example of tcDspPwm creation and usage: