tcDspTlv254x

Introduction

The tcDspTlv254x class is used to set up and receive data from a TI TLV254X family A-to-D converter. The converter is accessed via a McBSP interface.

The converter uses the TMS320 FS control to initiate read sequences.

Note:

The channel numbers for the TLV-2548 chip run from 0-7. For the TLV-2544 chip, channel numbers increment by 2 (0, 2, 4, and 6). It is up to the user of this class to ensure that the proper channel numbers are passed in for the specific device being accessed.

See also:

MityDSP::tcDspTlv254x Class Reference

Example

This is a simple example of tcDspTlv254x creation and usage:

 {
     // This class controls the MityDSP FPGA, and provides
     // register interfaces for CS control lines, etc.  This
     // class is generally specific to a MityDSP application.

     class tcFPGA : public tcDspOutputLatch
     {
         ...         

     public:

         typedef enum
         {
           ...
           eeADC_CS,  
           ...
         } teOutputs;

         // This method manages the CS output latch for various devices
         int SetOuput(unsigned int ID, unsigned int Value);
        
         ...

     }

     int main (int argc, char *argv[])
     {

        tcFPGA     FPGA;
        tcDspMcbsp MCBSP(0x018C0000,
                         DATA_DELAY1,         // rx_data_delay
                         WORD_LENGTH_16,      // rx_word_len
                         RXJUST_RJZF,         // rx_justify
                         DATA_DELAY1,         // tx_data_delay
                         WORD_LENGTH_16,      // tx_word_len
                         FSYNC_MODE_EXT,      // rx_fsync
                         FSYNC_MODE_INT,      // tx_fsync
                         CLK_MODE_INT,        // rx_clock
                         CLK_MODE_INT,        // tx_clock
                         FSYNC_POL_HIGH,      // rx_fsync_polarity
                         FSYNC_POL_HIGH,      // tx_fsync_polarity
                         CLKR_POL_FALLING,    // rx_clock_polarity 
                         CLKX_POL_RISING,     // tx_clock_polarity
                         CSTOP_DISABLED);     // clock_stop
        
        tuCfrReg   config;
        config.mnWord = 0;
        config.msBits.REF_VOLTb = REF_2V;
        config.msBits.REF_SELb = REF_INT;

        tcDspTlv254x ADC(&MCBSP,config,&FPGA,tcFPGA::eeADC_CS);

        ADC.request_data(0); // select channel 0
        TSK_sleep(1);        // provide time to sample
        unsigned short adc_value = ADC.read_data(); // read channel 0 sample

     } 
 
 }