Index

MityDSP Hardware Release Notes



April 22, 2013
MDK Version 2.12.0 DualAWG Version 1.01
  1. Updated DualAWG to allow the frequency to be updated dynamically without disabling the waveform generation. This was accomplished by adding a new sync_to_a flag so that register values written to waveform B are not applied until the corresponding register is written to waveform A. Redmine #2929
MityDSP-Pro Bootloader FPGA
    Updated MityDSP-PRO 4K series default boot FPGA image to route on-board PHY ethernet status to reserved pins for proper LED operation on development kit and reference designs.


March 26, 2012
MDK Version 2.11.0 ADS8343 & ADS8344 Version 1.11
  1. Update reset_shift register to be on the i_clk domain. This is a config reset delay used to generate the chip select to the ADC and internal state machine logic. Redmine #1290
DualAWG Version 1.00
  1. Add a new core based on the AWG Core to support two separate AWG outputs while consuming only a single BRAM. Redmine #1269
AWG Version 1.03
  1. Updated trigger and enable logic. Redmine #1268
Added missing XCO, XAW, and batch files to Bootloader source area for distributions not including VHDL core source code.

Nov 1, 2011
MDK Version 2.10.1 No changes

Sep 21, 2011
MDK Version 2.10.0 ADS8343 & ADS8344 Version 1.10
  1. Updated a cross-clock domain metastability issue on the latest_sample register to the DSP. This should avoid any issue with the emif sitting on that register. Bugzilla #2019
I2C2 Core (I2C version 2.0) Added
  1. The I2C core was rewritten to support devices requiring 16 bit subaddressing (for example, larger PROMS such as the FM24CL64B). Because of the scope of the rewrite, the original i2c core (version 1.X) was preserved for legacy programs and to avoid regressions. Version 2 and above will be captured in the I2C2 netlists.
  2. Support for 10 bit slave addressing is included, but untested (no hardware platforms available at the time of this delivery).
  3. The number of bytes that may be transferred in one continuous cycle is now 65535. However, you may essentially extend that infinitely by controlling the issue of the stop control bit of the bus protocol. There will be a small delay between commands, however.
  4. Clock stretching/extension is not yet supported.
  5. Slave mode is not supported.


Jun 22, 2011
MDK Version 2.9.2 No changes

Jan 20, 2011
MDK Version 2.9.1 ADS8329 1.04
  1. Add capability to send an arbitrary command (including configuration word) to device. Supports software reset.
LCD DMA 1.02
  1. Add optional LCD reset output GPIO pin (defaulted to active on load) to support NEC display.
  2. Added lcd_serdes_cl000119.vhd back end to support NEC WQVGA glass.


March 4, 2010
MDK Version 2.9.0
  1. All Cores rebuilt using ISE 11.4 tool chain. Only .ngc are delivered (no more EDN's will be delivered).
ADS8329 Version 1.03
  1. Fixed bug for burst capture mode (which is off by 1, capturing 1 less sample than requested). Bugzilla #1892
UART Version 2.4
  • Add support for parity bits (odd, even, mark, space) as well as 5,6,7, and 8 bit word size. Bugzilla #287
  • ADS7843 Version 1.2
  • Add support to transfer commands to attached display SPI interface that may be shared with the Touch Screen SPI interface lines (as is the case for Critical Link developed touch screen assemblies). Also add support to poll GPIO status at touchscreen status update rates.


  • November 6, 2009
    MDK Version 2.8.2
    Timing Generator Version 1.03
    1. Added support for payload bits override. Bugzilla #1870
    ADS8329 Version 1.02
    1. Fixed bug for burst capture mode (which is off by 1, capturing 1 less sample than requested). Bugzilla #1871


    October 16, 2009
    MDK Version 2.8.1
    UART Version 2.03
    1. Fixed metastability issue in start bit detect logic Bugzilla #1861
    2. Added metastability flip-flops for i_dcd, i_ri, and i_dsr


    October 8, 2009
    MDK Version 2.8.0
    LCD_DMA Version 1.01
    1. Added serdes_wrapper synchronization ports for running the display at higher data rates (synchronization is optional). Running the LCD clock at 6.25MHz the QVGA refresh rate can be as high as 80Hz. Bugzilla #1855
    2. Added LCD controls:
    3. Improved clock timing adjustments
    4. Added lcd_serdes_cl000099 wrapper
    5. Added Modelsim simulation scripts and updated testbench
    6. Added lcd_serdes_84_0023_001T.vhd to replace lcd_serdes.vhd
    Camera Link Version 1.09
    1. Added additional framegrabber timing registers to support inverting lval and fval signals, and subsampling framed data to support various cameras that have additional pixels clocked out during valid frame intervals or don't provide subsampling interfaces (or developers don't want to write the interface). Bugzilla #1221
    UART Version 2.02
    1. Added metastability flip-flops for i_xmit_cts. Bugzilla #1845


    June 4, 2009
    MDK Version 2.7.0
    ADS7843 Core Version 1.01
    1. Slowed Touch ADC DCLK rate down to 100 KHz from 50 MHz EMIF clock to support MDK development kit (which shifts the data in/out via a serial shift register). Bugzilla #1718
    AD7760 Core Version 1.02
    1. Fixed wr_busy flag such that it asserts earlier, so it is not missed. Bugzilla #1733
    EZ_USB Core Version 1.07
    1. Added support for resetting DCM and reporting external clock lock status. This fix requires version 1.01 of the Cypress USB PC Drivers. Fixed dropping of data when inbound FPGA FIFO fills. Bugzilla #1751
    Timing Generator Version 1.02
    1. Rebuilt core to remove IOBs in blackbox netlist, which do not allow map to work. No functional changes. Bugzilla #1752
    2. Default Timing Generator core now supports 1024 block RAM entries. Bugzilla #1762


    March 17, 2009
    MDK Version 2.6.0
    EZ_USB Core Version 1.03
    1. Fixed EZ-USB core for FULL speed operation. Also fixed some potential HIGH speed issues. Bugzilla #1715
    LCD_DMA Core Version 1.00
    1. New LCD Controller core, which uses the new EMIF_SDRAM_DMA engine. Bugzilla #1328
    MityDSP and MityDSP-XM Bootloader FPGA Version 2.02
    1. Rebuilt with KEEPER enabled on USB UART input pins. Bugzilla #1542


    February 11, 2009
    MDK Version 2.5.0
    AD7760 Version 1.01
    1. Fixed bug in burst capture mode. Bugzilla #1570
    Clock1305 Core Version 1.01
    1. Added Alarm interrupt generation capability. Bugzilla #1613
    UART Version 2.01
    1. Added Xmit-Enable output port. Bugzilla #1658
    EZ_USB Core Version 1.02
    1. Fixed binaries for high speed Cypress USB Core. Bugzilla #1674
    MityDSP and MityDSP-XM Bootloader FPGA Version 2.01
    1. Updated code to current standards.
    MityDSP-Pro Bootloader FPGA Version 1.01
    1. Added 50MHz clock input, and updated code to current standards.


    October 27, 2008
    MDK Version 2.4.0
    AD7760 Version 1.00
    1. New AD7760 ADC Interface Core.
    EZ_USB module 1.02
    1. New high speed Cypress USB Core.


    September 2, 2008
    MDK Version 2.3.0
    Ethernet Module 2.02
    1. Added multiple MAC filters and promiscuous mode for IGMP support. Bugzilla #1363
    2. Added packet filtering capability to ethernet module, supporting PtP FPGA based timestamping and other RTP data injection into MAC layer inbound and outbound data streams. Bugzilla #1424
    EMIF_Iface module 1.01
    1. Added optional DMA interface ports for FPGA controlled SDRAM read or write transfers. Bugzilla #1310
    Camera Link Version 1.08
    1. Added capability to transfer camera link data directly to SDRAM via EMIF_Iface DMA engine. Bugzilla #1327
    Clock1305 Core Version 1.00
    1. Baselined version of RFC 1305 compliant FPGA local clock. Bugzilla #1364
    Gpio Version 1.03
    1. Fixed bug where MSB of GPIO pins may not generate input interrupt. Bugzilla #1397


    May 16, 2008
    MDK Version 2.2.0
    Camera Link Version 1.07
    1. Added frame decimation register to support decimation of frames on fast cameras. Bugzilla #1218
    Base Module 1.08
    1. Added DCM reset logic to base module for consistent EMIF DCM resets across MityDSP designs. Added 4 ms clock enable output (25 MHz domain). Bugzilla #1253


    March 5, 2008
    MDK Version 2.1.0
    Ethernet Version 2.00
    1. Offset both Transmit and Receive buffers by 2 bytes in order to support direct DMA transfers from the DSP (without addition buffer copies). This was required as the DSP required certain IP layer fields to be 4 byte aligned in order to avoid additional buffer copies. Due to the nature of this change, version 2.00 of the ethernet core is no longer compatible with prior MDK versions of software. This change allows nearly a 3x improvement in ethernet stack performance and was deemed necessary to support new MityDSP realtime applications. Bugzilla #1096
    LCD Serial Deserializer
      Added additional flip-flops to ease meeting timing and meta-stability issues. Bugzilla #1102
    Camera Link Version 1.00
    1. Introduced. Bugzilla #1036
    ADS834x Version 1.09
    1. Added latest-sample register. Bugzilla #1136
    2. Combined ADS8343 and ADS8344 source directories into one ADS834x directory which generates two outputs.
    ADS8402 Version 1.04
    1. Added latest-sample register. Bugzilla #1136


    November 1, 2007
    MDK Version 2.01
    GPIO Source VHDL
    1. The source code for the GPIO core has been included in all distributions for optimized building. The GPIO core includes a default direction setting, which allows for an optional 32 bit vector (rather than a sized reference by the NUM_IO generic, see Bugzilla #1040) defining the default IO direction on reset.
    SPI Transciever Version 2.02
    1. Change MOSI level to be updated on write side (EMIF) side for correct level reporting. Resolves Bugzilla #1049


    September 21, 2007
    MDK Version 2.00
    Ethernet Version 1.04
    1. Decode Tx/Rx FIFOs at address offsets 0x40 through 0x7F in order to support MityDSP Pro DMA due to 645x EMIF erratas. Resolves Bugzilla #1017
    ADS8402 Version 1.03
    1. Decode FIFO reads additionally at address 0x40 through 0x7F in order to support MityDSP Pro DMA due to 645x EMIF erratas. Resolves Bugzilla #1017
    ADC9235 Version 1.03
    1. Decode FIFO reads additionally at address 0x40 through 0x7F in order to support MityDSP Pro DMA due to 645x EMIF erratas. Resolves Bugzilla #1017
    ADS8329 Version 1.01
    1. Decode FIFO reads additionally at address 0x40 through 0x7F in order to support MityDSP Pro DMA due to 645x EMIF erratas. Resolves Bugzilla #1017
    ADS834x Version 1.08 (1.07 skipped - internal release)
    1. Force chip select to toggle during power/up or reset in order to ensure a falling edge is detected by part correctly as CS is held low during normal operation. Resolves Bugzilla #969
    2. Decode FIFO reads additionally at address 0x40 through 0x7F in order to support MityDSP Pro DMA due to 645x EMIF erratas. Resolves Bugzilla #1017
    Stepper3967 Version 1.03
    1. Added current control flags to register definitions, added software control of MS flags. Resolves Bugzilla #1002
    LCD_serdes_wrapper Version 1.00
    1. Updated display timing to drive the standard Sharp portrait QVGA LCD. Resolves Bugzilla #1003
    2. Removed IOB instantiation within wrapper. Should be included in top level Resolves Bugzilla #1010
    UART Version 2.00
    1. Moved location of read FIFO register and MSR register to offset 0x0c and 0x10, respectively in order to support MityDSP Pro builds. The MityDSP-Pro DSP does not appear to assert byte enable strobes on read access logic. This UART will only work with software build using MDK 2.0. Resolves Bugzilla #1007
    MityDSP and MityDSP-XM Bootloader FPGA Version 2.00
    1. Rebuilt using UART Version 2.0 and new base module source code (which supports MityDSP Pro in common code). Resolves Bugzilla #1012
    MityDSP-PRO Bootloader FPGA Version 1.00
    1. Baseline Support for MityDSP-PRO. Resolves Bugzilla #1012


    June 13, 2007
    MDK Version 1.12.2
    SPI Transciever Version 2.01
    1. Fixed intermittent problem with extra output word being clocked. Fixed FIFO EMPTY Status Flag. Fixed reset condition to not clock data into the miso FIFO on startup. Resolves Bugzilla #942
    ADS7843 Version 1.00
    1. Baseline touchscreen controller. ADS7843. Resolves Bugzilla #641
    MityDSP XM DMA Engine Version 1.00
    1. SDRAM DMA engine, controlled via FPGA. Necessary to support QVGA LCD display. Built for MityDSP XM SDRAM timings. Baseline version. Resolves Bugzilla #639
    LCD Controller Engine Version 1.00
    1. QVGA LCD Control module. Supports QVGA color resolution and includes control for dimming backlight via PWM adjustment on LED control. Resolves Bugzilla #928


    May 4, 2007
    MDK Version 1.12.0
    Core VHDL Source Code
    1. Updated Quad Encoder VHDL file to fix problem where no quadrature pulses are detected ("lock-up"). Resolves Bugzilla #790
    ADS834x Version 1.06
    1. Fixed issue with first sample being bad following disabling of continuous mode capture. Resolves Bugzilla #368
    ADS8329 Version 1.00
    1. Baseline delivery of TI (Burr Brown) ADS8329 16-Bit 1 MHz serial interface ADC. Resolves Bugzilla #774
    ADS8402 Version 1.02
    1. Firmware now provides required reset to the ADS8402 at power up. There is also a reset bit in the CCR to force a reset. Resolves Bugzilla #535
    SPI Transciever Version 2.00
    1. Added receive functionality to the SPIT core. Resolves Bugzilla #736
    2. The SPIT core version 2.00 is not compatible with prior MDK software drivers.
    3. Added clock polarity software control.
    4. Added controlled clock mode (the output clock may be gated or allowed to free run) control.
    Timing Generator Version 1.00
    1. Added baseline version of Timing Generator Core, version 1.00. Resolves Bugzilla #459


    February 7, 2007
    MDK Version 1.11.1
    MityDSP Bootloader FPGA Version 1.08
    1. Corrected errors in 1.07 build. Watchdog timer is not connected in Bootloader FPGA due to conflicts with MityDSP Rev.C DSP CLKOUT3 signal. Resolves Bugzilla #679


    November 14, 2006
    MDK Version 1.11.0
    MityDSP Bootloader FPGA Version 1.07
    1. Rebuilt with new base_module to support masked interrupts, watchdog timer, and bank address clearing. Resolves Bugzilla #414, #498
    Base_Module Version 1.06
    1. Added scratch pad RAM (16 x 32-bit) @ offsets 0x40 thru 0x7f. Part of Bugzilla #436 Resolution
    2. Added a bank-zero clearing input port (for system resets). Part of Bugzilla #436 Resolution
    3. Added a watchdog timer. Part of Bugzilla #436 Resolution
    4. Changed bank_sel & sba_clk signal to tri-state enables. Resolves Bugzilla #498


    September 18, 2006
    MDK Version 1.10.0
    MityDSP Bootloader FPGA Version 1.06
    1. Updated Bootloader to include UART Version 1.5 Resolves Bugzilla #389
    Base_Module Version 1.05
    1. Added individual IRQ source masking capability. Also added a version register for the core itself (@ offset 0x18). Resolves Bugzilla #327
    UART Version 1.06
    1. Changed receive interrupt logic to only generate Rx interrupts if the receive FIFO is 1/2 Full or if the receive FIFO is not empty and 300 usecs have transpired. (reduce IRQ rate for higher BAUD rate configurations). Resolves Bugzilla #389
    BiQuad IIR Filter Version 1.04
    1. Initial delivery of FPGA based fixed point Infinite Impulse Response (IIR) filtering core. Resolves Bugzilla #360
    AWG Version 1.02
    1. Fixed a few bugs, and added phase roll-over output. Resolves Bugzilla #384 & #386
    2. Added sample enable input for more clocking flexibility.
    ADS8402 Version 1.01
    1. Updated trigger logic to use level instead of edge sensitivity Resolves Bugzilla #402
    2. Split capture logic from front end in order to support external filtering and capture engine Resolves Bugzilla #403


    June 20, 2006
    MDK Version 1.9.0
    ADS8344 and ADS8343 Version 1.05
    1. Fixed problem in continuous mode of operation (only) that caused flipping of even and odd words in the data FIFO for random start events. Resolves Bugzilla #333
    2. Fixed problem where 2 bursts worth of data are collected (instead of 1) in burst collect mode. Changes do not effect continuous mode of operation. Resolves Bugzilla #343
    ADS8402 Version 1.00
    1. Initial Baseline of ADS8402 16-bit 1 MHz ADC core for MityDSP Resolves Bugzilla #323
    AWG Version 1.00
    1. Initial Baseline of Arbitrary Waveform Generator Core for MityDSP Resolves Bugzilla #352


    May 11, 2006
    MDK Version 1.8.0
    Pulse Integrator Version 1.2
    1. Fixed intermittent value error due to register reset race condition Resolves Bugzilla #331


    April 5, 2006
    MDK Version 1.7
    Base_Module Version 1.04
    1. Fixed bank select logic. Resolves Bugzilla #305
    PulseIntegrator Version 1.1
    1. Introduced. Resolves Bugzilla #215
    MityUART Core Version 1.4
    1. Added Modem Control lines (DSR, DTR, RI, DCD). Resolves Bugzilla #260
    2. Removed Auto-Enabling of Tx/Rx interrupts. Resolves Bugzilla #290
    ADS8343 and ADS8344 Cores Version 1.03
    1. Added FlipBit command. Resolves Bugzilla #288
    I2C Core Version 1.1
    1. Fixed the CTL_IE logic so that it will clear the IRQ when not set. Resolves Bugzilla #304


    April 3, 2006
    MDK Version 1.6.2
    ADS8343 and ADS8344 Cores Version 1.02
    1. Fixed bug in external trigger mode. Resolves Bugzilla #283
    2. Fixed bug with inverted Differential-Mode bit. Resolves Bugzilla #284


    TBD, 2006
    MDK Version 1.6.0
    Top Level Muxing Scheme (wiredOR)
    1. The cores were updated to put out 0's when not selected and the EMIF_iface OR's the data busses together instead of using MUXes. Resolves Bugzilla #178
    I2C Core Version 1.0
    1. New I2C interface for the Real Time Clock Resolves Bugzilla #233
    distRAM Core Version 1.0
    1. A generic distributed RAM core was added for temp PWM count interface Resolves Bugzilla #251
    GPIO Core Version 1.2
    1. Removed the async reset from the core. Resolves Bugzilla #141
    CL_ETH_671X Core Version 1.3
    1. Fixed MII MI register alignment. Added phy 5-bit address for MII MI interface Resolves Bugzilla #192
    Stepper3967 Core Version 1.02.
    1. Fixed problem with odd travel count commands resulting in hard stops instead of smooth decelerations. Resolves Bugzilla #269.
    2. Fixed overshoot register to work properly, needed for locating terminal switches TS3 through TS7. Resolves Bugzilla #250.


    Febraury 24, 2006
    MDK Version 1.5.0
    ADC9235 Core Version 1.2
    1. Fixed empty flag on FIFO status. NOTE: FIFO count is actually 1 plus the number reported in the FSR when the empty flag is 0, 0 when empty flag is set. Resolves Bugzilla #232
    ADS8343 Core Version 1.00
    1. Initial delivery of vhdl core supporting Burr Brown / Texas Instruments ADS8343 16-bit analog-to-digital converter.
    Stepper3967 Core Version 1.01.
    1. Final delivery of Stepper baseline core (tested with software API). NOTE: version 1.00 does not support soft stop conditions properly. With testing, this delivery Resolves Bugzilla #175.
    GPIO Core Version 1.02
    1. Made NUM_IO generic 1 based instead of 0 based. Resolves Bugzilla #177


    January 23, 2006
    Base_Module Version 1.02.
    1. Reduced number of bits in IRQ-Mask registers down to 8 per IRQ line, and compacted them into a single 32-bit register. Resolves Bugzilla #180
    2. Implemented the new Serial-Bank-Addressing scheme for MityDSP-XM. The module defaults to compatibility with the standard MityDSP, and can be built for MityDSP-XM by setting generics on the module. Resolves Bugzilla #191
    Stepper3967 Core Version 1.00.
    1. Initial delivery of vhdl core supporting Allegro 3967 microstepping chip.
    BOOT_FPGA MityDSP_Top Level Version 1.04.
    1. Updated to work with the changes to base_module.vhd outlined above.


    November 17, 2005
    HDK Top Level Version 1.1.TBD
    1. Added PWM Core. Resolves Bugzilla #101
    ADC9235 Core Version 1.1
    1. Added metastable state for Burst Complete clear logic. Resolves Bugzilla #188
    PWM Core Version 1.1
    1. Initial Release. Includes internal bug fix for Bug 179.
    GPIO Core Version 1.1
    1. Reverse logic levels for t_port output signal. Resolves Bugzilla #144


    November 16, 2005
    HDK Top Level Version 1.0.0
    1. Initial release of the HDK, grouped together with MityDSP development kit.
    2. Common top-level vhdl modules needed for skeleton applications are located under hardware/vhdl.
    3. Core modules (including netlists) and necessary build scripts have been placed in the hardware/FPGA/cores path.
    4. Baseline bootloader FPGA image which employs recommended FPGA skeleton architecture (utilizing common vhdl modules for versioning and EMIF interfacing) for MityDSP application FPGA images included under the hardware/FPGA_boot path.
    5. Test modules for various cores are included under the hardware/FPGA_Test path. These modules also illustrate the general build structure recommended for new FPGA applications.
    6. Reference schematics, in Protel 2004 compatible format have been included in the hardware/ReferenceDesigns area. Schematics are also available in PDF for viewing.
    MityUART Core Version 1.3
    1. Added MityDSP Core Version register FIFO, includes capability to read core version number as well as interrupt vector registration from software.
    2. Updated FIFO to support hardware RTS/CTS flow control.
    Ethernet Core Version 1.2
    1. Added MityDSP Core Version register FIFO, includes capability to read core version number as well as interrupt vector registration from software.
    2. Shifted Tc Packet FIFO adddress from 0x00 to 0x18 to support core version address of 0x00.
    3. Added local interrupt enable/disable mask to support sharing IRQ line.
    GPIO Core Version 1.0
    1. Initial release of GPIO core. Compliant with MityDSP hardware development guidelines. See relevant design memos for more information.
    ADC9235 Core Version 1.0
    1. Initial release of ADC9235 core. Compliant with MityDSP hardware development guidelines. See relevant design memos for more information.
    Boot Loader FPGA Image Version 1.3
    1. FPGA image developed / built using MityDSP FPGA design skeleton, common top-level vhdl modules, and latest MityUART Core version (1.3) for dual serial port (USB+RS232). I/O mappings defined for supporting Camera I/O board.
    Reference Designs
    1. Initial Release of the following reference schematics:
      1. RS-232 Serial Interface
      2. 12-Bit SPI ADC Interface
      3. 12-Bit SPI DAC Interface
      4. Ethernet PHY Interface (Broadcom)
      5. CP210X USB Bridge Chip Interface



      
    Copyright © 2005, Critical Link LLC, All rights reserved.