Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

Hi Mads-l,

Can you print out the factory configuration information? Certain modules (Revision "A" silicon, IT silicon and lower speed grade options) do not support frequencies above 300 MHz (rev A silicon, 375 for IT silicon) and they are limited during the kernel boot up. You should be able to see some messages to this affect in the bootlog (dmesg | grep -i speed).

It the factory configuration information is corrupted, the kernel defaults to a "safe" 300 MHz speed limitation.

-Mike

Here is some information - cannot get any useful information from the bootlog.

From Bootloader startup:

Jumping to entry point at 0xC1080000.
U-Boot 2009.11 (Mar 31 2011 - 19:39:18)
I2C: ready
DRAM: 128 MB
NAND: 256 MiB
MMC: davinci: 0
In: serial
Out: serial
Err: serial
ARM Clock : 300000000 Hz
DDR Clock : 150000000 Hz
EMIFA CLock : 100000000 Hz
DSP Clock : 300000000 Hz
ASYNC3 Clock : 150000000 Hz
Enet config : 2
MMC 0 Enable : 1
Resetting ethernet phy
Net: Ethernet PHY: GENERIC @ 0x03 [0x8]
Hit any key to stop autoboot: 0

Bootloader config:

U-Boot > config
MityDSP-L138 Configuration:
Config Version : 1.0
Config Size : 264
Manufacturer : Critical Link
Ethernet Config : 2
Ethernet Name : GENERIC @ 0x03
Ethernet PHYMask: 8
LCD Config : 0
MMC0 Config : 1
MMC1 Config : 0

U-Boot config set:

U-Boot > config set
Ethernet Config : 2
UART - 0 Configuration ---
Enable UART : 0
UART - 1 Configuration ---
Enable UART : 1
Baud : 115200
HW Flow Control : 0
Is Console : 1
UART - 2 Configuration ---
Enable UART : 0
SPI - 0 Configuration ---
Enable SPI : 0
SPI - 1 Configuration ---
Enable SPI : 1
CLK is Output : 1
Chip Select [0] Enable : 01
Chip Select [1] Enable : 00
Chip Select [2] Enable : 00
Chip Select [3] Enable : 00
Chip Select [4] Enable : 00
Chip Select [5] Enable : 00
Chip Select [6] Enable : 00
Chip Select [7] Enable : 00
ENA ENable : 0
CLK Rate : 300000000
LCD Configuration
LCD Enable : 0
MMC 0 Configuration
MMC 0 Enable : 1
Write Protect Pin bank : 4
Write Protect Pin bank offset : 1
Card Detect Pin bank : 4
Card Detect Pin bank offset : 0

From Linux:

root@am180x-evm:/# cat /proc/cpuinfo
Processor : ARM926EJ-S rev 5 (v5l)
BogoMIPS : 148.88
Features : swp half thumb fastmult edsp java
CPU implementer : 0x41
CPU architecture: 5TEJ
CPU variant : 0x0
CPU part : 0x926
CPU revision : 5

Hardware : MityDSP-L138/MityARM-1808
Revision : 0000
Serial : 000000000001adb9

In u-boot, run the command "factoryconfig".

-Mike

This is the "factoryconfig" printout:

U-Boot > factoryconfig
Factory Configuration:
Config Version : 1.1
MAC Address : 00:50:C2:BF:8B:D2
Serial Number : 110009
FPGA Type : 0 [none]
Part Number : 1808-FX-225-RC
U-Boot >

What version of the kernel are you using? The pre-programmed one on FLASH? That version of the kernel may be older than the patch that adds support for upping the speed beyond 300 MHz.

Can you do a "dmesg" and dump the log file?

Sorry for the inconvenience.

-Mike

Hi,

I am usually running the 3.1.x kernel that I build from the git repository downloaded from Critical link. Here are kernel logs for both this kernel and the kernel which resides in SPI-flash from factory.
I notice that the /sys/kernel/debug/davinchi_clocks seems to report the same same. (ref_clk 24 MHz pll0 300 MHz)

mads-l

Can you check if CONFIG_CPU_FREQ=y is set in the 3.1 kernel configuration. Also can you confirm that the CONFIG_CPU_FREQ_GOV_USERSPACE=y?

can you also:

cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies

The sys/kernel/debug/davinci_clocks will only tell you the current settings, not the options...

-Mike

Hi,

Yes - both kernel settings is set to 'y'.

root@vdr:/sys/devices/system/cpu/cpu0/cpufreq# cat scaling_available_frequencies

456000 408000 372000 300000 200000 96000

Mads-l

Oh. You should be all set, see Setting_CPU_Speed.

-Mike

Thanks,

Missed that one - it's working.

Mads-l