Critical Link MityCam SoC Firmware
1.0
Critical Link MityCam SoC Firmware
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#define BACKPRESSURE_ROWS_MASK (0xF << 12) |
#define BACKPRESSURE_ROWS_SHIFT (12) |
#define BOT_OVERFLOW_STICKY_BIT (1 << 30) |
#define BOT_PACKET_SYNC_ERROR_BIT (1 << 31) |
#define BPP_CTRL_MASK (7 << 1) |
#define CTRL_12BPP_10TAP_BIT (2 << 1) |
#define CTRL_12BPP_BASE_BIT (3 << 1) |
#define CTRL_12BPP_MED_BIT (6 << 1) |
#define CTRL_16BPP_10TAP_BIT (0 << 1) |
#define CTRL_16BPP_BASE_BIT (4 << 1) |
#define CTRL_8BPP_10TAP_BIT (1 << 1) |
#define CTRL_8BPP_BASE_BIT (5 << 1) |
#define CTRL_REG_OFFSET 1 |
#define FRAME_OUT_CNT_OFFSET 4 |
#define FV_DELAY_REG_OFFSET 3 |
#define HV_DELAY_REG_MASK (0xFF) |
#define LV_DELAY_REG_MASK (0xFF) |
#define LV_DELAY_REG_OFFSET 2 |
#define MSB_8BPP_SLICE_BIT (1 << 4) |
#define PLL85_LOCKED_BIT (1 << 24) |
#define PLL85A_LOCKED_BIT (1 << 25) |
#define PLL_RESET_BIT (1 << 6) |
#define PSEUDO_SINGLE_PORT (1 << 5) |
#define RESET_BIT (1) |
CTRL Register masks / bits
#define TEST_PATTERN_85MHZ_EN_BIT (1 << 9) |
#define TEST_PATTERN_EN_BIT (1 << 8) |
#define TOP_OVERFLOW_STICKY_BIT (1 << 28) |
#define TOP_PACKET_SYNC_ERROR_BIT (1 << 29) |
#define VERS_REG_OFFSET 0 |
Register offsets