Critical Link MityCam SoC Firmware  1.0
Critical Link MityCam SoC Firmware
GenICamSharedRegs.h
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1 // These are the shared GenICam registers; the definitions are #included in the
2 
3 // IMPORTANT: Registers must be in monotonically increasing address order.
4 
5 REGDEF_STR (DEVICE_FIRMWARE_VERSION, RO, 64, "1.0"),
6 REGDEF_INT (DEVICE_RESET, WO, 0),
7 
8 REGDEF_I64 (DEVICE_FPGA_VERSION , RO, 0),
9 REGDEF_STR (DEVICE_SOFTWARE_DATE , RO, 64, ""),
10 REGDEF_STR (DEVICE_FX3_DATE , RO, 64, ""),
11 
12 REGDEF_INT (AQUISITION_FRAMERATE , RW, 66666),
13 REGDEF_INT (EXPOSURE_TIME , RW, 20000),
14 REGDEF_INT (EXPOSURE_TIME_SELECT , RW, 0),
15 REGDEF_INT (ROI_WIDTH , RW, SocCamera::tcRegisterFile::cnMAX_IMAGE_WIDTH),
16 REGDEF_INT (ROI_HEIGHT , RW, SocCamera::tcRegisterFile::cnMAX_IMAGE_HEIGHT),
17 REGDEF_INT (ROI_OFFSET_X , RW, 0),
18 REGDEF_INT (ROI_OFFSET_Y , RW, 0),
19 REGDEF_INT (ACQUISITION_START , WO, 0),
20 REGDEF_INT (ACQUISITION_MODE , RW, ACQUISITION_MODE_CONTINUOUS),
21 
22 REGDEF_INT (PIXEL_FORMAT , RW, PIXEL_FORMAT_MONO16),
23 REGDEF_INT (PAYLOAD_SIZE , RO, SocCamera::tcRegisterFile::cnMAX_PAYLOAD_SIZE),
24 REGDEF_INT (BINNING_HORIZONTAL , RW, 1),
25 REGDEF_INT (BINNING_VERTICAL , RW, 1),
26 REGDEF_INT (REVERSE_X , RW, 0),
27 REGDEF_INT (REVERSE_Y , RW, 1),
28 REGDEF_INT (ACQUISITION_NUM_FRAMES, RW, 16),
29 REGDEF_INT (ACQUISITION_STOP , WO, 0),
30 REGDEF_INT (DECIMATION_VERTICAL , RW, 1),
31 REGDEF_FLT (SENSOR_TEMPERATURE , RO, 0.0),
32 REGDEF_FLT (BOARD_TEMPERATURE , RO, 0.0),
33 REGDEF_INT (EDGE_DETECTION , RW, 0),
34 REGDEF_INT (SHUTTER_MODE , RW, SHUTTERMODE_ROLLING),
35 REGDEF_INT (SENSOR_GAINMODE , RW, 0),
36 REGDEF_INT (SENSOR_CALIBRATE , RW, 1),
37 REGDEF_INT (TEST_PATTERN , RW, 0),
38 REGDEF_INT (CLOCK_SPEED , RW, 0),
39 
40 REGDEF_INT (SQRT_COMPRESS , RW, 0),
41 
42 REGDEF_INT (HOT_PIXEL_CORRECT , RW, 50),
43 REGDEF_INT (BAD_PIXEL_CTRL , RW, 1),
44 REGDEF_INT (BAD_PIXEL_CTRL_MAP , RW, 0),
45 
46 REGDEF_INT (VOLTAGE_SENSOR_SELECT , RW, 0),
47 REGDEF_FLT (VOLTAGE_SENSOR_VALUE , RO, 0.0f),
48 REGDEF_INT (DEVICE_TEMPERATURE_SELECT , RW, 1),
49 REGDEF_FLT (DEVICE_TEMPERATURE , RO, 0.0f),
50 
51 REGDEF_INT (SENSOR_WIDTH, RO, 0),
52 REGDEF_INT (SENSOR_HEIGHT, RO, 0),
53 
54 REGDEF_INT (FREE_RAM_CFG , RO, 0),
55 
56 REGDEF_INT (INTERNAL_EXP_MODE, RW, 1),
57 
58 REGDEF_INT (LUT_SELECTOR, RW, 0),
59 REGDEF_INT (LUT_ENABLE, RW, 0),
60 REGDEF_INT (LUT_MAXINDEX, RO, 255),
61 REGDEF_INT (LUT_INDEX, RW, 0),
62 REGDEF_INT (LUT_MAXVALUE, RO, 255),
63 REGDEF_INT (LUT_VALUE, RW, 0),
64 // REGDEF_INT (LUT_VALUEALL, RW, 0),
65 
66 REGDEF_INT (GAIN_SELECTOR, RW, 0),
67 REGDEF_FLT (GAIN, RW, 0),
68 REGDEF_INT (GAIN_AUTO, RW, 0),
69 REGDEF_INT (GAIN_AUTOBALANCE, RW, 0),
70 REGDEF_INT (BLACK_LEVEL_SELECTOR, RW, 0),
71 REGDEF_FLT (BLACK_LEVEL, RW, 0),
72 REGDEF_INT (BLACK_LEVEL_AUTO, RW, 0),
73 REGDEF_INT (BLACK_LEVEL_AUTOBALANCE, RW, 0),
74 REGDEF_INT (WHITE_CLIP_SELECTOR, RW, 0),
75 REGDEF_FLT (WHITE_CLIP, RW, 0),
76 REGDEF_INT (BALANCE_RATIO_SELECTOR, RW, 0),
77 REGDEF_FLT (BALANCE_RATIO, RW, 0),
78 REGDEF_INT (BALANCE_WHITE_AUTO, RW, 0),
79 REGDEF_FLT (GAMMA, RW, 0),
80 REGDEF_FLT (BLACK_LEVEL_BIAS, RW, 0),
81 
82 REGDEF_INT (COLOR_TRANSF_SELECTOR, RW, 0),
83 REGDEF_INT (COLOR_TRANSF_ENABLE, RW, 0),
84 REGDEF_INT (COLOR_TRANSF_VALUE_SELECTOR, RW, 0),
85 REGDEF_FLT (COLOR_TRANSF_VALUE, RW, 0),
86 
87 REGDEF_INT (TRIGGER_SELECTOR, RW, 3),
88 REGDEF_INT (TRIGGER_MODE, RW, 0),
89 REGDEF_INT (TRIGGER_SOURCE, RW, 0),
90 REGDEF_INT (TRIGGER_ACTIVATION, RW, 0),
91 
92 REGDEF_INT (DIGITAL_IO_LINE_SELECT, RW, 0),
93 REGDEF_INT (DIGITAL_IO_LINE_MODE, RW, 0),
94 REGDEF_INT (DIGITAL_IO_LINE_SOURCE, RW, 0),
95 REGDEF_INT (USER_OUTPUT_SELECTOR, RW, 0),
96 REGDEF_INT (USER_OUTPUT_VALUE, RW, 0),
97 REGDEF_INT (DIGITAL_IO_LINE_STATUS, RW, 0),
98 REGDEF_INT (DIGITAL_IO_LINE_INVERTER, RW, 0),
99 
100 REGDEF_INT (INDICATOR_CONTROL, RW, 1),
101 REGDEF_INT (FAN_CONTROL, RW, 1),
102 
103 REGDEF_INT (IS_CAMERA_COLOR, RW, 1),
104 
105 REGDEF_INT(SENS_REG_ADDR, RW, 0),
106 REGDEF_INT(SENS_VAL, RW, 0),
107 REGDEF_INT(SENS_READ, WO, 0),
108 REGDEF_INT(SENS_WRITE, WO, 0),
109 
110 REGDEF_INT(SENS_MIN_FRAME_PERIOD, RO, 1000),
111 
112 REGDEF_INT(SENS_SPECIFIC_1, RW, 0),
113 REGDEF_INT(SENS_SPECIFIC_2, RW, 0),
114 REGDEF_INT(SENS_SPECIFIC_3, RW, 0),
115 REGDEF_INT(SENS_SPECIFIC_4, RW, 0),
116 REGDEF_INT(SENS_SPECIFIC_5, RW, 0),
117 REGDEF_INT(SENS_SPECIFIC_6, RW, 0),
118 REGDEF_INT(SENS_SPECIFIC_7, RW, 0),
119 REGDEF_INT(SENS_SPECIFIC_8, RW, 0),
120 REGDEF_INT(SENS_SPECIFIC_9, RW, 0),
121 REGDEF_STR(SENS_SPECIFIC_10,RW, 64, ""),
122 REGDEF_FLT(SENS_SPECIFIC_11, RW, 0.0),
123 REGDEF_FLT(SENS_SPECIFIC_12, RW, 0.0),
124 REGDEF_INT(SENS_SPECIFIC_13, RW, 0),
125 REGDEF_INT(SENS_SPECIFIC_14, RW, 0),
126 REGDEF_INT(SENS_SPECIFIC_15, RW, 0),
127 REGDEF_INT(SENS_SPECIFIC_16, RW, 0),
128 REGDEF_INT(SENS_SPECIFIC_16, RW, 0),
129 REGDEF_INT(SENS_SPECIFIC_17, RW, 0),
130 REGDEF_INT(SENS_SPECIFIC_18, RW, 0),
131 REGDEF_INT(SENS_SPECIFIC_19, RW, 0),
132 REGDEF_INT(SENS_SPECIFIC_20, RW, 0),
133 REGDEF_INT(SENS_SPECIFIC_21, RW, 0),
134 REGDEF_INT(SENS_SPECIFIC_22, RW, 0),
135 REGDEF_INT(SENS_SPECIFIC_23, RW, 0),
136 REGDEF_INT(SENS_SPECIFIC_24, RW, 0),
137 REGDEF_INT(SENS_SPECIFIC_25, RW, 0),
138 REGDEF_INT(SENS_SPECIFIC_26, RW, 0),
139 REGDEF_INT(SENS_SPECIFIC_26, RW, 0),
140 REGDEF_INT(SENS_SPECIFIC_27, RW, 0),
141 REGDEF_INT(SENS_SPECIFIC_28, RW, 0),
142 REGDEF_INT(SENS_SPECIFIC_29, RW, 0),
143 REGDEF_INT(SENS_SPECIFIC_30, RW, 0),
144 
145 REGDEF_FLT(SENS_SPECIFIC_FLOAT_1, RW, 0.0),
146 REGDEF_FLT(SENS_SPECIFIC_FLOAT_2, RW, 0.0),
147 REGDEF_FLT(SENS_SPECIFIC_FLOAT_3, RW, 0.0),
148 REGDEF_FLT(SENS_SPECIFIC_FLOAT_4, RW, 0.0),
149 REGDEF_FLT(SENS_SPECIFIC_FLOAT_5, RW, 0.0),
150 
151 REGDEF_BUF(SENS_PEEKPOKE , RW, (SENS_PEEKPOKE_ADDR_END-SENS_PEEKPOKE_ADDR+1)),
152 
153 REGDEF_STR (XML_FILE , RO, XML_FILE_SIZE_B, std::string()),
154 
155 REGDEF_I64(MANIFEST_TABLE_COUNT,RO, 1), // 1 entry in the manifest table.
156 REGDEF_INT(MANIFEST_VER, RO, 0x02010000), // subminor = 0, min=1, maj=2
157 REGDEF_INT(MANIFEST_TYPE, RO, 0x01010000), // reserved = 0, type = 1, shema minor = 1, schema major = 1
158 REGDEF_I64(MANIFEST_REG, RO, XML_FILE_ADDR),
159 REGDEF_I64(MANIFEST_FILE_SIZE, RO, 0),
160 REGDEF_STR(MANIFEST_SHA1, RO, 20, ""),
SocCamera::tcRegisterFile::cnMAX_IMAGE_WIDTH
static const uint32_t cnMAX_IMAGE_WIDTH
These may be dependant on the sensor type, but for now just want a handy place to put them.
Definition: RegisterFile.h:129
REGDEF_BUF
REGDEF_BUF(SENS_PEEKPOKE, RW,(SENS_PEEKPOKE_ADDR_END-SENS_PEEKPOKE_ADDR+1))
SENS_PEEKPOKE_ADDR_END
const uint32_t SENS_PEEKPOKE_ADDR_END
Definition: RegisterFile.h:870
SocCamera::tcRegisterFile::cnMAX_IMAGE_HEIGHT
static const uint32_t cnMAX_IMAGE_HEIGHT
Definition: RegisterFile.h:130
REGDEF_INT
REGDEF_INT(DEVICE_RESET, WO, 0)
PIXEL_FORMAT_MONO16
const uint32_t PIXEL_FORMAT_MONO16
Flags for PIXEL_FORMAT register.
Definition: RegisterFile.h:931
SENS_PEEKPOKE_ADDR
const uint32_t SENS_PEEKPOKE_ADDR
Definition: RegisterFile.h:869
XML_FILE_SIZE_B
const uint32_t XML_FILE_SIZE_B
Size allocated for XML file in register space.
Definition: RegisterFile.h:71
REGDEF_FLT
REGDEF_FLT(SENSOR_TEMPERATURE, RO, 0.0)
REGDEF_I64
REGDEF_I64(DEVICE_FPGA_VERSION, RO, 0)
SocCamera::tcRegisterFile::cnMAX_PAYLOAD_SIZE
static const uint32_t cnMAX_PAYLOAD_SIZE
Definition: RegisterFile.h:131
ACQUISITION_MODE_CONTINUOUS
#define ACQUISITION_MODE_CONTINUOUS
Definition: GigE.h:245
XML_FILE_ADDR
const uint32_t XML_FILE_ADDR
This is where the XML file is loaded into memory.
Definition: RegisterFile.h:875
REGDEF_STR
REGDEF_STR(DEVICE_FIRMWARE_VERSION, RO, 64, "1.0")
SHUTTERMODE_ROLLING
const uint32_t SHUTTERMODE_ROLLING
Flags for SHUTTER_MODE register.
Definition: RegisterFile.h:1070