#include <map>
#include <iostream>
#include <climits>
#include <stdint.h>
#include <sys/types.h>
#include <sys/socket.h>
#include <netinet/in.h>
#include <netdb.h>
#include "CommandInterface/RegisterFileObserver.h"
#include "Utility/Observable.h"
#include "GigE.h"
#include "PayloadSetter.h"
#include "Sensors/SensorBoard.h"

Include dependency graph for RegisterFile.h:

This graph shows which files directly or indirectly include this file:

Classes
class	SocCamera::tcRegisterFile

union	SocCamera::tcRegisterFile::tuDataType

struct	SocCamera::tcRegisterFile::tsRegDefinition

class	SocCamera::tcRegUpdateMsg

class	SocCamera::tcRegUpdateTypeMsg< T >

Namespaces
	SocCamera

	LUTSelector

	AnalogControl

	ColorTransf

	TriggerSelector

	TriggerActivation

	LineSource

Macros
#define	REG_ACCESS_NA 0,0

#define	REG_ACCESS_WO 0,1

#define	REG_ACCESS_RO 1,0

#define	REG_ACCESS_RW 1,1

#define	REGDEF_I64(name, access, dflt) { name ## _ADDR, #name, sizeof(uint64_t), SocCamera::eeRegUint64, REG_ACCESS_ ## access, { .dfltlval = dflt }, std::string() }

#define	REGDEF_INT(name, access, dflt) { name ## _ADDR, #name, sizeof(uint32_t), SocCamera::eeRegUint32, REG_ACCESS_ ## access, { .dfltnval = dflt }, std::string() }

#define	REGDEF_FLT(name, access, dflt) { name ## _ADDR, #name, sizeof(float), SocCamera::eeRegFloat, REG_ACCESS_ ## access, { .dfltfval = dflt }, std::string() }

#define	REGDEF_STR(name, access, size, dflt) { name ## _ADDR, #name, size, SocCamera::eeRegString, REG_ACCESS_ ## access, { .dfltnval = 0 }, dflt }

#define	REGDEF_BUF(name, access, size) { name ## _ADDR, #name, size, SocCamera::eeRegNoType, REG_ACCESS_ ## access, { .dfltrptr = nullptr }, std::string() }

#define	REGDEF_END_OF_TABLE { 0xFFFFFFFF,NULL,0,SocCamera::eeRegUint32,0,0,{ .dfltnval = 0 },std::string() }

#define	GENCP_USER_DEFINED_NAME (1 << 0)

#define	GENCP_ACCESS_PRIVILEGE (1 << 1)

#define	GENCP_MESSAGE_CHANNEL (1 << 2)

#define	GENCP_TIMESTAMP (1 << 3)

#define	GENCP_STRING_ENCODING_ASCII (0 << 4)

#define	GENCP_STRING_ENCODING_UTF8 (1 << 4)

#define	GENCP_STRING_ENCODING_UTF16 (2 << 4)

#define	GENCP_FAMILY_NAME (1 << 8)

#define	GENCP_SBRM_SUPPORT (1 << 9)

#define	GENCP_ENDIANESS_REGISTER (1 << 10)

#define	GENCP_WRITTEN_LENGTH_FIELD (1 << 11)

#define	GENCP_MULTIEVENT (1 << 12)

#define	GENCP_CONFIG_HEARTBEAT_ENABLE (1 << 0)

#define	GENCP_CONFIG_MULTIEVENT_ENABLE (1 << 1)

#define	SBRM_TABLE_ADDR (0x10000)

#define	U3V_SIRM_AVAILABLE (1 << 0)

#define	U3V_EIRM_AVAILABLE (1 << 1)

#define	U3V_IIDC2_AVAILABLE (1 << 2)

#define	U3V_CMD_EP_BUFF_SIZE (1020) /* Smaller buffer so that the FX3 doesn't get into an error state with something too large for it */

#define	U3V_MAX_HEADER (52) /* Maximum number of bytes in USB3V packet header */

#define	U3V_MAX_FOOTER (32) /* Maximum number of bytes in USB3V packet footer */

#define	GENCP_LITTLE_ENDIAN (0xFFFFFFFF)

#define	XML_REGS_OFFSET (0x30000)

#define	PFNC_CUSTOM 0x80000000

#define	PFNC_SINGLE_COMPONENT 0x01000000

#define	PFNC_MULTIPLE_COMPONENT 0x02000000

#define	PFNC_COMPONENT_MASK 0x7F000000

#define	PFNC_OCCUPY1BIT 0x00010000

#define	PFNC_OCCUPY2BIT 0x00020000

#define	PFNC_OCCUPY4BIT 0x00040000

#define	PFNC_OCCUPY8BIT 0x00080000

#define	PFNC_OCCUPY10BIT 0x000A0000

#define	PFNC_OCCUPY12BIT 0x000C0000

#define	PFNC_OCCUPY16BIT 0x00100000

#define	PFNC_OCCUPY24BIT 0x00180000

#define	PFNC_OCCUPY30BIT 0x001E0000

#define	PFNC_OCCUPY32BIT 0x00200000

#define	PFNC_OCCUPY36BIT 0x00240000

#define	PFNC_OCCUPY40BIT 0x00280000

#define	PFNC_OCCUPY48BIT 0x00300000

#define	PFNC_OCCUPY64BIT 0x00400000

#define	PFNC_PIXEL_SIZE_MASK 0x00FF0000

#define	PFNC_PIXEL_SIZE_SHIFT 16

#define	PFNC_PIXEL_ID_MASK 0x0000FFFF

#define	PFNC_PIXEL_SIZE(X) ((X & PFNC_PIXEL_SIZE_MASK) >> PFNC_PIXEL_SIZE_SHIFT)

#define	PFNC_IS_PIXEL_SINGLE_COMPONENT(X) ((X & PFNC_COMPONENT_MASK) == PFNC_SINGLE_COMPONENT)

#define	PFNC_IS_PIXEL_MULTIPLE_COMPONENT(X) ((X & PFNC_COMPONENT_MASK) == PFNC_MULTIPLE_COMPONENT)

#define	PFNC_IS_PIXEL_CUSTOM(X) ((X & PFNC_CUSTOM) == PFNC_CUSTOM)

#define	PFNC_PIXEL_ID(X) (X & PFNC_PIXEL_ID_MASK)

Typedefs
typedef tcRegUpdateTypeMsg< uint64_t >	SocCamera::tcRegUpdateUint64Msg

typedef tcRegUpdateTypeMsg< uint32_t >	SocCamera::tcRegUpdateUint32Msg

typedef tcRegUpdateTypeMsg< float >	SocCamera::tcRegUpdateFloatMsg

typedef tcRegUpdateTypeMsg< std::string >	SocCamera::tcRegUpdateStringMsg

typedef tcRegUpdateTypeMsg< void * >	SocCamera::tcRegUpdateBufferMsg

Enumerations
enum	SocCamera::teRegType { SocCamera::eeRegNoType, SocCamera::eeRegUint32, SocCamera::eeRegFloat, SocCamera::eeRegUint64, SocCamera::eeRegString }
	Specifies what kind of data a register holds. More...

enum	LUTSelector::eeLUTSelected { LUTSelector::eeLuminance = 0, LUTSelector::eeRed = 1, LUTSelector::eeGreen = 2, LUTSelector::eeBlue = 3, LUTSelector::eeDeviceSpecific = 10 }

enum	AnalogControl::eeAnalogSelected { AnalogControl::eeAll = 0, AnalogControl::eeRed = 1, AnalogControl::eeGreen = 2, AnalogControl::eeBlue = 3, AnalogControl::eeY = 4, AnalogControl::eeU = 5, AnalogControl::eeV = 6, AnalogControl::eeAnalogAll = 10, AnalogControl::eeAnalogRed = 11, AnalogControl::eeAnalogGreen = 12, AnalogControl::eeAnalogBlue = 13, AnalogControl::eeAnalogY = 14, AnalogControl::eeAnalogU = 15, AnalogControl::eeAnalogV = 16, AnalogControl::eeDigitalAll = 20, AnalogControl::eeDigitalRed = 21, AnalogControl::eeDigitalGreen = 22, AnalogControl::eeDigitalBlue = 23, AnalogControl::eeDigitalY = 24, AnalogControl::eeDigitalU = 25, AnalogControl::eeDigitalV = 26 }

enum	AnalogControl::eeAnalogAuto { AnalogControl::eeOff = 0, AnalogControl::eeOnce = 1, AnalogControl::eeContinuous = 2, AnalogControl::eeDeviceSpecific = 10 }

enum	ColorTransf::eeColorTransfSelected { ColorTransf::eeRGBtoRGB = 0, ColorTransf::eeRGBtoYUV = 1, ColorTransf::eeDeviceSpecific = 10 }

enum	ColorTransf::eeColorTransfValueSelected { ColorTransf::eeGain00 = 0, ColorTransf::eeGain01 = 1, ColorTransf::eeGain02 = 2, ColorTransf::eeGain10 = 3, ColorTransf::eeGain11 = 4, ColorTransf::eeGain12 = 5, ColorTransf::eeGain20 = 6, ColorTransf::eeGain21 = 7, ColorTransf::eeGain22 = 8, ColorTransf::eeOffset0 = 9, ColorTransf::eeOffset1 = 10, ColorTransf::eeOffset2 = 11 }

enum	TriggerSelector::eeTriggerSelected { TriggerSelector::eeAcquisitionStart = 0, TriggerSelector::eeAcquisitionEnd = 1, TriggerSelector::eeAcquisitionActive = 2, TriggerSelector::eeFrameStart = 3, TriggerSelector::eeFrameEnd = 4, TriggerSelector::eeFrameActive = 5, TriggerSelector::eeFrameBurstStart = 6, TriggerSelector::eeFrameBurstEnd = 7, TriggerSelector::eeFrameBurstActive = 8, TriggerSelector::eeLineStart = 9, TriggerSelector::eeExposureStart = 10, TriggerSelector::eeExposureEnd = 11, TriggerSelector::eeExposureActive = 12 }

enum	TriggerActivation::teTriggerActivation { TriggerActivation::eeRisingEdge = 0, TriggerActivation::eeFallingEdge = 1, TriggerActivation::eeAnyEdge = 2, TriggerActivation::eeLevelHigh = 3, TriggerActivation::eeLevelLow = 4 }

enum	LineSource::teLineSource { LineSource::eeOff = 0, LineSource::eeZero = 1, LineSource::eeOne = 2, LineSource::eeExposureActive = 5, LineSource::eeUserOutput0 = 22, LineSource::eeUserOutput1 = 23, LineSource::eeFabricInput1 = 32, LineSource::eeFabricInput2 = 33, LineSource::eeFabricInput3 = 34, LineSource::eeFabricInput4 = 35 }

Variables
const uint32_t	MANUFACTURER_REGISTER_SIZE_B = 0xA000
	Size of manufacturer register space. More...

const uint32_t	BOOTSTRAP_REGISTER_SIZE_B = 0xA000
	Size of bootstrap register space. More...

const uint32_t	XML_FILE_SIZE_B = 0xA000
	Size allocated for XML file in register space. More...

const uint32_t	TOTAL_REGISTER_SIZE_B = MANUFACTURER_REGISTER_SIZE_B + BOOTSTRAP_REGISTER_SIZE_B + XML_FILE_SIZE_B

const uint32_t	VERSION_ADDR = 0x0000'0000
	This register indicates the version of the GigE Vision specification implemented by this device. Version 1.0 of this specification shall return 0x00010000. More...

const uint32_t	DEVICE_MODE_ADDR = 0x0000'0004
	This register indicates the character set used by the various strings present in the bootstrap registers and other device-specific information, such as the endianness of multi-byte data. More...

const uint32_t	DEVICE_MAC_HIGH0_ADDR = 0x0000'0008
	This register stores the MAC address (upper 16-bit) of the given network interface. More...

const uint32_t	DEVICE_MAC_LOW0_ADDR = 0x0000'000C
	This register stores the MAC address (lower 32-bit) of the given network interface. More...

const uint32_t	NET_IFACE_CAPABILITY0_ADDR = 0x0000'0010
	This register indicates the IP configuration scheme supported on the given network interface. Multiple schemes can be supported simultaneously. More...

const uint32_t	NET_IFACE_CONFIG0_ADDR = 0x0000'0014
	This register indicates which IP configurations schemes are currently activated on the given network interface. More...

const uint32_t	CURRENT_IP_ADDR0_ADDR = 0x0000'0024
	This register reports the IP address for the given network interface once it has been configured. More...

const uint32_t	CURRENT_SUBNET0_ADDR = 0x0000'0034
	This register provides the subnet mask of the given interface. More...

const uint32_t	CURRENT_GATEWAY0_ADDR = 0x0000'0044
	This register indicates the default gateway IP address to be used on the given network interface. More...

const uint32_t	MANUFACTURER_NAME_ADDR = 0x0000'0048
	This registers stores a string containing the manufacturer name. This string uses the character set indicated in the "string character set" register. More...

const uint32_t	MODEL_NAME_ADDR = 0x0000'0068
	This registers stores a string containing the device model name. This string uses the character set indicated in the "string character set" register. More...

const uint32_t	DEVICE_VERSION_ADDR = 0x0000'0088
	This register stores a string containing the version of the device. This string uses the character set indicated in the "string character set" register. The XML device description file should also provide this information to ensure the device matches the description file. More...

const uint32_t	MANUFACTURER_INFO_ADDR = 0x0000'00A8
	This register stores a string containing additional manufacturer-specific information about the device. This string uses the character set indicated in the "string character set" register. More...

const uint32_t	SERIAL_NUMBER_ADDR = 0x0000'00D8
	String providing the serial number of this device. More...

const uint32_t	USER_NAME_ADDR = 0x0000'00E8
	String providing the device name. More...

const uint32_t	FIRST_URL_ADDR = 0x0000'0200
	This register stores the first URL to the XML device description file. This URL must be used as the first choice by the application. This string uses the character set indicated in the "string character set" register. More...

const uint32_t	SECOND_URL_ADDR = 0x0000'0400
	This register stores the second URsi_meL to the XML device description file. This URL is an alternative if the application was unsuccessful to retrieve the device description file using the first URL. This string uses the character set indicated in the "string character set" register. More...

const uint32_t	NB_INTERFACES_ADDR = 0x0000'0600
	This register indicates the number of physical network interfaces supported by this device. A device must support at least one network interfaces (the primary interface). In this specification, a device can support at most four network interfaces. More...

const uint32_t	PERSISTENT_IP_ADDR0_ADDR = 0x0000'064C
	This register indicates the Persistent IP address for this network interface. It is only used when the device boots with the Persistent IP configuration scheme. More...

const uint32_t	PERSISTENT_SUBNET0_ADDR = 0x0000'065C
	This register indicates the Persistent subnet mask associated with the Persistent IP address on this network interface. It is only used when the device boots with the Persistent IP configuration scheme. More...

const uint32_t	PERSISTENT_GATEWAY0_ADDR = 0x0000'066C
	This register indicates the persistent default gateway for this network interface. It is only used when the device boots with the Persistent IP configuration scheme. More...

const uint32_t	NB_MSG_CHANNELS_ADDR = 0x0000'0900
	This register reports the number of message channel supported by this device. In the current version of this specification, a maximum of 1 message channel can be supported. More...

const uint32_t	NB_STREAM_CHANNELS_ADDR = 0x0000'0904
	This register reports the number of stream channels supported by this device. A device must support at least one stream channel. A device can support up to 512 stream channels. More...

const uint32_t	NB_ACTIVE_LINKS_ADDR = 0x0000'0910
	This register reports the number of physical links that are currently active. More...

const uint32_t	GVSP_CAPABILITY_ADDR = 0x0000'092C
	Bit 1 indicates SCSP availability, bit 2 indicates legacy 16 bit block ID support available. 2-31 reserved. More...

const uint32_t	MSG_CAPABILITY_ADDR = 0x0000'0930
	Indicates the MCSP capability. Bit 0 is MCSP_Supported. More...

const uint32_t	GVCP_CAPABILITY_ADDR = 0x0000'0934
	This register reports the optional GVCP command supported by this device. More...

const uint32_t	HEARTBEAT_TIMEOUT_ADDR = 0x0000'0938
	This registers indicates the current heartbeat timeout in milliseconds. More...

const uint32_t	TIMESTAMP_FREQ_HIGH_ADDR = 0x0000'093C
	This register indicates the number of timestamp tick during 1 second. This corresponds to the timestamp frequency in Hertz. Upper 32-bit. More...

const uint32_t	TIMESTAMP_FREQ_LOW_ADDR = 0x0000'0940
	This register indicates the number of timestamp tick during 1 second. This corresponds to the timestamp frequency in Hertz. Lower 32-bit. More...

const uint32_t	TIMESTAMP_CTRL_ADDR = 0x0000'0944
	This register is used to control the timestamp counter. More...

const uint32_t	TIMESTAMP_VALUE_HIGH_ADDR = 0x0000'0948
	This register reports the latched value of the timestamp counter. It is necessary to latch the 64-bit timestamp value to guaranty its integrity when performing the two 32-bit read accesses to retrieve the higher and lower 32-bit portions. Upper 32-bit. More...

const uint32_t	TIMESTAMP_VALUE_LOW_ADDR = 0x0000'094C
	This register reports the latched value of the timestamp counter. It is necessary to latch the 64-bit timestamp value to guaranty its integrity when performing the two 32-bit read accesses to retrieve the higher and lower 32-bit portions. Lower 32-bit. More...

const uint32_t	GVCP_CONFIGURATION_ADDR = 0x0000'0954

const uint32_t	PENDING_TIMEOUT_ADDR = 0x0000'0958
	Pending Timeout to report the longest GVCP command execution time before issuing a PENDING_ACK. If PENDING_ACK is not supported, then this is the worst-case execution time before command completion. More...

const uint32_t	CTRL_SWITCHOVER_KEY_ADDR = 0x0000'095C
	Key to authenticate primary application switchover requests. More...

const uint32_t	GVSP_CONFIGURATION_ADDR = 0x0000'0960
	This register enables the 64-bit block_id64 for GVSP. More...

const uint32_t	PHY_CAPABILITY_ADDR = 0x0000'0964
	Indicates the physical link configuration supported by this device. More...

const uint32_t	PHY_CONFIG_ADDR = 0x0000'0968
	Indicates the currently active physical link configuration. More...

const uint32_t	IEEE_1588_STATUS_ADDR = 0x0000'096C
	Reports the state of the IEEE 1588 clock. More...

const uint32_t	SCHEDULED_ACTION_Q_SIZE_ADDR = 0x0000'0970
	Indicates the number of Scheduled Action Commands that can be queued (size of the queue). More...

const uint32_t	CCP_ADDR = 0x0000'0A00
	This register is used to grant privilege to an application. More...

const uint32_t	PA_PORT_ADDR = 0x0000'0A04
	UDP source port of the control channel of the primary application. More...

const uint32_t	PA_IP_ADDR = 0x0000'0A14
	Source IP address of the control channel of the primary application. More...

const uint32_t	MCP_ADDR = 0x0000'0B00
	This register provides port information about the message channel. The message channel is activated when the host_port field is different from 0. Otherwise, the channel is closed. More...

const uint32_t	MCDA_ADDR = 0x0000'0B10
	This register indicates the destination IP address for the message channel. More...

const uint32_t	MCTT_ADDR = 0x0000'0B14
	This register provides the transmission timeout value in milliseconds. This indicates the amount of time to wait for acknowledge after a message is sent on the message channel before timeout. More...

const uint32_t	MCRC_ADDR = 0x0000'0B18
	This register indicates the number of retransmissions allowed when a message channel message times out. If MCRC is set to 0, then no retransmission is allowed. More...

const uint32_t	MCSP_ADDR = 0x0000'0B1C
	Message Channel Source Port. More...

const uint32_t	SCP0_ADDR = 0x0000'0D00
	This register provides port information for this stream channel. The stream channel is activated when the host_port field is different from 0. Otherwise, the channel is closed. More...

const uint32_t	SCPS0_ADDR = 0x0000'0D04
	This register indicates the packet size in bytes for this stream channel. This is the total packet size, including all headers (Ethernet, IP, UDP and GVSP). It also provides a way to set the IP header "do not fragment" bit and to send stream test packet to the application. More...

const uint32_t	SCPD0_ADDR = 0x0000'0D08
	This register indicates the delay (in timestamp counter unit) to insert between each packet for this stream channel. This can be used as a crude flow-control mechanism if the application cannot keep up with the packets coming from the device. More...

const uint32_t	SCDA0_ADDR = 0x0000'0D18
	This register indicates the destination IP address for this stream channel. More...

const uint32_t	SCSP0_ADDR = 0x0000'0D1C
	This register indicates the source port of the GVSP stream. More...

const uint32_t	SCC0_ADDR = 0x0000'0D20
	First Stream Channel Capability register. More...

const uint32_t	SCCFG0_ADDR = 0x0000'0D24
	First Stream Channel Configuration register. More...

const uint32_t	MANIFEST_TABLE_ADDR = 0x1000'0000

const uint32_t	ABRM_GENCP_VERSION_ADDR = 0x00000

const uint32_t	ABRM_MANUFACTURER_NAME_ADDR = 0x00004

const uint32_t	ABRM_MODEL_NAME_ADDR = 0x00044

const uint32_t	ABRM_FAMILY_NAME_ADDR = 0x00084

const uint32_t	ABRM_DEVICE_VERSION_ADDR = 0x000C4

const uint32_t	ABRM_MANUFACTURER_INFO_ADDR = 0x00104

const uint32_t	ABRM_SERIAL_NUMBER_ADDR = 0x00144

const uint32_t	ABRM_USER_DEFINED_NAME_ADDR = 0x00184

const uint32_t	ABRM_DEVICE_CAPABILITY_ADDR = 0x001C4

const uint32_t	ABRM_MAX_DEVICE_RESPONSE_TIME_ADDR = 0x001CC

const uint32_t	ABRM_MANIFEST_TABLE_ADDRESS_ADDR = 0x001D0

const uint32_t	ABRM_SBRM_ADDRESS_ADDR = 0x001D8

const uint32_t	ABRM_DEVICE_CONFIGURATION_ADDR = 0x001E0

const uint32_t	ABRM_HEARTBEAT_TIMEOUT_ADDR = 0x001E8

const uint32_t	ABRM_MESSAGE_CHANNEL_ID_ADDR = 0x001EC

const uint32_t	ABRM_TIMESTAMP_ADDR = 0x001F0

const uint32_t	ABRM_TIMESTAMP_LATCH_ADDR = 0x001F8

const uint32_t	ABRM_TIMESTAMP_INCREMENT_ADDR = 0x001FC

const uint32_t	ABRM_ACCESS_PRIVILEGE_ADDR = 0x00204

const uint32_t	ABRM_PROTOCOL_ENDIANESS_ADDR = 0x00208

const uint32_t	ABRM_IMPLEMENTATION_ENDIANESS_ADDR = 0x0020C

const uint32_t	ABRM_RESERVED_ADDR = 0x00210

const uint64_t	U3V_DEVICE_CAPABILITY = GENCP_ENDIANESS_REGISTER \| GENCP_USER_DEFINED_NAME \| GENCP_FAMILY_NAME \| GENCP_TIMESTAMP \| GENCP_STRING_ENCODING_ASCII \| GENCP_SBRM_SUPPORT \| GENCP_WRITTEN_LENGTH_FIELD

const uint64_t	U3V_DEVICE_CONFIGURATION = 0

const uint32_t	U3V_VERSION_ADDR = SBRM_TABLE_ADDR

const uint32_t	U3V_CP_CABABILITY_ADDR = SBRM_TABLE_ADDR + 0x04

const uint32_t	U3V_CP_CONFIGURATION_ADDR = SBRM_TABLE_ADDR + 0x0C

const uint32_t	U3V_MAX_COMMAND_TRANS_ADDR = SBRM_TABLE_ADDR + 0x14

const uint32_t	U3V_MAX_ACK_TRANS_ADDR = SBRM_TABLE_ADDR + 0x18

const uint32_t	U3V_NB_STRTEAM_ADDR = SBRM_TABLE_ADDR + 0x1C

const uint32_t	U3V_SIRM_ADDRESS_ADDR = SBRM_TABLE_ADDR + 0x20

const uint32_t	U3V_SIRM_LENGTH_ADDR = SBRM_TABLE_ADDR + 0x28

const uint32_t	U3V_EIRM_ADDRESS_ADDR = SBRM_TABLE_ADDR + 0x2C

const uint32_t	U3V_EIRM_LENGTH_ADDR = SBRM_TABLE_ADDR + 0x34

const uint32_t	U3V_IIDC2_ADDRESS_ADDR = SBRM_TABLE_ADDR + 0x38

const uint32_t	U3V_CURRENT_SPEED_ADDR = SBRM_TABLE_ADDR + 0x40

const uint32_t	U3V_VERSION = 0x00010001

const uint64_t	U3V_CP_CAPABILITY = U3V_SIRM_AVAILABLE

const uint64_t	U3V_CP_CONFIGURATION = 0

const uint32_t	U3V_MAX_CMD_LEN = U3V_CMD_EP_BUFF_SIZE

const uint32_t	U3V_MAX_ACK_LEN = U3V_CMD_EP_BUFF_SIZE

const uint32_t	U3V_NB_STREAMS = 1

const uint32_t	U3V_SIRM_LENGTH = 0x30

const uint32_t	U3V_SIRM_TABLE_ADDR = 0x20000

const uint32_t	U3V_SIRM_INFO_ADDR = U3V_SIRM_TABLE_ADDR

const uint32_t	U3V_SIRM_CTRL_ADDR = U3V_SIRM_TABLE_ADDR + 0x04

const uint32_t	U3V_REQ_PAYLOAD_SIZE_ADDR = U3V_SIRM_TABLE_ADDR + 0x08

const uint32_t	U3V_REQ_LEADER_SIZE_ADDR = U3V_SIRM_TABLE_ADDR + 0x10

const uint32_t	U3V_REQ_TRAILER_SIZE_ADDR = U3V_SIRM_TABLE_ADDR + 0x14

const uint32_t	U3V_MAX_LEADER_ADDR = U3V_SIRM_TABLE_ADDR + 0x18

const uint32_t	U3V_PAYLOAD_SIZE_ADDR = U3V_SIRM_TABLE_ADDR + 0x1C

const uint32_t	U3V_PAYLOAD_COUNT_ADDR = U3V_SIRM_TABLE_ADDR + 0x20

const uint32_t	U3V_PAYLOAD_FINAL1_ADDR = U3V_SIRM_TABLE_ADDR + 0x24

const uint32_t	U3V_PAYLOAD_FINAL2_ADDR = U3V_SIRM_TABLE_ADDR + 0x28

const uint32_t	U3V_MAX_TRAILER_SIZE_ADDR = U3V_SIRM_TABLE_ADDR + 0x2C

const uint32_t	DEVICE_FIRMWARE_VERSION_ADDR = XML_REGS_OFFSET + 0x0000'2000

const uint32_t	DEVICE_RESET_ADDR = XML_REGS_OFFSET + 0x0000'2100

const uint32_t	DEVICE_FPGA_VERSION_ADDR = XML_REGS_OFFSET + 0x0000'3000

const uint32_t	DEVICE_SOFTWARE_DATE_ADDR = XML_REGS_OFFSET + 0x0000'3008

const uint32_t	DEVICE_FX3_DATE_ADDR = XML_REGS_OFFSET + 0x0000'3048

const uint32_t	AQUISITION_FRAMERATE_ADDR = XML_REGS_OFFSET + 0x0000'A000
	This register controls the acquisition rate. This is actually the frame interval in usecs. More...

const uint32_t	EXPOSURE_TIME_ADDR = XML_REGS_OFFSET + 0x0000'A004
	SFNC 5.7.4 ExposureTime - This register sets the Exposure time (uS). More...

const uint32_t	ROI_WIDTH_ADDR = XML_REGS_OFFSET + 0x0000'A008
	SFNC 4.18 Width - This register sets the width of the ROI. More...

const uint32_t	ROI_HEIGHT_ADDR = XML_REGS_OFFSET + 0x0000'A00C
	SFNC 4.19 Height - This register sets the height of the ROI. More...

const uint32_t	ROI_OFFSET_X_ADDR = XML_REGS_OFFSET + 0x0000'A010
	SFNC 4.20 OffsetX - This register stores the starting column of the ROI. More...

const uint32_t	ROI_OFFSET_Y_ADDR = XML_REGS_OFFSET + 0x0000'A014
	SFNC 4.21 OffsetY - This register stores the starting row of the ROI. More...

const uint32_t	ACQUISITION_START_ADDR = XML_REGS_OFFSET + 0x0000'A018
	SFNC 5.5.3 AcquisitionStart - Start/stop image acquisition using the specified acquision mode in the Acquisition Mode register. More...

const uint32_t	ACQUISITION_MODE_ADDR = XML_REGS_OFFSET + 0x0000'A01C
	SFNC 5.5.2 AcquisitionMode - Controls acquisition mode. More...

const uint32_t	PIXEL_FORMAT_ADDR = XML_REGS_OFFSET + 0x0000'A020
	SFNC 4.35 PixelFormat - Contains the pixel format. More...

const uint32_t	PAYLOAD_SIZE_ADDR = XML_REGS_OFFSET + 0x0000'A024
	SFNC 25.2.5 PayloadSize - Size of frame without headers. More...

const uint32_t	BINNING_HORIZONTAL_ADDR = XML_REGS_OFFSET + 0x0000'A028
	SFNC 4.26 BinningHorizontal - Number of pixels to bin in the horizontal direction. More...

const uint32_t	BINNING_VERTICAL_ADDR = XML_REGS_OFFSET + 0x0000'A02C
	SFNC 4.28 BinningVertical - Number of pixels to bin in the vertical direction. More...

const uint32_t	REVERSE_X_ADDR = XML_REGS_OFFSET + 0x0000'A030
	SFNC 4.33 ReverseX - "Bool" that flips X when true. More...

const uint32_t	REVERSE_Y_ADDR = XML_REGS_OFFSET + 0x0000'A034
	SFNC 4.34 ReverseY - "Bool" that flips Y when true. More...

const uint32_t	ACQUISITION_NUM_FRAMES_ADDR = XML_REGS_OFFSET + 0x0000'A038
	SFNC 5.5.4 AquisitionFrameCount - Number of frames to be captured in MultiFrame mode. More...

const uint32_t	ACQUISITION_STOP_ADDR = XML_REGS_OFFSET + 0x0000'A03C
	SFNC 5.5.4 AquisitionStop - Start/stop image acquisition using the specified acquision mode in the Acquisition Mode register. More...

const uint32_t	DECIMATION_VERTICAL_ADDR = XML_REGS_OFFSET + 0x0000'A040
	SFNC 4.32 DecimationVertical - Number of rows to skip in the vertical direction. More...

const uint32_t	SENSOR_TEMPERATURE_ADDR = XML_REGS_OFFSET + 0x0000'A044

const uint32_t	BOARD_TEMPERATURE_ADDR = XML_REGS_OFFSET + 0x0000'A048

const uint32_t	EDGE_DETECTION_ADDR = XML_REGS_OFFSET + 0x0000'A04C

const uint32_t	SHUTTER_MODE_ADDR = XML_REGS_OFFSET + 0x0000'A050

const uint32_t	SENSOR_GAINMODE_ADDR = XML_REGS_OFFSET + 0x0000'A054

const uint32_t	SENSOR_CALIBRATE_ADDR = XML_REGS_OFFSET + 0x0000'A058

const uint32_t	TEST_PATTERN_ADDR = XML_REGS_OFFSET + 0x0000'A05C

const uint32_t	CLOCK_SPEED_ADDR = XML_REGS_OFFSET + 0x0000'A060

const uint32_t	SQRT_COMPRESS_ADDR = XML_REGS_OFFSET + 0x0000'A064

const uint32_t	HOT_PIXEL_CORRECT_ADDR = XML_REGS_OFFSET + 0x0000'A068

const uint32_t	BAD_PIXEL_CTRL_ADDR = XML_REGS_OFFSET + 0x0000'A070

const uint32_t	BAD_PIXEL_CTRL_MAP_ADDR = XML_REGS_OFFSET + 0x0000'A074
	Set whether to display bad pixel map (as 1s/0s) for debugging. More...

const uint32_t	VOLTAGE_SENSOR_SELECT_ADDR = XML_REGS_OFFSET + 0x0000'A078
	Selects which ADC / voltage sensor to read back. More...

const uint32_t	VOLTAGE_SENSOR_VALUE_ADDR = XML_REGS_OFFSET + 0x0000'A07C
	retrieves selected ADC voltage sensor value More...

const uint32_t	DEVICE_TEMPERATURE_SELECT_ADDR = XML_REGS_OFFSET + 0x0000'A080
	SFNC 3.60 DeviceTemperatureSelector. More...

const uint32_t	DEVICE_TEMPERATURE_ADDR = XML_REGS_OFFSET + 0x0000'A084
	SFNC 3.61 DeviceTemperature. More...

const uint32_t	EXPOSURE_TIME_SELECT_ADDR = XML_REGS_OFFSET + 0x0000'A08C
	SFNC 5.7.3 ExposureTimeSelector - This optional register allows selecting different exposure times (see SFNC). More...

const uint32_t	SENSOR_WIDTH_ADDR = XML_REGS_OFFSET + 0x0000'A090
	SFNC 4.2 SensorWidth - Effective width of sensor in pixels. More...

const uint32_t	SENSOR_HEIGHT_ADDR = XML_REGS_OFFSET + 0x0000'A094
	SFNC 4.3 SensorHeight - Effective height of sensor in pixels. More...

const uint32_t	FREE_RAM_CFG_ADDR = XML_REGS_OFFSET + 0x0000'A100

const uint32_t	INTERNAL_EXP_MODE_ADDR = XML_REGS_OFFSET + 0x0000'A200

const uint32_t	LUT_SELECTOR_ADDR = XML_REGS_OFFSET + 0x0000'A300

const uint32_t	LUT_ENABLE_ADDR = XML_REGS_OFFSET + 0x0000'A304

const uint32_t	LUT_MAXINDEX_ADDR = XML_REGS_OFFSET + 0x0000'A308

const uint32_t	LUT_INDEX_ADDR = XML_REGS_OFFSET + 0x0000'A30C

const uint32_t	LUT_MAXVALUE_ADDR = XML_REGS_OFFSET + 0x0000'A310

const uint32_t	LUT_VALUE_ADDR = XML_REGS_OFFSET + 0x0000'A314

const uint32_t	GAIN_SELECTOR_ADDR = XML_REGS_OFFSET + 0x0000'A400

const uint32_t	GAIN_ADDR = XML_REGS_OFFSET + 0x0000'A404

const uint32_t	GAIN_AUTO_ADDR = XML_REGS_OFFSET + 0x0000'A408

const uint32_t	GAIN_AUTOBALANCE_ADDR = XML_REGS_OFFSET + 0x0000'A40C

const uint32_t	BLACK_LEVEL_SELECTOR_ADDR = XML_REGS_OFFSET + 0x0000'A410

const uint32_t	BLACK_LEVEL_ADDR = XML_REGS_OFFSET + 0x0000'A414

const uint32_t	BLACK_LEVEL_AUTO_ADDR = XML_REGS_OFFSET + 0x0000'A418

const uint32_t	BLACK_LEVEL_AUTOBALANCE_ADDR = XML_REGS_OFFSET + 0x0000'A41C

const uint32_t	WHITE_CLIP_SELECTOR_ADDR = XML_REGS_OFFSET + 0x0000'A420

const uint32_t	WHITE_CLIP_ADDR = XML_REGS_OFFSET + 0x0000'A424

const uint32_t	BALANCE_RATIO_SELECTOR_ADDR = XML_REGS_OFFSET + 0x0000'A428

const uint32_t	BALANCE_RATIO_ADDR = XML_REGS_OFFSET + 0x0000'A42C

const uint32_t	BALANCE_WHITE_AUTO_ADDR = XML_REGS_OFFSET + 0x0000'A430

const uint32_t	GAMMA_ADDR = XML_REGS_OFFSET + 0x0000'A434

const uint32_t	BLACK_LEVEL_BIAS_ADDR = XML_REGS_OFFSET + 0x0000'A440

const uint32_t	COLOR_TRANSF_SELECTOR_ADDR = XML_REGS_OFFSET + 0x0000'A500

const uint32_t	COLOR_TRANSF_ENABLE_ADDR = XML_REGS_OFFSET + 0x0000'A504

const uint32_t	COLOR_TRANSF_VALUE_SELECTOR_ADDR = XML_REGS_OFFSET + 0x0000'A508

const uint32_t	COLOR_TRANSF_VALUE_ADDR = XML_REGS_OFFSET + 0x0000'A50C

const uint32_t	TRIGGER_SELECTOR_ADDR = XML_REGS_OFFSET + 0x0000'B000

const uint32_t	TRIGGER_MODE_ADDR = XML_REGS_OFFSET + 0x0000'B004

const uint32_t	TRIGGER_SOURCE_ADDR = XML_REGS_OFFSET + 0x0000'B008

const uint32_t	TRIGGER_ACTIVATION_ADDR = XML_REGS_OFFSET + 0x0000'B00C

const uint32_t	DIGITAL_IO_LINE_SELECT_ADDR = XML_REGS_OFFSET + 0x0000'B100

const uint32_t	DIGITAL_IO_LINE_MODE_ADDR = XML_REGS_OFFSET + 0x0000'B104

const uint32_t	DIGITAL_IO_LINE_SOURCE_ADDR = XML_REGS_OFFSET + 0x0000'B10C

const uint32_t	USER_OUTPUT_SELECTOR_ADDR = XML_REGS_OFFSET + 0x0000'B110

const uint32_t	USER_OUTPUT_VALUE_ADDR = XML_REGS_OFFSET + 0x0000'B114

const uint32_t	DIGITAL_IO_LINE_STATUS_ADDR = XML_REGS_OFFSET + 0x0000'B118

const uint32_t	DIGITAL_IO_LINE_INVERTER_ADDR = XML_REGS_OFFSET + 0x0000'B11C

const uint32_t	INDICATOR_CONTROL_ADDR = XML_REGS_OFFSET + 0x0000'B120
	control indicators / LEDS on camera More...

const uint32_t	FAN_CONTROL_ADDR = XML_REGS_OFFSET + 0x0000'B124
	control for FAN More...

const uint32_t	IS_CAMERA_COLOR_ADDR = XML_REGS_OFFSET + 0x0000'B200
	True if this is a color capable camera. More...

const uint32_t	SENS_REG_ADDR_ADDR = XML_REGS_OFFSET + 0x0000'C000

const uint32_t	SENS_VAL_ADDR = XML_REGS_OFFSET + 0x0000'C004

const uint32_t	SENS_READ_ADDR = XML_REGS_OFFSET + 0x0000'C008

const uint32_t	SENS_WRITE_ADDR = XML_REGS_OFFSET + 0x0000'C00C

const uint32_t	SENS_MIN_FRAME_PERIOD_ADDR = XML_REGS_OFFSET + 0x0000'C020

const uint32_t	SENS_SPECIFIC_1_ADDR = XML_REGS_OFFSET + 0x0000'D000

const uint32_t	SENS_SPECIFIC_2_ADDR = XML_REGS_OFFSET + 0x0000'D004

const uint32_t	SENS_SPECIFIC_3_ADDR = XML_REGS_OFFSET + 0x0000'D008

const uint32_t	SENS_SPECIFIC_4_ADDR = XML_REGS_OFFSET + 0x0000'D00C

const uint32_t	SENS_SPECIFIC_5_ADDR = XML_REGS_OFFSET + 0x0000'D010

const uint32_t	SENS_SPECIFIC_6_ADDR = XML_REGS_OFFSET + 0x0000'D014

const uint32_t	SENS_SPECIFIC_7_ADDR = XML_REGS_OFFSET + 0x0000'D018

const uint32_t	SENS_SPECIFIC_8_ADDR = XML_REGS_OFFSET + 0x0000'D01C

const uint32_t	SENS_SPECIFIC_9_ADDR = XML_REGS_OFFSET + 0x0000'D020

const uint32_t	SENS_SPECIFIC_10_ADDR = XML_REGS_OFFSET + 0x0000'D024

const uint32_t	SENS_SPECIFIC_11_ADDR = XML_REGS_OFFSET + 0x0000'D064

const uint32_t	SENS_SPECIFIC_12_ADDR = XML_REGS_OFFSET + 0x0000'D068

const uint32_t	SENS_SPECIFIC_13_ADDR = XML_REGS_OFFSET + 0x0000'D06C

const uint32_t	SENS_SPECIFIC_14_ADDR = XML_REGS_OFFSET + 0x0000'D070

const uint32_t	SENS_SPECIFIC_15_ADDR = XML_REGS_OFFSET + 0x0000'D074

const uint32_t	SENS_SPECIFIC_16_ADDR = XML_REGS_OFFSET + 0x0000'D078

const uint32_t	SENS_SPECIFIC_17_ADDR = XML_REGS_OFFSET + 0x0000'D07C

const uint32_t	SENS_SPECIFIC_18_ADDR = XML_REGS_OFFSET + 0x0000'D080

const uint32_t	SENS_SPECIFIC_19_ADDR = XML_REGS_OFFSET + 0x0000'D084

const uint32_t	SENS_SPECIFIC_20_ADDR = XML_REGS_OFFSET + 0x0000'D088

const uint32_t	SENS_SPECIFIC_21_ADDR = XML_REGS_OFFSET + 0x0000'D08C

const uint32_t	SENS_SPECIFIC_22_ADDR = XML_REGS_OFFSET + 0x0000'D090

const uint32_t	SENS_SPECIFIC_23_ADDR = XML_REGS_OFFSET + 0x0000'D094

const uint32_t	SENS_SPECIFIC_24_ADDR = XML_REGS_OFFSET + 0x0000'D098

const uint32_t	SENS_SPECIFIC_25_ADDR = XML_REGS_OFFSET + 0x0000'D09C

const uint32_t	SENS_SPECIFIC_26_ADDR = XML_REGS_OFFSET + 0x0000'D0A0

const uint32_t	SENS_SPECIFIC_27_ADDR = XML_REGS_OFFSET + 0x0000'D0A4

const uint32_t	SENS_SPECIFIC_28_ADDR = XML_REGS_OFFSET + 0x0000'D0A8

const uint32_t	SENS_SPECIFIC_29_ADDR = XML_REGS_OFFSET + 0x0000'D0AC

const uint32_t	SENS_SPECIFIC_30_ADDR = XML_REGS_OFFSET + 0x0000'D0B0

const uint32_t	SENS_SPECIFIC_FLOAT_1_ADDR = XML_REGS_OFFSET + 0x0000'D100

const uint32_t	SENS_SPECIFIC_FLOAT_2_ADDR = XML_REGS_OFFSET + 0x0000'D104

const uint32_t	SENS_SPECIFIC_FLOAT_3_ADDR = XML_REGS_OFFSET + 0x0000'D108

const uint32_t	SENS_SPECIFIC_FLOAT_4_ADDR = XML_REGS_OFFSET + 0x0000'D10c

const uint32_t	SENS_SPECIFIC_FLOAT_5_ADDR = XML_REGS_OFFSET + 0x0000'D110

const uint32_t	SENS_PEEKPOKE_ADDR = XML_REGS_OFFSET + 0x0020'0000

const uint32_t	SENS_PEEKPOKE_ADDR_END = XML_REGS_OFFSET + 0x0023'FFFF

const uint32_t	XML_FILE_ADDR = XML_REGS_OFFSET + 0x0001'4000
	This is where the XML file is loaded into memory. More...

const uint32_t	DEBUG_BUFFER_BYTESWRITTEN_ADDR = 0x0030'0000

const uint32_t	DEBUG_BUFFER_ADDR = 0x0030'1000

const uint32_t	MANIFEST_TABLE_COUNT_ADDR = MANIFEST_TABLE_ADDR

const uint32_t	MANIFEST_VER_ADDR = MANIFEST_TABLE_ADDR + 0x08

const uint32_t	MANIFEST_TYPE_ADDR = MANIFEST_VER_ADDR + 0x04

const uint32_t	MANIFEST_REG_ADDR = MANIFEST_TYPE_ADDR + 0x04

const uint32_t	MANIFEST_FILE_SIZE_ADDR = MANIFEST_REG_ADDR + 0x08

const uint32_t	MANIFEST_SHA1_ADDR = MANIFEST_FILE_SIZE_ADDR + 0x08

const uint32_t	BEYOND_MANIFEST_ADDR = 0x20000000

const uint32_t	TEST_PENDING_ACK_ADDR = BEYOND_MANIFEST_ADDR

const uint32_t	HDMI_START_ADDR = BEYOND_MANIFEST_ADDR + 0x04

const uint32_t	HDMI_STOP_ADDR = BEYOND_MANIFEST_ADDR + 0x08

const uint32_t	HDMI_OFFSET_X_ADDR = BEYOND_MANIFEST_ADDR + 0x0c

const uint32_t	HDMI_OFFSET_Y_ADDR = BEYOND_MANIFEST_ADDR + 0x10

const uint32_t	HDMI_WIDTH_ADDR = BEYOND_MANIFEST_ADDR + 0x14

const uint32_t	HDMI_HEIGHT_ADDR = BEYOND_MANIFEST_ADDR + 0x18

const uint32_t	HDMI_OUTPUT_SEL_ADDR = BEYOND_MANIFEST_ADDR + 0x1c

const uint32_t	HDMI_GAMMA_ADDR = BEYOND_MANIFEST_ADDR + 0x24

const uint32_t	HDMI_WBRED_ADDR = BEYOND_MANIFEST_ADDR + 0x28

const uint32_t	HDMI_WBGREEN_ADDR = BEYOND_MANIFEST_ADDR + 0x2C

const uint32_t	HDMI_WBBLUE_ADDR = BEYOND_MANIFEST_ADDR + 0x30

const uint32_t	HDMI_TESTPATEN_ADDR = BEYOND_MANIFEST_ADDR + 0x34

const uint32_t	HDMI_BPP_ADDR = BEYOND_MANIFEST_ADDR + 0x38

const uint32_t	GIGE_VERSION_1_2 = 0x00010002
	Flags for VERSION register. More...

const uint32_t	GIGE_VERSION_2_0 = 0x00020000

const uint32_t	PIXEL_FORMAT_MONO16 = 0x01100007
	Flags for PIXEL_FORMAT register. More...

const uint32_t	PIXEL_FORMAT_MONO8 = 0x01080001

const uint32_t	PIXEL_FORMAT_MONO12 = 0x01100005

const uint32_t	PIXEL_FORMAT_MONO12P = 0x010C0047

const uint32_t	PIXEL_FORMAT_MONO12PACKED = 0x010C0007

const uint32_t	PIXEL_FORMAT_BAYERGR8 = 0x01080008

const uint32_t	PIXEL_FORMAT_BAYERRG8 = 0x01080009

const uint32_t	PIXEL_FORMAT_BAYERGB8 = 0x0108000A

const uint32_t	PIXEL_FORMAT_BAYERBG8 = 0x0108000B

const uint32_t	PIXEL_FORMAT_BAYERGR16 = 0x0110002E

const uint32_t	PIXEL_FORMAT_BAYERRG16 = 0x0110002F

const uint32_t	PIXEL_FORMAT_BAYERGB16 = 0x01100030

const uint32_t	PIXEL_FORMAT_BAYERBG16 = 0x01100031

const uint32_t	PIXEL_FORMAT_BAYERBG12P = 0x010C0053

const uint32_t	PIXEL_FORMAT_BAYERGB12P = 0x010C0055

const uint32_t	PIXEL_FORMAT_BAYERGR12P = 0x010C0057

const uint32_t	PIXEL_FORMAT_BAYERRG12P = 0x010C0059

const uint32_t	PIXEL_FORMAT_BAYERGR12PACKED = 0x010C002A

const uint32_t	PIXEL_FORMAT_BAYERRG12PACKED = 0x010C002B

const uint32_t	PIXEL_FORMAT_BAYERGB12PACKED = 0x010C002C

const uint32_t	PIXEL_FORMAT_BAYERBG12PACKED = 0x010C002D

const uint32_t	PRIVILEGE_EXCLUSIVE = 0x00000001
	Flags for CCP register. More...

const uint32_t	PRIVILEGE_CONTROL = 0x00000002
	Control privilege (read-write) More...

const uint32_t	GVCP_CAP_UN = 0x80000000
	Flags for GVCP_CAPABILITY register. More...

const uint32_t	GVCP_CAP_SN = 0x40000000

const uint32_t	GVCP_CAP_HD = 0x20000000

const uint32_t	GVCP_CAP_LS = 0x10000000

const uint32_t	GVCP_CAP_CAP = 0x08000000

const uint32_t	GVCP_CAP_MT = 0x04000000

const uint32_t	GVCP_CAP_TD = 0x02000000

const uint32_t	GVCP_CAP_DD = 0x01000000

const uint32_t	GVCP_CAP_WD = 0x00800000

const uint32_t	GVCP_CAP_ES = 0x00400000

const uint32_t	GVCP_CAP_PAS = 0x00200000

const uint32_t	GVCP_CAP_UA = 0x00100000

const uint32_t	GVCP_CAP_PTP = 0x00080000

const uint32_t	GVCP_CAP_ES2 = 0x00040000

const uint32_t	GVCP_CAP_SAC = 0x00020000

const uint32_t	GVCP_CAP_A = 0x00000040

const uint32_t	GVCP_CAP_PA = 0x00000020

const uint32_t	GVCP_CAP_ED = 0x00000010

const uint32_t	GVCP_CAP_E = 0x00000008

const uint32_t	GVCP_CAP_PR = 0x00000004

const uint32_t	GVCP_CAP_W = 0x00000002

const uint32_t	GVCP_CAP_C = 0x00000001

const uint32_t	GVCP_CAP_VALUE = GVCP_CAP_UN \| GVCP_CAP_SN \| GVCP_CAP_CAP \| GVCP_CAP_W \| GVCP_CAP_PR

const uint32_t	GVsP_CAP_SP = 0x80000000
	Flags for GVSP_CAPABILITY & GVSP_CONFIGURATION register. More...

const uint32_t	GVsP_CAP_LB = 0x40000000

const uint32_t	GVsP_CAP_VALUE = GVsP_CAP_SP \| GVsP_CAP_LB

const uint32_t	GVsP_CFG_BL = 0x40000000
	Flags for GVSP_CONFIGURATION register. More...

const uint32_t	PHY_CAP_DLAG = 0x00000008
	Flags for PHY_CAPABILITY register. More...

const uint32_t	PHY_CAP_SLAG = 0x00000004
	This device supports static link aggregation configuration. More...

const uint32_t	PHY_CAP_ML = 0x00000002
	This device supports multiple link (ML) configuration. More...

const uint32_t	PHY_CAP_SL = 0x00000001
	This device supports single link (SL) configuration. More...

const uint32_t	PHY_CONFIG_DLAG = 3
	Flags for PHY_CONFIG register. More...

const uint32_t	PHY_CONFIG_SLAG = 2
	Static link aggregation configuration. More...

const uint32_t	PHY_CONFIG_ML = 1
	Multiple link (ML) configuration. More...

const uint32_t	PHY_CONFIG_SL = 0
	Single link (SL) configuration. More...

const uint32_t	DEVMODE_BIGENDIAN = 0x80000000
	Flags for DEVICE_MODE register. More...

const uint32_t	DEVMODE_ASCII = 0x00000002

const uint32_t	DEVMODE_UTF8 = 0x00000001

const uint32_t	SHUTTERMODE_ROLLING = 0x00000000
	Flags for SHUTTER_MODE register. More...

const uint32_t	SHUTTERMODE_GLOBAL = 0x00000001

const uint32_t	NET_IFACE_C_PR = 0x80000000
	Flags for NET_IFACE_CAPABILITY0 & NET_IFACE_CONFIG0 Register. More...

const uint32_t	NET_IFACE_C_PG = 0x40000000

const uint32_t	NET_IFACE_C_L = 0x00000004

const uint32_t	NET_IFACE_C_D = 0x00000002

const uint32_t	NET_IFACE_C_P = 0x00000001

const uint32_t	NET_IFACE_C_MASK = NET_IFACE_C_L\|NET_IFACE_C_D\|NET_IFACE_C_P

const uint32_t	SCPS_F = 0x80000000
	Flags for SCPS0 Register. More...

const uint32_t	SCPS_D = 0x40000000

const uint32_t	SCPS_P = 0x20000000

const uint32_t	SCPS_PKT_SIZE_MASK = 0x0000FFFF

const uint32_t	SCPS_MASK = SCPS_F\|SCPS_D\|SCPS_PKT_SIZE_MASK

const uint32_t	SC_CAP_BE = 0x80000000
	Flags for SCC0 Register. More...

const uint32_t	SC_CAP_R = 0x40000000

const uint32_t	SC_CAP_MZ = 0x00000010

const uint32_t	SC_CAP_PRD = 0x00000008

const uint32_t	SC_CAP_AIT = 0x00000004

const uint32_t	SC_CAP_US = 0x00000002

const uint32_t	SC_CAP_EC = 0x00000001

const uint32_t	SC_CAP_VALUE = 0

const uint32_t	TIMESTAMP_CTRL_L = 0x00000002
	Flags for TIMESTAMP_CTRL Register. More...

const uint32_t	TIMESTAMP_CTRL_R = 0x00000001

Macro Definition Documentation

◆ GENCP_ACCESS_PRIVILEGE

#define GENCP_ACCESS_PRIVILEGE (1 << 1)

◆ GENCP_CONFIG_HEARTBEAT_ENABLE

#define GENCP_CONFIG_HEARTBEAT_ENABLE (1 << 0)

◆ GENCP_CONFIG_MULTIEVENT_ENABLE

#define GENCP_CONFIG_MULTIEVENT_ENABLE (1 << 1)

◆ GENCP_ENDIANESS_REGISTER

#define GENCP_ENDIANESS_REGISTER (1 << 10)

◆ GENCP_FAMILY_NAME

#define GENCP_FAMILY_NAME (1 << 8)

◆ GENCP_LITTLE_ENDIAN

#define GENCP_LITTLE_ENDIAN (0xFFFFFFFF)

◆ GENCP_MESSAGE_CHANNEL

#define GENCP_MESSAGE_CHANNEL (1 << 2)

◆ GENCP_MULTIEVENT

#define GENCP_MULTIEVENT (1 << 12)

◆ GENCP_SBRM_SUPPORT

#define GENCP_SBRM_SUPPORT (1 << 9)

◆ GENCP_STRING_ENCODING_ASCII

#define GENCP_STRING_ENCODING_ASCII (0 << 4)

◆ GENCP_STRING_ENCODING_UTF16

#define GENCP_STRING_ENCODING_UTF16 (2 << 4)

◆ GENCP_STRING_ENCODING_UTF8

#define GENCP_STRING_ENCODING_UTF8 (1 << 4)

◆ GENCP_TIMESTAMP

#define GENCP_TIMESTAMP (1 << 3)

◆ GENCP_USER_DEFINED_NAME

#define GENCP_USER_DEFINED_NAME (1 << 0)

◆ GENCP_WRITTEN_LENGTH_FIELD

#define GENCP_WRITTEN_LENGTH_FIELD (1 << 11)

◆ PFNC_COMPONENT_MASK

#define PFNC_COMPONENT_MASK 0x7F000000

◆ PFNC_CUSTOM

#define PFNC_CUSTOM 0x80000000

◆ PFNC_IS_PIXEL_CUSTOM

#define PFNC_IS_PIXEL_CUSTOM ( X ) ((X & PFNC_CUSTOM) == PFNC_CUSTOM)

◆ PFNC_IS_PIXEL_MULTIPLE_COMPONENT

#define PFNC_IS_PIXEL_MULTIPLE_COMPONENT ( X ) ((X & PFNC_COMPONENT_MASK) == PFNC_MULTIPLE_COMPONENT)

◆ PFNC_IS_PIXEL_SINGLE_COMPONENT

#define PFNC_IS_PIXEL_SINGLE_COMPONENT ( X ) ((X & PFNC_COMPONENT_MASK) == PFNC_SINGLE_COMPONENT)

◆ PFNC_MULTIPLE_COMPONENT

#define PFNC_MULTIPLE_COMPONENT 0x02000000

◆ PFNC_OCCUPY10BIT

#define PFNC_OCCUPY10BIT 0x000A0000

◆ PFNC_OCCUPY12BIT

#define PFNC_OCCUPY12BIT 0x000C0000

◆ PFNC_OCCUPY16BIT

#define PFNC_OCCUPY16BIT 0x00100000

◆ PFNC_OCCUPY1BIT

#define PFNC_OCCUPY1BIT 0x00010000

◆ PFNC_OCCUPY24BIT

#define PFNC_OCCUPY24BIT 0x00180000

◆ PFNC_OCCUPY2BIT

#define PFNC_OCCUPY2BIT 0x00020000

◆ PFNC_OCCUPY30BIT

#define PFNC_OCCUPY30BIT 0x001E0000

◆ PFNC_OCCUPY32BIT

#define PFNC_OCCUPY32BIT 0x00200000

◆ PFNC_OCCUPY36BIT

#define PFNC_OCCUPY36BIT 0x00240000

◆ PFNC_OCCUPY40BIT

#define PFNC_OCCUPY40BIT 0x00280000

◆ PFNC_OCCUPY48BIT

#define PFNC_OCCUPY48BIT 0x00300000

◆ PFNC_OCCUPY4BIT

#define PFNC_OCCUPY4BIT 0x00040000

◆ PFNC_OCCUPY64BIT

#define PFNC_OCCUPY64BIT 0x00400000

◆ PFNC_OCCUPY8BIT

#define PFNC_OCCUPY8BIT 0x00080000

◆ PFNC_PIXEL_ID

#define PFNC_PIXEL_ID ( X ) (X & PFNC_PIXEL_ID_MASK)

◆ PFNC_PIXEL_ID_MASK

#define PFNC_PIXEL_ID_MASK 0x0000FFFF

◆ PFNC_PIXEL_SIZE

#define PFNC_PIXEL_SIZE ( X ) ((X & PFNC_PIXEL_SIZE_MASK) >> PFNC_PIXEL_SIZE_SHIFT)

◆ PFNC_PIXEL_SIZE_MASK

#define PFNC_PIXEL_SIZE_MASK 0x00FF0000

◆ PFNC_PIXEL_SIZE_SHIFT

#define PFNC_PIXEL_SIZE_SHIFT 16

◆ PFNC_SINGLE_COMPONENT

#define PFNC_SINGLE_COMPONENT 0x01000000

◆ REG_ACCESS_NA

#define REG_ACCESS_NA 0,0

◆ REG_ACCESS_RO

#define REG_ACCESS_RO 1,0

◆ REG_ACCESS_RW

#define REG_ACCESS_RW 1,1

◆ REG_ACCESS_WO

#define REG_ACCESS_WO 0,1

◆ REGDEF_BUF

#define REGDEF_BUF	(	name,
		access,
		size
	)	{ name ## _ADDR, #name, size, SocCamera::eeRegNoType, REG_ACCESS_ ## access, { .dfltrptr = nullptr }, std::string() }

◆ REGDEF_END_OF_TABLE

#define REGDEF_END_OF_TABLE { 0xFFFFFFFF,NULL,0,SocCamera::eeRegUint32,0,0,{ .dfltnval = 0 },std::string() }

◆ REGDEF_FLT

#define REGDEF_FLT	(	name,
		access,
		dflt
	)	{ name ## _ADDR, #name, sizeof(float), SocCamera::eeRegFloat, REG_ACCESS_ ## access, { .dfltfval = dflt }, std::string() }

◆ REGDEF_I64

#define REGDEF_I64	(	name,
		access,
		dflt
	)	{ name ## _ADDR, #name, sizeof(uint64_t), SocCamera::eeRegUint64, REG_ACCESS_ ## access, { .dfltlval = dflt }, std::string() }

◆ REGDEF_INT

#define REGDEF_INT	(	name,
		access,
		dflt
	)	{ name ## _ADDR, #name, sizeof(uint32_t), SocCamera::eeRegUint32, REG_ACCESS_ ## access, { .dfltnval = dflt }, std::string() }

◆ REGDEF_STR

#define REGDEF_STR	(	name,
		access,
		size,
		dflt
	)	{ name ## _ADDR, #name, size, SocCamera::eeRegString, REG_ACCESS_ ## access, { .dfltnval = 0 }, dflt }

◆ SBRM_TABLE_ADDR

#define SBRM_TABLE_ADDR (0x10000)

◆ U3V_CMD_EP_BUFF_SIZE

#define U3V_CMD_EP_BUFF_SIZE (1020) /* Smaller buffer so that the FX3 doesn't get into an error state with something too large for it */

◆ U3V_EIRM_AVAILABLE

#define U3V_EIRM_AVAILABLE (1 << 1)

◆ U3V_IIDC2_AVAILABLE

#define U3V_IIDC2_AVAILABLE (1 << 2)

◆ U3V_MAX_FOOTER

#define U3V_MAX_FOOTER (32) /* Maximum number of bytes in USB3V packet footer */

◆ U3V_MAX_HEADER

#define U3V_MAX_HEADER (52) /* Maximum number of bytes in USB3V packet header */

◆ U3V_SIRM_AVAILABLE

#define U3V_SIRM_AVAILABLE (1 << 0)

◆ XML_REGS_OFFSET

#define XML_REGS_OFFSET (0x30000)

Variable Documentation

◆ ABRM_ACCESS_PRIVILEGE_ADDR

const uint32_t ABRM_ACCESS_PRIVILEGE_ADDR = 0x00204

◆ ABRM_DEVICE_CAPABILITY_ADDR

const uint32_t ABRM_DEVICE_CAPABILITY_ADDR = 0x001C4

◆ ABRM_DEVICE_CONFIGURATION_ADDR

const uint32_t ABRM_DEVICE_CONFIGURATION_ADDR = 0x001E0

◆ ABRM_DEVICE_VERSION_ADDR

const uint32_t ABRM_DEVICE_VERSION_ADDR = 0x000C4

◆ ABRM_FAMILY_NAME_ADDR

const uint32_t ABRM_FAMILY_NAME_ADDR = 0x00084

◆ ABRM_GENCP_VERSION_ADDR

const uint32_t ABRM_GENCP_VERSION_ADDR = 0x00000

◆ ABRM_HEARTBEAT_TIMEOUT_ADDR

const uint32_t ABRM_HEARTBEAT_TIMEOUT_ADDR = 0x001E8

◆ ABRM_IMPLEMENTATION_ENDIANESS_ADDR

const uint32_t ABRM_IMPLEMENTATION_ENDIANESS_ADDR = 0x0020C

◆ ABRM_MANIFEST_TABLE_ADDRESS_ADDR

const uint32_t ABRM_MANIFEST_TABLE_ADDRESS_ADDR = 0x001D0

◆ ABRM_MANUFACTURER_INFO_ADDR

const uint32_t ABRM_MANUFACTURER_INFO_ADDR = 0x00104

◆ ABRM_MANUFACTURER_NAME_ADDR

const uint32_t ABRM_MANUFACTURER_NAME_ADDR = 0x00004

◆ ABRM_MAX_DEVICE_RESPONSE_TIME_ADDR

const uint32_t ABRM_MAX_DEVICE_RESPONSE_TIME_ADDR = 0x001CC

◆ ABRM_MESSAGE_CHANNEL_ID_ADDR

const uint32_t ABRM_MESSAGE_CHANNEL_ID_ADDR = 0x001EC

◆ ABRM_MODEL_NAME_ADDR

const uint32_t ABRM_MODEL_NAME_ADDR = 0x00044

◆ ABRM_PROTOCOL_ENDIANESS_ADDR

const uint32_t ABRM_PROTOCOL_ENDIANESS_ADDR = 0x00208

◆ ABRM_RESERVED_ADDR

const uint32_t ABRM_RESERVED_ADDR = 0x00210

◆ ABRM_SBRM_ADDRESS_ADDR

const uint32_t ABRM_SBRM_ADDRESS_ADDR = 0x001D8

◆ ABRM_SERIAL_NUMBER_ADDR

const uint32_t ABRM_SERIAL_NUMBER_ADDR = 0x00144

◆ ABRM_TIMESTAMP_ADDR

const uint32_t ABRM_TIMESTAMP_ADDR = 0x001F0

◆ ABRM_TIMESTAMP_INCREMENT_ADDR

const uint32_t ABRM_TIMESTAMP_INCREMENT_ADDR = 0x001FC

◆ ABRM_TIMESTAMP_LATCH_ADDR

const uint32_t ABRM_TIMESTAMP_LATCH_ADDR = 0x001F8

◆ ABRM_USER_DEFINED_NAME_ADDR

const uint32_t ABRM_USER_DEFINED_NAME_ADDR = 0x00184

◆ ACQUISITION_MODE_ADDR

const uint32_t ACQUISITION_MODE_ADDR = XML_REGS_OFFSET + 0x0000'A01C

SFNC 5.5.2 AcquisitionMode - Controls acquisition mode.

◆ ACQUISITION_NUM_FRAMES_ADDR

const uint32_t ACQUISITION_NUM_FRAMES_ADDR = XML_REGS_OFFSET + 0x0000'A038

SFNC 5.5.4 AquisitionFrameCount - Number of frames to be captured in MultiFrame mode.

◆ ACQUISITION_START_ADDR

const uint32_t ACQUISITION_START_ADDR = XML_REGS_OFFSET + 0x0000'A018

SFNC 5.5.3 AcquisitionStart - Start/stop image acquisition using the specified acquision mode in the Acquisition Mode register.

◆ ACQUISITION_STOP_ADDR

const uint32_t ACQUISITION_STOP_ADDR = XML_REGS_OFFSET + 0x0000'A03C

SFNC 5.5.4 AquisitionStop - Start/stop image acquisition using the specified acquision mode in the Acquisition Mode register.

◆ AQUISITION_FRAMERATE_ADDR

const uint32_t AQUISITION_FRAMERATE_ADDR = XML_REGS_OFFSET + 0x0000'A000

This register controls the acquisition rate. This is actually the frame interval in usecs.

◆ BAD_PIXEL_CTRL_ADDR

const uint32_t BAD_PIXEL_CTRL_ADDR = XML_REGS_OFFSET + 0x0000'A070

◆ BAD_PIXEL_CTRL_MAP_ADDR

const uint32_t BAD_PIXEL_CTRL_MAP_ADDR = XML_REGS_OFFSET + 0x0000'A074

Set whether to display bad pixel map (as 1s/0s) for debugging.

◆ BALANCE_RATIO_ADDR

const uint32_t BALANCE_RATIO_ADDR = XML_REGS_OFFSET + 0x0000'A42C

◆ BALANCE_RATIO_SELECTOR_ADDR

const uint32_t BALANCE_RATIO_SELECTOR_ADDR = XML_REGS_OFFSET + 0x0000'A428

◆ BALANCE_WHITE_AUTO_ADDR

const uint32_t BALANCE_WHITE_AUTO_ADDR = XML_REGS_OFFSET + 0x0000'A430

◆ BEYOND_MANIFEST_ADDR

const uint32_t BEYOND_MANIFEST_ADDR = 0x20000000

◆ BINNING_HORIZONTAL_ADDR

const uint32_t BINNING_HORIZONTAL_ADDR = XML_REGS_OFFSET + 0x0000'A028

SFNC 4.26 BinningHorizontal - Number of pixels to bin in the horizontal direction.

◆ BINNING_VERTICAL_ADDR

const uint32_t BINNING_VERTICAL_ADDR = XML_REGS_OFFSET + 0x0000'A02C

SFNC 4.28 BinningVertical - Number of pixels to bin in the vertical direction.

◆ BLACK_LEVEL_ADDR

const uint32_t BLACK_LEVEL_ADDR = XML_REGS_OFFSET + 0x0000'A414

◆ BLACK_LEVEL_AUTO_ADDR

const uint32_t BLACK_LEVEL_AUTO_ADDR = XML_REGS_OFFSET + 0x0000'A418

◆ BLACK_LEVEL_AUTOBALANCE_ADDR

const uint32_t BLACK_LEVEL_AUTOBALANCE_ADDR = XML_REGS_OFFSET + 0x0000'A41C

◆ BLACK_LEVEL_BIAS_ADDR

const uint32_t BLACK_LEVEL_BIAS_ADDR = XML_REGS_OFFSET + 0x0000'A440

◆ BLACK_LEVEL_SELECTOR_ADDR

const uint32_t BLACK_LEVEL_SELECTOR_ADDR = XML_REGS_OFFSET + 0x0000'A410

◆ BOARD_TEMPERATURE_ADDR

const uint32_t BOARD_TEMPERATURE_ADDR = XML_REGS_OFFSET + 0x0000'A048

◆ BOOTSTRAP_REGISTER_SIZE_B

const uint32_t BOOTSTRAP_REGISTER_SIZE_B = 0xA000

Size of bootstrap register space.

◆ CCP_ADDR

const uint32_t CCP_ADDR = 0x0000'0A00

This register is used to grant privilege to an application.

◆ CLOCK_SPEED_ADDR

const uint32_t CLOCK_SPEED_ADDR = XML_REGS_OFFSET + 0x0000'A060

◆ COLOR_TRANSF_ENABLE_ADDR

const uint32_t COLOR_TRANSF_ENABLE_ADDR = XML_REGS_OFFSET + 0x0000'A504

◆ COLOR_TRANSF_SELECTOR_ADDR

const uint32_t COLOR_TRANSF_SELECTOR_ADDR = XML_REGS_OFFSET + 0x0000'A500

◆ COLOR_TRANSF_VALUE_ADDR

const uint32_t COLOR_TRANSF_VALUE_ADDR = XML_REGS_OFFSET + 0x0000'A50C

◆ COLOR_TRANSF_VALUE_SELECTOR_ADDR

const uint32_t COLOR_TRANSF_VALUE_SELECTOR_ADDR = XML_REGS_OFFSET + 0x0000'A508

◆ CTRL_SWITCHOVER_KEY_ADDR

const uint32_t CTRL_SWITCHOVER_KEY_ADDR = 0x0000'095C

Key to authenticate primary application switchover requests.

◆ CURRENT_GATEWAY0_ADDR

const uint32_t CURRENT_GATEWAY0_ADDR = 0x0000'0044

This register indicates the default gateway IP address to be used on the given network interface.

◆ CURRENT_IP_ADDR0_ADDR

const uint32_t CURRENT_IP_ADDR0_ADDR = 0x0000'0024

This register reports the IP address for the given network interface once it has been configured.

◆ CURRENT_SUBNET0_ADDR

const uint32_t CURRENT_SUBNET0_ADDR = 0x0000'0034

This register provides the subnet mask of the given interface.

◆ DEBUG_BUFFER_ADDR

const uint32_t DEBUG_BUFFER_ADDR = 0x0030'1000

◆ DEBUG_BUFFER_BYTESWRITTEN_ADDR

const uint32_t DEBUG_BUFFER_BYTESWRITTEN_ADDR = 0x0030'0000

◆ DECIMATION_VERTICAL_ADDR

const uint32_t DECIMATION_VERTICAL_ADDR = XML_REGS_OFFSET + 0x0000'A040

SFNC 4.32 DecimationVertical - Number of rows to skip in the vertical direction.

◆ DEVICE_FIRMWARE_VERSION_ADDR

const uint32_t DEVICE_FIRMWARE_VERSION_ADDR = XML_REGS_OFFSET + 0x0000'2000

◆ DEVICE_FPGA_VERSION_ADDR

const uint32_t DEVICE_FPGA_VERSION_ADDR = XML_REGS_OFFSET + 0x0000'3000

◆ DEVICE_FX3_DATE_ADDR

const uint32_t DEVICE_FX3_DATE_ADDR = XML_REGS_OFFSET + 0x0000'3048

◆ DEVICE_MAC_HIGH0_ADDR

const uint32_t DEVICE_MAC_HIGH0_ADDR = 0x0000'0008

This register stores the MAC address (upper 16-bit) of the given network interface.

◆ DEVICE_MAC_LOW0_ADDR

const uint32_t DEVICE_MAC_LOW0_ADDR = 0x0000'000C

This register stores the MAC address (lower 32-bit) of the given network interface.

◆ DEVICE_MODE_ADDR

const uint32_t DEVICE_MODE_ADDR = 0x0000'0004

This register indicates the character set used by the various strings present in the bootstrap registers and other device-specific information, such as the endianness of multi-byte data.

◆ DEVICE_RESET_ADDR

const uint32_t DEVICE_RESET_ADDR = XML_REGS_OFFSET + 0x0000'2100

◆ DEVICE_SOFTWARE_DATE_ADDR

const uint32_t DEVICE_SOFTWARE_DATE_ADDR = XML_REGS_OFFSET + 0x0000'3008

◆ DEVICE_TEMPERATURE_ADDR

const uint32_t DEVICE_TEMPERATURE_ADDR = XML_REGS_OFFSET + 0x0000'A084

SFNC 3.61 DeviceTemperature.

◆ DEVICE_TEMPERATURE_SELECT_ADDR

const uint32_t DEVICE_TEMPERATURE_SELECT_ADDR = XML_REGS_OFFSET + 0x0000'A080

SFNC 3.60 DeviceTemperatureSelector.

◆ DEVICE_VERSION_ADDR

const uint32_t DEVICE_VERSION_ADDR = 0x0000'0088

This register stores a string containing the version of the device. This string uses the character set indicated in the "string character set" register. The XML device description file should also provide this information to ensure the device matches the description file.

◆ DEVMODE_ASCII

const uint32_t DEVMODE_ASCII = 0x00000002

◆ DEVMODE_BIGENDIAN

const uint32_t DEVMODE_BIGENDIAN = 0x80000000

Flags for DEVICE_MODE register.

◆ DEVMODE_UTF8

const uint32_t DEVMODE_UTF8 = 0x00000001

◆ DIGITAL_IO_LINE_INVERTER_ADDR

const uint32_t DIGITAL_IO_LINE_INVERTER_ADDR = XML_REGS_OFFSET + 0x0000'B11C

◆ DIGITAL_IO_LINE_MODE_ADDR

const uint32_t DIGITAL_IO_LINE_MODE_ADDR = XML_REGS_OFFSET + 0x0000'B104

◆ DIGITAL_IO_LINE_SELECT_ADDR

const uint32_t DIGITAL_IO_LINE_SELECT_ADDR = XML_REGS_OFFSET + 0x0000'B100

◆ DIGITAL_IO_LINE_SOURCE_ADDR

const uint32_t DIGITAL_IO_LINE_SOURCE_ADDR = XML_REGS_OFFSET + 0x0000'B10C

◆ DIGITAL_IO_LINE_STATUS_ADDR

const uint32_t DIGITAL_IO_LINE_STATUS_ADDR = XML_REGS_OFFSET + 0x0000'B118

◆ EDGE_DETECTION_ADDR

const uint32_t EDGE_DETECTION_ADDR = XML_REGS_OFFSET + 0x0000'A04C

◆ EXPOSURE_TIME_ADDR

const uint32_t EXPOSURE_TIME_ADDR = XML_REGS_OFFSET + 0x0000'A004

SFNC 5.7.4 ExposureTime - This register sets the Exposure time (uS).

◆ EXPOSURE_TIME_SELECT_ADDR

const uint32_t EXPOSURE_TIME_SELECT_ADDR = XML_REGS_OFFSET + 0x0000'A08C

SFNC 5.7.3 ExposureTimeSelector - This optional register allows selecting different exposure times (see SFNC).

◆ FAN_CONTROL_ADDR

const uint32_t FAN_CONTROL_ADDR = XML_REGS_OFFSET + 0x0000'B124

control for FAN

◆ FIRST_URL_ADDR

const uint32_t FIRST_URL_ADDR = 0x0000'0200

This register stores the first URL to the XML device description file. This URL must be used as the first choice by the application. This string uses the character set indicated in the "string character set" register.

◆ FREE_RAM_CFG_ADDR

const uint32_t FREE_RAM_CFG_ADDR = XML_REGS_OFFSET + 0x0000'A100

◆ GAIN_ADDR

const uint32_t GAIN_ADDR = XML_REGS_OFFSET + 0x0000'A404

◆ GAIN_AUTO_ADDR

const uint32_t GAIN_AUTO_ADDR = XML_REGS_OFFSET + 0x0000'A408

◆ GAIN_AUTOBALANCE_ADDR

const uint32_t GAIN_AUTOBALANCE_ADDR = XML_REGS_OFFSET + 0x0000'A40C

◆ GAIN_SELECTOR_ADDR

const uint32_t GAIN_SELECTOR_ADDR = XML_REGS_OFFSET + 0x0000'A400

◆ GAMMA_ADDR

const uint32_t GAMMA_ADDR = XML_REGS_OFFSET + 0x0000'A434

◆ GIGE_VERSION_1_2

const uint32_t GIGE_VERSION_1_2 = 0x00010002

Flags for VERSION register.

◆ GIGE_VERSION_2_0

const uint32_t GIGE_VERSION_2_0 = 0x00020000

◆ GVCP_CAP_A

const uint32_t GVCP_CAP_A = 0x00000040

◆ GVCP_CAP_C

const uint32_t GVCP_CAP_C = 0x00000001

◆ GVCP_CAP_CAP

const uint32_t GVCP_CAP_CAP = 0x08000000

◆ GVCP_CAP_DD

const uint32_t GVCP_CAP_DD = 0x01000000

◆ GVCP_CAP_E

const uint32_t GVCP_CAP_E = 0x00000008

◆ GVCP_CAP_ED

const uint32_t GVCP_CAP_ED = 0x00000010

◆ GVCP_CAP_ES

const uint32_t GVCP_CAP_ES = 0x00400000

◆ GVCP_CAP_ES2

const uint32_t GVCP_CAP_ES2 = 0x00040000

◆ GVCP_CAP_HD

const uint32_t GVCP_CAP_HD = 0x20000000

◆ GVCP_CAP_LS

const uint32_t GVCP_CAP_LS = 0x10000000

◆ GVCP_CAP_MT

const uint32_t GVCP_CAP_MT = 0x04000000

◆ GVCP_CAP_PA

const uint32_t GVCP_CAP_PA = 0x00000020

◆ GVCP_CAP_PAS

const uint32_t GVCP_CAP_PAS = 0x00200000

◆ GVCP_CAP_PR

const uint32_t GVCP_CAP_PR = 0x00000004

◆ GVCP_CAP_PTP

const uint32_t GVCP_CAP_PTP = 0x00080000

◆ GVCP_CAP_SAC

const uint32_t GVCP_CAP_SAC = 0x00020000

◆ GVCP_CAP_SN

const uint32_t GVCP_CAP_SN = 0x40000000

◆ GVCP_CAP_TD

const uint32_t GVCP_CAP_TD = 0x02000000

◆ GVCP_CAP_UA

const uint32_t GVCP_CAP_UA = 0x00100000

◆ GVCP_CAP_UN

const uint32_t GVCP_CAP_UN = 0x80000000

Flags for GVCP_CAPABILITY register.

◆ GVCP_CAP_VALUE

const uint32_t GVCP_CAP_VALUE = GVCP_CAP_UN | GVCP_CAP_SN | GVCP_CAP_CAP | GVCP_CAP_W | GVCP_CAP_PR

◆ GVCP_CAP_W

const uint32_t GVCP_CAP_W = 0x00000002

◆ GVCP_CAP_WD

const uint32_t GVCP_CAP_WD = 0x00800000

◆ GVCP_CAPABILITY_ADDR

const uint32_t GVCP_CAPABILITY_ADDR = 0x0000'0934

This register reports the optional GVCP command supported by this device.

◆ GVCP_CONFIGURATION_ADDR

const uint32_t GVCP_CONFIGURATION_ADDR = 0x0000'0954

◆ GVsP_CAP_LB

const uint32_t GVsP_CAP_LB = 0x40000000

◆ GVsP_CAP_SP

const uint32_t GVsP_CAP_SP = 0x80000000

Flags for GVSP_CAPABILITY & GVSP_CONFIGURATION register.

◆ GVsP_CAP_VALUE

const uint32_t GVsP_CAP_VALUE = GVsP_CAP_SP | GVsP_CAP_LB

◆ GVSP_CAPABILITY_ADDR

const uint32_t GVSP_CAPABILITY_ADDR = 0x0000'092C

Bit 1 indicates SCSP availability, bit 2 indicates legacy 16 bit block ID support available. 2-31 reserved.

◆ GVsP_CFG_BL

const uint32_t GVsP_CFG_BL = 0x40000000

Flags for GVSP_CONFIGURATION register.

◆ GVSP_CONFIGURATION_ADDR

const uint32_t GVSP_CONFIGURATION_ADDR = 0x0000'0960

This register enables the 64-bit block_id64 for GVSP.

◆ HDMI_BPP_ADDR

const uint32_t HDMI_BPP_ADDR = BEYOND_MANIFEST_ADDR + 0x38

◆ HDMI_GAMMA_ADDR

const uint32_t HDMI_GAMMA_ADDR = BEYOND_MANIFEST_ADDR + 0x24

◆ HDMI_HEIGHT_ADDR

const uint32_t HDMI_HEIGHT_ADDR = BEYOND_MANIFEST_ADDR + 0x18

◆ HDMI_OFFSET_X_ADDR

const uint32_t HDMI_OFFSET_X_ADDR = BEYOND_MANIFEST_ADDR + 0x0c

◆ HDMI_OFFSET_Y_ADDR

const uint32_t HDMI_OFFSET_Y_ADDR = BEYOND_MANIFEST_ADDR + 0x10

◆ HDMI_OUTPUT_SEL_ADDR

const uint32_t HDMI_OUTPUT_SEL_ADDR = BEYOND_MANIFEST_ADDR + 0x1c

◆ HDMI_START_ADDR

const uint32_t HDMI_START_ADDR = BEYOND_MANIFEST_ADDR + 0x04

◆ HDMI_STOP_ADDR

const uint32_t HDMI_STOP_ADDR = BEYOND_MANIFEST_ADDR + 0x08

◆ HDMI_TESTPATEN_ADDR

const uint32_t HDMI_TESTPATEN_ADDR = BEYOND_MANIFEST_ADDR + 0x34

◆ HDMI_WBBLUE_ADDR

const uint32_t HDMI_WBBLUE_ADDR = BEYOND_MANIFEST_ADDR + 0x30

◆ HDMI_WBGREEN_ADDR

const uint32_t HDMI_WBGREEN_ADDR = BEYOND_MANIFEST_ADDR + 0x2C

◆ HDMI_WBRED_ADDR

const uint32_t HDMI_WBRED_ADDR = BEYOND_MANIFEST_ADDR + 0x28

◆ HDMI_WIDTH_ADDR

const uint32_t HDMI_WIDTH_ADDR = BEYOND_MANIFEST_ADDR + 0x14

◆ HEARTBEAT_TIMEOUT_ADDR

const uint32_t HEARTBEAT_TIMEOUT_ADDR = 0x0000'0938

This registers indicates the current heartbeat timeout in milliseconds.

◆ HOT_PIXEL_CORRECT_ADDR

const uint32_t HOT_PIXEL_CORRECT_ADDR = XML_REGS_OFFSET + 0x0000'A068

◆ IEEE_1588_STATUS_ADDR

const uint32_t IEEE_1588_STATUS_ADDR = 0x0000'096C

Reports the state of the IEEE 1588 clock.

◆ INDICATOR_CONTROL_ADDR

const uint32_t INDICATOR_CONTROL_ADDR = XML_REGS_OFFSET + 0x0000'B120

control indicators / LEDS on camera

◆ INTERNAL_EXP_MODE_ADDR

const uint32_t INTERNAL_EXP_MODE_ADDR = XML_REGS_OFFSET + 0x0000'A200

◆ IS_CAMERA_COLOR_ADDR

const uint32_t IS_CAMERA_COLOR_ADDR = XML_REGS_OFFSET + 0x0000'B200

True if this is a color capable camera.

◆ LUT_ENABLE_ADDR

const uint32_t LUT_ENABLE_ADDR = XML_REGS_OFFSET + 0x0000'A304

◆ LUT_INDEX_ADDR

const uint32_t LUT_INDEX_ADDR = XML_REGS_OFFSET + 0x0000'A30C

◆ LUT_MAXINDEX_ADDR

const uint32_t LUT_MAXINDEX_ADDR = XML_REGS_OFFSET + 0x0000'A308

◆ LUT_MAXVALUE_ADDR

const uint32_t LUT_MAXVALUE_ADDR = XML_REGS_OFFSET + 0x0000'A310

◆ LUT_SELECTOR_ADDR

const uint32_t LUT_SELECTOR_ADDR = XML_REGS_OFFSET + 0x0000'A300

◆ LUT_VALUE_ADDR

const uint32_t LUT_VALUE_ADDR = XML_REGS_OFFSET + 0x0000'A314

◆ MANIFEST_FILE_SIZE_ADDR

const uint32_t MANIFEST_FILE_SIZE_ADDR = MANIFEST_REG_ADDR + 0x08

◆ MANIFEST_REG_ADDR

const uint32_t MANIFEST_REG_ADDR = MANIFEST_TYPE_ADDR + 0x04

◆ MANIFEST_SHA1_ADDR

const uint32_t MANIFEST_SHA1_ADDR = MANIFEST_FILE_SIZE_ADDR + 0x08

◆ MANIFEST_TABLE_ADDR

const uint32_t MANIFEST_TABLE_ADDR = 0x1000'0000

◆ MANIFEST_TABLE_COUNT_ADDR

const uint32_t MANIFEST_TABLE_COUNT_ADDR = MANIFEST_TABLE_ADDR

◆ MANIFEST_TYPE_ADDR

const uint32_t MANIFEST_TYPE_ADDR = MANIFEST_VER_ADDR + 0x04

◆ MANIFEST_VER_ADDR

const uint32_t MANIFEST_VER_ADDR = MANIFEST_TABLE_ADDR + 0x08

◆ MANUFACTURER_INFO_ADDR

const uint32_t MANUFACTURER_INFO_ADDR = 0x0000'00A8

This register stores a string containing additional manufacturer-specific information about the device. This string uses the character set indicated in the "string character set" register.

◆ MANUFACTURER_NAME_ADDR

const uint32_t MANUFACTURER_NAME_ADDR = 0x0000'0048

This registers stores a string containing the manufacturer name. This string uses the character set indicated in the "string character set" register.

◆ MANUFACTURER_REGISTER_SIZE_B

const uint32_t MANUFACTURER_REGISTER_SIZE_B = 0xA000

Size of manufacturer register space.

◆ MCDA_ADDR

const uint32_t MCDA_ADDR = 0x0000'0B10

This register indicates the destination IP address for the message channel.

◆ MCP_ADDR

const uint32_t MCP_ADDR = 0x0000'0B00

This register provides port information about the message channel. The message channel is activated when the host_port field is different from 0. Otherwise, the channel is closed.

◆ MCRC_ADDR

const uint32_t MCRC_ADDR = 0x0000'0B18

This register indicates the number of retransmissions allowed when a message channel message times out. If MCRC is set to 0, then no retransmission is allowed.

◆ MCSP_ADDR

const uint32_t MCSP_ADDR = 0x0000'0B1C

Message Channel Source Port.

◆ MCTT_ADDR

const uint32_t MCTT_ADDR = 0x0000'0B14

This register provides the transmission timeout value in milliseconds. This indicates the amount of time to wait for acknowledge after a message is sent on the message channel before timeout.

◆ MODEL_NAME_ADDR

const uint32_t MODEL_NAME_ADDR = 0x0000'0068

This registers stores a string containing the device model name. This string uses the character set indicated in the "string character set" register.

◆ MSG_CAPABILITY_ADDR

const uint32_t MSG_CAPABILITY_ADDR = 0x0000'0930

Indicates the MCSP capability. Bit 0 is MCSP_Supported.

◆ NB_ACTIVE_LINKS_ADDR

const uint32_t NB_ACTIVE_LINKS_ADDR = 0x0000'0910

This register reports the number of physical links that are currently active.

◆ NB_INTERFACES_ADDR

const uint32_t NB_INTERFACES_ADDR = 0x0000'0600

This register indicates the number of physical network interfaces supported by this device. A device must support at least one network interfaces (the primary interface). In this specification, a device can support at most four network interfaces.

◆ NB_MSG_CHANNELS_ADDR

const uint32_t NB_MSG_CHANNELS_ADDR = 0x0000'0900

This register reports the number of message channel supported by this device. In the current version of this specification, a maximum of 1 message channel can be supported.

◆ NB_STREAM_CHANNELS_ADDR

const uint32_t NB_STREAM_CHANNELS_ADDR = 0x0000'0904

This register reports the number of stream channels supported by this device. A device must support at least one stream channel. A device can support up to 512 stream channels.

◆ NET_IFACE_C_D

const uint32_t NET_IFACE_C_D = 0x00000002

◆ NET_IFACE_C_L

const uint32_t NET_IFACE_C_L = 0x00000004

◆ NET_IFACE_C_MASK

const uint32_t NET_IFACE_C_MASK = NET_IFACE_C_L|NET_IFACE_C_D|NET_IFACE_C_P

◆ NET_IFACE_C_P

const uint32_t NET_IFACE_C_P = 0x00000001

◆ NET_IFACE_C_PG

const uint32_t NET_IFACE_C_PG = 0x40000000

◆ NET_IFACE_C_PR

const uint32_t NET_IFACE_C_PR = 0x80000000

Flags for NET_IFACE_CAPABILITY0 & NET_IFACE_CONFIG0 Register.

◆ NET_IFACE_CAPABILITY0_ADDR

const uint32_t NET_IFACE_CAPABILITY0_ADDR = 0x0000'0010

This register indicates the IP configuration scheme supported on the given network interface. Multiple schemes can be supported simultaneously.

◆ NET_IFACE_CONFIG0_ADDR

const uint32_t NET_IFACE_CONFIG0_ADDR = 0x0000'0014

This register indicates which IP configurations schemes are currently activated on the given network interface.

◆ PA_IP_ADDR

const uint32_t PA_IP_ADDR = 0x0000'0A14

Source IP address of the control channel of the primary application.

◆ PA_PORT_ADDR

const uint32_t PA_PORT_ADDR = 0x0000'0A04

UDP source port of the control channel of the primary application.

◆ PAYLOAD_SIZE_ADDR

const uint32_t PAYLOAD_SIZE_ADDR = XML_REGS_OFFSET + 0x0000'A024

SFNC 25.2.5 PayloadSize - Size of frame without headers.

◆ PENDING_TIMEOUT_ADDR

const uint32_t PENDING_TIMEOUT_ADDR = 0x0000'0958

Pending Timeout to report the longest GVCP command execution time before issuing a PENDING_ACK. If PENDING_ACK is not supported, then this is the worst-case execution time before command completion.

◆ PERSISTENT_GATEWAY0_ADDR

const uint32_t PERSISTENT_GATEWAY0_ADDR = 0x0000'066C

This register indicates the persistent default gateway for this network interface. It is only used when the device boots with the Persistent IP configuration scheme.

◆ PERSISTENT_IP_ADDR0_ADDR

const uint32_t PERSISTENT_IP_ADDR0_ADDR = 0x0000'064C

This register indicates the Persistent IP address for this network interface. It is only used when the device boots with the Persistent IP configuration scheme.

◆ PERSISTENT_SUBNET0_ADDR

const uint32_t PERSISTENT_SUBNET0_ADDR = 0x0000'065C

This register indicates the Persistent subnet mask associated with the Persistent IP address on this network interface. It is only used when the device boots with the Persistent IP configuration scheme.

◆ PHY_CAP_DLAG

const uint32_t PHY_CAP_DLAG = 0x00000008

Flags for PHY_CAPABILITY register.

This device supports dynamic link aggregation configuration.

◆ PHY_CAP_ML

const uint32_t PHY_CAP_ML = 0x00000002

This device supports multiple link (ML) configuration.

◆ PHY_CAP_SL

const uint32_t PHY_CAP_SL = 0x00000001

This device supports single link (SL) configuration.

◆ PHY_CAP_SLAG

const uint32_t PHY_CAP_SLAG = 0x00000004

This device supports static link aggregation configuration.

◆ PHY_CAPABILITY_ADDR

const uint32_t PHY_CAPABILITY_ADDR = 0x0000'0964

Indicates the physical link configuration supported by this device.

◆ PHY_CONFIG_ADDR

const uint32_t PHY_CONFIG_ADDR = 0x0000'0968

Indicates the currently active physical link configuration.

◆ PHY_CONFIG_DLAG

const uint32_t PHY_CONFIG_DLAG = 3

Flags for PHY_CONFIG register.

Dynamic link aggregation configuration.

◆ PHY_CONFIG_ML

const uint32_t PHY_CONFIG_ML = 1

Multiple link (ML) configuration.

◆ PHY_CONFIG_SL

const uint32_t PHY_CONFIG_SL = 0

Single link (SL) configuration.

◆ PHY_CONFIG_SLAG

const uint32_t PHY_CONFIG_SLAG = 2

Static link aggregation configuration.

◆ PIXEL_FORMAT_ADDR

const uint32_t PIXEL_FORMAT_ADDR = XML_REGS_OFFSET + 0x0000'A020

SFNC 4.35 PixelFormat - Contains the pixel format.

◆ PIXEL_FORMAT_BAYERBG12P

const uint32_t PIXEL_FORMAT_BAYERBG12P = 0x010C0053

◆ PIXEL_FORMAT_BAYERBG12PACKED

const uint32_t PIXEL_FORMAT_BAYERBG12PACKED = 0x010C002D

◆ PIXEL_FORMAT_BAYERBG16

const uint32_t PIXEL_FORMAT_BAYERBG16 = 0x01100031

◆ PIXEL_FORMAT_BAYERBG8

const uint32_t PIXEL_FORMAT_BAYERBG8 = 0x0108000B

◆ PIXEL_FORMAT_BAYERGB12P

const uint32_t PIXEL_FORMAT_BAYERGB12P = 0x010C0055

◆ PIXEL_FORMAT_BAYERGB12PACKED

const uint32_t PIXEL_FORMAT_BAYERGB12PACKED = 0x010C002C

◆ PIXEL_FORMAT_BAYERGB16

const uint32_t PIXEL_FORMAT_BAYERGB16 = 0x01100030

◆ PIXEL_FORMAT_BAYERGB8

const uint32_t PIXEL_FORMAT_BAYERGB8 = 0x0108000A

◆ PIXEL_FORMAT_BAYERGR12P

const uint32_t PIXEL_FORMAT_BAYERGR12P = 0x010C0057

◆ PIXEL_FORMAT_BAYERGR12PACKED

const uint32_t PIXEL_FORMAT_BAYERGR12PACKED = 0x010C002A

◆ PIXEL_FORMAT_BAYERGR16

const uint32_t PIXEL_FORMAT_BAYERGR16 = 0x0110002E

◆ PIXEL_FORMAT_BAYERGR8

const uint32_t PIXEL_FORMAT_BAYERGR8 = 0x01080008

◆ PIXEL_FORMAT_BAYERRG12P

const uint32_t PIXEL_FORMAT_BAYERRG12P = 0x010C0059

◆ PIXEL_FORMAT_BAYERRG12PACKED

const uint32_t PIXEL_FORMAT_BAYERRG12PACKED = 0x010C002B

◆ PIXEL_FORMAT_BAYERRG16

const uint32_t PIXEL_FORMAT_BAYERRG16 = 0x0110002F

◆ PIXEL_FORMAT_BAYERRG8

const uint32_t PIXEL_FORMAT_BAYERRG8 = 0x01080009

◆ PIXEL_FORMAT_MONO12

const uint32_t PIXEL_FORMAT_MONO12 = 0x01100005

◆ PIXEL_FORMAT_MONO12P

const uint32_t PIXEL_FORMAT_MONO12P = 0x010C0047

◆ PIXEL_FORMAT_MONO12PACKED

const uint32_t PIXEL_FORMAT_MONO12PACKED = 0x010C0007

◆ PIXEL_FORMAT_MONO16

const uint32_t PIXEL_FORMAT_MONO16 = 0x01100007

Flags for PIXEL_FORMAT register.

◆ PIXEL_FORMAT_MONO8

const uint32_t PIXEL_FORMAT_MONO8 = 0x01080001

◆ PRIVILEGE_CONTROL

const uint32_t PRIVILEGE_CONTROL = 0x00000002

Control privilege (read-write)

◆ PRIVILEGE_EXCLUSIVE

const uint32_t PRIVILEGE_EXCLUSIVE = 0x00000001

Flags for CCP register.

Exclusive control privilege (read-write)

◆ REVERSE_X_ADDR

const uint32_t REVERSE_X_ADDR = XML_REGS_OFFSET + 0x0000'A030

SFNC 4.33 ReverseX - "Bool" that flips X when true.

◆ REVERSE_Y_ADDR

const uint32_t REVERSE_Y_ADDR = XML_REGS_OFFSET + 0x0000'A034

SFNC 4.34 ReverseY - "Bool" that flips Y when true.

◆ ROI_HEIGHT_ADDR

const uint32_t ROI_HEIGHT_ADDR = XML_REGS_OFFSET + 0x0000'A00C

SFNC 4.19 Height - This register sets the height of the ROI.

◆ ROI_OFFSET_X_ADDR

const uint32_t ROI_OFFSET_X_ADDR = XML_REGS_OFFSET + 0x0000'A010

SFNC 4.20 OffsetX - This register stores the starting column of the ROI.

◆ ROI_OFFSET_Y_ADDR

const uint32_t ROI_OFFSET_Y_ADDR = XML_REGS_OFFSET + 0x0000'A014

SFNC 4.21 OffsetY - This register stores the starting row of the ROI.

◆ ROI_WIDTH_ADDR

const uint32_t ROI_WIDTH_ADDR = XML_REGS_OFFSET + 0x0000'A008

SFNC 4.18 Width - This register sets the width of the ROI.

◆ SC_CAP_AIT

const uint32_t SC_CAP_AIT = 0x00000004

◆ SC_CAP_BE

const uint32_t SC_CAP_BE = 0x80000000

Flags for SCC0 Register.

◆ SC_CAP_EC

const uint32_t SC_CAP_EC = 0x00000001

◆ SC_CAP_MZ

const uint32_t SC_CAP_MZ = 0x00000010

◆ SC_CAP_PRD

const uint32_t SC_CAP_PRD = 0x00000008

◆ SC_CAP_R

const uint32_t SC_CAP_R = 0x40000000

◆ SC_CAP_US

const uint32_t SC_CAP_US = 0x00000002

◆ SC_CAP_VALUE

const uint32_t SC_CAP_VALUE = 0

◆ SCC0_ADDR

const uint32_t SCC0_ADDR = 0x0000'0D20

First Stream Channel Capability register.

◆ SCCFG0_ADDR

const uint32_t SCCFG0_ADDR = 0x0000'0D24

First Stream Channel Configuration register.

◆ SCDA0_ADDR

const uint32_t SCDA0_ADDR = 0x0000'0D18

This register indicates the destination IP address for this stream channel.

◆ SCHEDULED_ACTION_Q_SIZE_ADDR

const uint32_t SCHEDULED_ACTION_Q_SIZE_ADDR = 0x0000'0970

Indicates the number of Scheduled Action Commands that can be queued (size of the queue).

◆ SCP0_ADDR

const uint32_t SCP0_ADDR = 0x0000'0D00

This register provides port information for this stream channel. The stream channel is activated when the host_port field is different from 0. Otherwise, the channel is closed.

◆ SCPD0_ADDR

const uint32_t SCPD0_ADDR = 0x0000'0D08

This register indicates the delay (in timestamp counter unit) to insert between each packet for this stream channel. This can be used as a crude flow-control mechanism if the application cannot keep up with the packets coming from the device.

◆ SCPS0_ADDR

const uint32_t SCPS0_ADDR = 0x0000'0D04

This register indicates the packet size in bytes for this stream channel. This is the total packet size, including all headers (Ethernet, IP, UDP and GVSP). It also provides a way to set the IP header "do not fragment" bit and to send stream test packet to the application.

◆ SCPS_D

const uint32_t SCPS_D = 0x40000000

◆ SCPS_F

const uint32_t SCPS_F = 0x80000000

Flags for SCPS0 Register.

◆ SCPS_MASK

const uint32_t SCPS_MASK = SCPS_F|SCPS_D|SCPS_PKT_SIZE_MASK

◆ SCPS_P

const uint32_t SCPS_P = 0x20000000

◆ SCPS_PKT_SIZE_MASK

const uint32_t SCPS_PKT_SIZE_MASK = 0x0000FFFF

◆ SCSP0_ADDR

const uint32_t SCSP0_ADDR = 0x0000'0D1C

This register indicates the source port of the GVSP stream.

◆ SECOND_URL_ADDR

const uint32_t SECOND_URL_ADDR = 0x0000'0400

This register stores the second URsi_meL to the XML device description file. This URL is an alternative if the application was unsuccessful to retrieve the device description file using the first URL. This string uses the character set indicated in the "string character set" register.

◆ SENS_MIN_FRAME_PERIOD_ADDR

const uint32_t SENS_MIN_FRAME_PERIOD_ADDR = XML_REGS_OFFSET + 0x0000'C020

◆ SENS_PEEKPOKE_ADDR

const uint32_t SENS_PEEKPOKE_ADDR = XML_REGS_OFFSET + 0x0020'0000

◆ SENS_PEEKPOKE_ADDR_END

const uint32_t SENS_PEEKPOKE_ADDR_END = XML_REGS_OFFSET + 0x0023'FFFF

◆ SENS_READ_ADDR

const uint32_t SENS_READ_ADDR = XML_REGS_OFFSET + 0x0000'C008

◆ SENS_REG_ADDR_ADDR

const uint32_t SENS_REG_ADDR_ADDR = XML_REGS_OFFSET + 0x0000'C000

◆ SENS_SPECIFIC_10_ADDR

const uint32_t SENS_SPECIFIC_10_ADDR = XML_REGS_OFFSET + 0x0000'D024

◆ SENS_SPECIFIC_11_ADDR

const uint32_t SENS_SPECIFIC_11_ADDR = XML_REGS_OFFSET + 0x0000'D064

◆ SENS_SPECIFIC_12_ADDR

const uint32_t SENS_SPECIFIC_12_ADDR = XML_REGS_OFFSET + 0x0000'D068

◆ SENS_SPECIFIC_13_ADDR

const uint32_t SENS_SPECIFIC_13_ADDR = XML_REGS_OFFSET + 0x0000'D06C

◆ SENS_SPECIFIC_14_ADDR

const uint32_t SENS_SPECIFIC_14_ADDR = XML_REGS_OFFSET + 0x0000'D070

◆ SENS_SPECIFIC_15_ADDR

const uint32_t SENS_SPECIFIC_15_ADDR = XML_REGS_OFFSET + 0x0000'D074

◆ SENS_SPECIFIC_16_ADDR

const uint32_t SENS_SPECIFIC_16_ADDR = XML_REGS_OFFSET + 0x0000'D078

◆ SENS_SPECIFIC_17_ADDR

const uint32_t SENS_SPECIFIC_17_ADDR = XML_REGS_OFFSET + 0x0000'D07C

◆ SENS_SPECIFIC_18_ADDR

const uint32_t SENS_SPECIFIC_18_ADDR = XML_REGS_OFFSET + 0x0000'D080

◆ SENS_SPECIFIC_19_ADDR

const uint32_t SENS_SPECIFIC_19_ADDR = XML_REGS_OFFSET + 0x0000'D084

◆ SENS_SPECIFIC_1_ADDR

const uint32_t SENS_SPECIFIC_1_ADDR = XML_REGS_OFFSET + 0x0000'D000

◆ SENS_SPECIFIC_20_ADDR

const uint32_t SENS_SPECIFIC_20_ADDR = XML_REGS_OFFSET + 0x0000'D088

◆ SENS_SPECIFIC_21_ADDR

const uint32_t SENS_SPECIFIC_21_ADDR = XML_REGS_OFFSET + 0x0000'D08C

◆ SENS_SPECIFIC_22_ADDR

const uint32_t SENS_SPECIFIC_22_ADDR = XML_REGS_OFFSET + 0x0000'D090

◆ SENS_SPECIFIC_23_ADDR

const uint32_t SENS_SPECIFIC_23_ADDR = XML_REGS_OFFSET + 0x0000'D094

◆ SENS_SPECIFIC_24_ADDR

const uint32_t SENS_SPECIFIC_24_ADDR = XML_REGS_OFFSET + 0x0000'D098

◆ SENS_SPECIFIC_25_ADDR

const uint32_t SENS_SPECIFIC_25_ADDR = XML_REGS_OFFSET + 0x0000'D09C

◆ SENS_SPECIFIC_26_ADDR

const uint32_t SENS_SPECIFIC_26_ADDR = XML_REGS_OFFSET + 0x0000'D0A0

◆ SENS_SPECIFIC_27_ADDR

const uint32_t SENS_SPECIFIC_27_ADDR = XML_REGS_OFFSET + 0x0000'D0A4

◆ SENS_SPECIFIC_28_ADDR

const uint32_t SENS_SPECIFIC_28_ADDR = XML_REGS_OFFSET + 0x0000'D0A8

◆ SENS_SPECIFIC_29_ADDR

const uint32_t SENS_SPECIFIC_29_ADDR = XML_REGS_OFFSET + 0x0000'D0AC

◆ SENS_SPECIFIC_2_ADDR

const uint32_t SENS_SPECIFIC_2_ADDR = XML_REGS_OFFSET + 0x0000'D004

◆ SENS_SPECIFIC_30_ADDR

const uint32_t SENS_SPECIFIC_30_ADDR = XML_REGS_OFFSET + 0x0000'D0B0

◆ SENS_SPECIFIC_3_ADDR

const uint32_t SENS_SPECIFIC_3_ADDR = XML_REGS_OFFSET + 0x0000'D008

◆ SENS_SPECIFIC_4_ADDR

const uint32_t SENS_SPECIFIC_4_ADDR = XML_REGS_OFFSET + 0x0000'D00C

◆ SENS_SPECIFIC_5_ADDR

const uint32_t SENS_SPECIFIC_5_ADDR = XML_REGS_OFFSET + 0x0000'D010

◆ SENS_SPECIFIC_6_ADDR

const uint32_t SENS_SPECIFIC_6_ADDR = XML_REGS_OFFSET + 0x0000'D014

◆ SENS_SPECIFIC_7_ADDR

const uint32_t SENS_SPECIFIC_7_ADDR = XML_REGS_OFFSET + 0x0000'D018

◆ SENS_SPECIFIC_8_ADDR

const uint32_t SENS_SPECIFIC_8_ADDR = XML_REGS_OFFSET + 0x0000'D01C

◆ SENS_SPECIFIC_9_ADDR

const uint32_t SENS_SPECIFIC_9_ADDR = XML_REGS_OFFSET + 0x0000'D020

◆ SENS_SPECIFIC_FLOAT_1_ADDR

const uint32_t SENS_SPECIFIC_FLOAT_1_ADDR = XML_REGS_OFFSET + 0x0000'D100

◆ SENS_SPECIFIC_FLOAT_2_ADDR

const uint32_t SENS_SPECIFIC_FLOAT_2_ADDR = XML_REGS_OFFSET + 0x0000'D104

◆ SENS_SPECIFIC_FLOAT_3_ADDR

const uint32_t SENS_SPECIFIC_FLOAT_3_ADDR = XML_REGS_OFFSET + 0x0000'D108

◆ SENS_SPECIFIC_FLOAT_4_ADDR

const uint32_t SENS_SPECIFIC_FLOAT_4_ADDR = XML_REGS_OFFSET + 0x0000'D10c

◆ SENS_SPECIFIC_FLOAT_5_ADDR

const uint32_t SENS_SPECIFIC_FLOAT_5_ADDR = XML_REGS_OFFSET + 0x0000'D110

◆ SENS_VAL_ADDR

const uint32_t SENS_VAL_ADDR = XML_REGS_OFFSET + 0x0000'C004

◆ SENS_WRITE_ADDR

const uint32_t SENS_WRITE_ADDR = XML_REGS_OFFSET + 0x0000'C00C

◆ SENSOR_CALIBRATE_ADDR

const uint32_t SENSOR_CALIBRATE_ADDR = XML_REGS_OFFSET + 0x0000'A058

◆ SENSOR_GAINMODE_ADDR

const uint32_t SENSOR_GAINMODE_ADDR = XML_REGS_OFFSET + 0x0000'A054

◆ SENSOR_HEIGHT_ADDR

const uint32_t SENSOR_HEIGHT_ADDR = XML_REGS_OFFSET + 0x0000'A094

SFNC 4.3 SensorHeight - Effective height of sensor in pixels.

◆ SENSOR_TEMPERATURE_ADDR

const uint32_t SENSOR_TEMPERATURE_ADDR = XML_REGS_OFFSET + 0x0000'A044

◆ SENSOR_WIDTH_ADDR

const uint32_t SENSOR_WIDTH_ADDR = XML_REGS_OFFSET + 0x0000'A090

SFNC 4.2 SensorWidth - Effective width of sensor in pixels.

◆ SERIAL_NUMBER_ADDR

const uint32_t SERIAL_NUMBER_ADDR = 0x0000'00D8

String providing the serial number of this device.

◆ SHUTTER_MODE_ADDR

const uint32_t SHUTTER_MODE_ADDR = XML_REGS_OFFSET + 0x0000'A050

◆ SHUTTERMODE_GLOBAL

const uint32_t SHUTTERMODE_GLOBAL = 0x00000001

◆ SHUTTERMODE_ROLLING

const uint32_t SHUTTERMODE_ROLLING = 0x00000000

Flags for SHUTTER_MODE register.

◆ SQRT_COMPRESS_ADDR

const uint32_t SQRT_COMPRESS_ADDR = XML_REGS_OFFSET + 0x0000'A064

◆ TEST_PATTERN_ADDR

const uint32_t TEST_PATTERN_ADDR = XML_REGS_OFFSET + 0x0000'A05C

◆ TEST_PENDING_ACK_ADDR

const uint32_t TEST_PENDING_ACK_ADDR = BEYOND_MANIFEST_ADDR

◆ TIMESTAMP_CTRL_ADDR

const uint32_t TIMESTAMP_CTRL_ADDR = 0x0000'0944

This register is used to control the timestamp counter.

◆ TIMESTAMP_CTRL_L

const uint32_t TIMESTAMP_CTRL_L = 0x00000002

Flags for TIMESTAMP_CTRL Register.

◆ TIMESTAMP_CTRL_R

const uint32_t TIMESTAMP_CTRL_R = 0x00000001

◆ TIMESTAMP_FREQ_HIGH_ADDR

const uint32_t TIMESTAMP_FREQ_HIGH_ADDR = 0x0000'093C

This register indicates the number of timestamp tick during 1 second. This corresponds to the timestamp frequency in Hertz. Upper 32-bit.

◆ TIMESTAMP_FREQ_LOW_ADDR

const uint32_t TIMESTAMP_FREQ_LOW_ADDR = 0x0000'0940

This register indicates the number of timestamp tick during 1 second. This corresponds to the timestamp frequency in Hertz. Lower 32-bit.

◆ TIMESTAMP_VALUE_HIGH_ADDR

const uint32_t TIMESTAMP_VALUE_HIGH_ADDR = 0x0000'0948

This register reports the latched value of the timestamp counter. It is necessary to latch the 64-bit timestamp value to guaranty its integrity when performing the two 32-bit read accesses to retrieve the higher and lower 32-bit portions. Upper 32-bit.

◆ TIMESTAMP_VALUE_LOW_ADDR

const uint32_t TIMESTAMP_VALUE_LOW_ADDR = 0x0000'094C

This register reports the latched value of the timestamp counter. It is necessary to latch the 64-bit timestamp value to guaranty its integrity when performing the two 32-bit read accesses to retrieve the higher and lower 32-bit portions. Lower 32-bit.

◆ TOTAL_REGISTER_SIZE_B

const uint32_t TOTAL_REGISTER_SIZE_B = MANUFACTURER_REGISTER_SIZE_B + BOOTSTRAP_REGISTER_SIZE_B + XML_FILE_SIZE_B

◆ TRIGGER_ACTIVATION_ADDR

const uint32_t TRIGGER_ACTIVATION_ADDR = XML_REGS_OFFSET + 0x0000'B00C

◆ TRIGGER_MODE_ADDR

const uint32_t TRIGGER_MODE_ADDR = XML_REGS_OFFSET + 0x0000'B004

◆ TRIGGER_SELECTOR_ADDR

const uint32_t TRIGGER_SELECTOR_ADDR = XML_REGS_OFFSET + 0x0000'B000

◆ TRIGGER_SOURCE_ADDR

const uint32_t TRIGGER_SOURCE_ADDR = XML_REGS_OFFSET + 0x0000'B008

◆ U3V_CP_CABABILITY_ADDR

const uint32_t U3V_CP_CABABILITY_ADDR = SBRM_TABLE_ADDR + 0x04

◆ U3V_CP_CAPABILITY

const uint64_t U3V_CP_CAPABILITY = U3V_SIRM_AVAILABLE

◆ U3V_CP_CONFIGURATION

const uint64_t U3V_CP_CONFIGURATION = 0

◆ U3V_CP_CONFIGURATION_ADDR

const uint32_t U3V_CP_CONFIGURATION_ADDR = SBRM_TABLE_ADDR + 0x0C

◆ U3V_CURRENT_SPEED_ADDR

const uint32_t U3V_CURRENT_SPEED_ADDR = SBRM_TABLE_ADDR + 0x40

◆ U3V_DEVICE_CAPABILITY

◆ U3V_DEVICE_CONFIGURATION

const uint64_t U3V_DEVICE_CONFIGURATION = 0

◆ U3V_EIRM_ADDRESS_ADDR

const uint32_t U3V_EIRM_ADDRESS_ADDR = SBRM_TABLE_ADDR + 0x2C

◆ U3V_EIRM_LENGTH_ADDR

const uint32_t U3V_EIRM_LENGTH_ADDR = SBRM_TABLE_ADDR + 0x34

◆ U3V_IIDC2_ADDRESS_ADDR

const uint32_t U3V_IIDC2_ADDRESS_ADDR = SBRM_TABLE_ADDR + 0x38

◆ U3V_MAX_ACK_LEN

const uint32_t U3V_MAX_ACK_LEN = U3V_CMD_EP_BUFF_SIZE

◆ U3V_MAX_ACK_TRANS_ADDR

const uint32_t U3V_MAX_ACK_TRANS_ADDR = SBRM_TABLE_ADDR + 0x18

◆ U3V_MAX_CMD_LEN

const uint32_t U3V_MAX_CMD_LEN = U3V_CMD_EP_BUFF_SIZE

◆ U3V_MAX_COMMAND_TRANS_ADDR

const uint32_t U3V_MAX_COMMAND_TRANS_ADDR = SBRM_TABLE_ADDR + 0x14

◆ U3V_MAX_LEADER_ADDR

const uint32_t U3V_MAX_LEADER_ADDR = U3V_SIRM_TABLE_ADDR + 0x18

◆ U3V_MAX_TRAILER_SIZE_ADDR

const uint32_t U3V_MAX_TRAILER_SIZE_ADDR = U3V_SIRM_TABLE_ADDR + 0x2C

◆ U3V_NB_STREAMS

const uint32_t U3V_NB_STREAMS = 1

◆ U3V_NB_STRTEAM_ADDR

const uint32_t U3V_NB_STRTEAM_ADDR = SBRM_TABLE_ADDR + 0x1C

◆ U3V_PAYLOAD_COUNT_ADDR

const uint32_t U3V_PAYLOAD_COUNT_ADDR = U3V_SIRM_TABLE_ADDR + 0x20

◆ U3V_PAYLOAD_FINAL1_ADDR

const uint32_t U3V_PAYLOAD_FINAL1_ADDR = U3V_SIRM_TABLE_ADDR + 0x24

◆ U3V_PAYLOAD_FINAL2_ADDR

const uint32_t U3V_PAYLOAD_FINAL2_ADDR = U3V_SIRM_TABLE_ADDR + 0x28

◆ U3V_PAYLOAD_SIZE_ADDR

const uint32_t U3V_PAYLOAD_SIZE_ADDR = U3V_SIRM_TABLE_ADDR + 0x1C

◆ U3V_REQ_LEADER_SIZE_ADDR

const uint32_t U3V_REQ_LEADER_SIZE_ADDR = U3V_SIRM_TABLE_ADDR + 0x10

◆ U3V_REQ_PAYLOAD_SIZE_ADDR

const uint32_t U3V_REQ_PAYLOAD_SIZE_ADDR = U3V_SIRM_TABLE_ADDR + 0x08

◆ U3V_REQ_TRAILER_SIZE_ADDR

const uint32_t U3V_REQ_TRAILER_SIZE_ADDR = U3V_SIRM_TABLE_ADDR + 0x14

◆ U3V_SIRM_ADDRESS_ADDR

const uint32_t U3V_SIRM_ADDRESS_ADDR = SBRM_TABLE_ADDR + 0x20

◆ U3V_SIRM_CTRL_ADDR

const uint32_t U3V_SIRM_CTRL_ADDR = U3V_SIRM_TABLE_ADDR + 0x04

◆ U3V_SIRM_INFO_ADDR

const uint32_t U3V_SIRM_INFO_ADDR = U3V_SIRM_TABLE_ADDR

◆ U3V_SIRM_LENGTH

const uint32_t U3V_SIRM_LENGTH = 0x30

◆ U3V_SIRM_LENGTH_ADDR

const uint32_t U3V_SIRM_LENGTH_ADDR = SBRM_TABLE_ADDR + 0x28

◆ U3V_SIRM_TABLE_ADDR

const uint32_t U3V_SIRM_TABLE_ADDR = 0x20000

◆ U3V_VERSION

const uint32_t U3V_VERSION = 0x00010001

◆ U3V_VERSION_ADDR

const uint32_t U3V_VERSION_ADDR = SBRM_TABLE_ADDR

◆ USER_NAME_ADDR

const uint32_t USER_NAME_ADDR = 0x0000'00E8

String providing the device name.

◆ USER_OUTPUT_SELECTOR_ADDR

const uint32_t USER_OUTPUT_SELECTOR_ADDR = XML_REGS_OFFSET + 0x0000'B110

◆ USER_OUTPUT_VALUE_ADDR

const uint32_t USER_OUTPUT_VALUE_ADDR = XML_REGS_OFFSET + 0x0000'B114

◆ VERSION_ADDR

const uint32_t VERSION_ADDR = 0x0000'0000

This register indicates the version of the GigE Vision specification implemented by this device. Version 1.0 of this specification shall return 0x00010000.

◆ VOLTAGE_SENSOR_SELECT_ADDR

const uint32_t VOLTAGE_SENSOR_SELECT_ADDR = XML_REGS_OFFSET + 0x0000'A078

Selects which ADC / voltage sensor to read back.

◆ VOLTAGE_SENSOR_VALUE_ADDR

const uint32_t VOLTAGE_SENSOR_VALUE_ADDR = XML_REGS_OFFSET + 0x0000'A07C

retrieves selected ADC voltage sensor value

◆ WHITE_CLIP_ADDR

const uint32_t WHITE_CLIP_ADDR = XML_REGS_OFFSET + 0x0000'A424

◆ WHITE_CLIP_SELECTOR_ADDR

const uint32_t WHITE_CLIP_SELECTOR_ADDR = XML_REGS_OFFSET + 0x0000'A420

◆ XML_FILE_ADDR

const uint32_t XML_FILE_ADDR = XML_REGS_OFFSET + 0x0001'4000

This is where the XML file is loaded into memory.

◆ XML_FILE_SIZE_B

const uint32_t XML_FILE_SIZE_B = 0xA000

Size allocated for XML file in register space.

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