RegisterFile.h

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#ifndef REGISTERFILE_H
#define REGISTERFILE_H
 
#include <map>
#include <iostream>
 
#include <climits>
#include <stdint.h>
#include <sys/types.h>
#include <sys/socket.h>
#include <netinet/in.h>
#include <netdb.h>
 
#include "CommandInterface/RegisterFileObserver.h"
#include "Utility/Observable.h"
#include "GigE.h"
 
#include "PayloadSetter.h"
 
#include "Sensors/SensorBoard.h"
 
 
const uint32_t MANUFACTURER_REGISTER_SIZE_B = 0xA000;  
const uint32_t BOOTSTRAP_REGISTER_SIZE_B    = 0xA000;  
const uint32_t XML_FILE_SIZE_B              = 0xA000;  
const uint32_t TOTAL_REGISTER_SIZE_B        = MANUFACTURER_REGISTER_SIZE_B + BOOTSTRAP_REGISTER_SIZE_B + XML_FILE_SIZE_B;
 
// Yea macros shouldn't be used too often, but these make it a whole lot faster to add an element to the
// register definition table. They make it even an order of magnitude faster when adding fields to the
// tsRegDefinition structure.
#define REG_ACCESS_NA    0,0        //<! Access mode NA - Not Available.
#define REG_ACCESS_WO    0,1        //<! Access mode WO - Write Only
#define REG_ACCESS_RO    1,0        //<! Access mode RO - Read Only
#define REG_ACCESS_RW    1,1        //<! Access mode RW - Readable & Writable
 
//typedef struct
//{
//    uint64_t    address;
//    const char* name;
//    uint32_t    size;
//    teRegType   type;
//    bool        rdaccess;
//    bool        wraccess;
//    union {
//      uint32_t    dfltnval;
//      float       dfltfval;
//      uint64_t    dfltlval;
//    };
//    const char* dfltsval;
//} tsRegDefinition;
 
#define REGDEF_I64(name,access,dflt)      { name ## _ADDR, #name, sizeof(uint64_t), SocCamera::eeRegUint64, REG_ACCESS_ ## access, { .dfltlval = dflt }, std::string() }
#define REGDEF_INT(name,access,dflt)      { name ## _ADDR, #name, sizeof(uint32_t), SocCamera::eeRegUint32, REG_ACCESS_ ## access, { .dfltnval = dflt }, std::string() }
#define REGDEF_FLT(name,access,dflt)      { name ## _ADDR, #name, sizeof(float), SocCamera::eeRegFloat, REG_ACCESS_ ## access, { .dfltfval = dflt }, std::string() }
#define REGDEF_STR(name,access,size,dflt) { name ## _ADDR, #name, size, SocCamera::eeRegString, REG_ACCESS_ ## access, { .dfltnval = 0 }, dflt }
#define REGDEF_BUF(name,access,size)      { name ## _ADDR, #name, size, SocCamera::eeRegNoType, REG_ACCESS_ ## access, { .dfltrptr = nullptr }, std::string() }
#define REGDEF_END_OF_TABLE               { 0xFFFFFFFF,NULL,0,SocCamera::eeRegUint32,0,0,{ .dfltnval = 0 },std::string() }
 
namespace SocCamera
{
typedef enum {
    eeRegNoType, 
    eeRegUint32, 
    eeRegFloat,  
    eeRegUint64, 
    eeRegString, 
} teRegType;
 
class tcRegisterFile : public tcObservable, public tcRegisterFileObservable
{
public:
 
    static const uint32_t cnNOADDRESS;
 
    //{
    static const uint32_t cnMAX_IMAGE_WIDTH  = 3360;
    static const uint32_t cnMAX_IMAGE_HEIGHT = 2496;
    static const uint32_t cnMAX_PAYLOAD_SIZE = cnMAX_IMAGE_WIDTH * cnMAX_IMAGE_HEIGHT * 2;
    //}
 
    typedef union {
        uint32_t    dfltnval; 
        float       dfltfval; 
        uint64_t    dfltlval; 
        void*       dfltrptr; 
    } tuDataType;
 
    typedef enum {
        eeLittleEndian,
        eeBigEndian
    } teEndianness;
 
    typedef struct
    {
        uint64_t    address;   
        const char* name;      
        uint32_t    size;      
        teRegType   type;      
        bool        rdaccess;  
        bool        wraccess;  
        tuDataType  numData;   
        std::string dfltsval;  
    } tsRegDefinition;
 
    static bool instanceMade();
 
    static tcRegisterFile* getInstance(tsRegDefinition * apRegs = NULL, bool abBigEndian = true);
    void initialize(tcSensorBoard* apSensor, tcPayloadSetter *apIface);
 
    int         get_array               (uint32_t address, uint8_t* buff, uint16_t length) const;
 
    int         get_buffer              (uint32_t address, const char*& ptr, uint32_t& length) const;
    void        update_buffer           (uint32_t address, const uint8_t* buff, uint32_t length);
    GEV_STATUS  set_buffer              (uint32_t address, const uint8_t* buff, uint32_t length);
 
    uint32_t    get_word                (uint32_t address);
    void        update_word             (uint32_t address, uint32_t data);      
    GEV_STATUS  set_word                (uint32_t address, uint32_t data);
 
    uint64_t    get_long                (uint32_t address);
    void        update_long             (uint32_t address, uint64_t data);      
    GEV_STATUS  set_long                (uint32_t address, uint64_t data);
 
    float       get_float               (uint32_t address);
    void        update_float            (uint32_t address, float data);         
    GEV_STATUS  set_float               (uint32_t address, float data);
 
    std::string get_string              (uint32_t address);
    void        update_string           (uint32_t address, const char* data, int len = -1);   
    GEV_STATUS  set_string              (uint32_t address, const char* data);
 
    void sync_manifest_table(const std::string &arXmlFile, const uint64_t fpga_version);
    void sync_user_name(uint64_t anAddress);
 
    void check_and_update_payload_size(uint64_t address);
 
    template <typename T>
    static T swap_endian(T u)
    {
        union
        {
            T u;
            unsigned char u8[sizeof(T)];
        } source, dest;
 
        source.u = u;
 
        for (size_t k = 0; k < sizeof(T); k++)
            dest.u8[k] = source.u8[sizeof(T) - k - 1];
 
        return dest.u;
    }
 
    tsRegDefinition* reg_def (const char *name) const;
    tsRegDefinition* reg_def (uint64_t address, bool sloppy = false) const;
    tsRegDefinition* next_reg(uint64_t address) const;
 
    uint32_t    reg_addr     (const char *name);
    int         reg_size     (uint32_t address);
    std::string reg_name     (uint32_t address);
    bool        reg_valid    (uint32_t address);                 
    bool        reg_rd       (uint32_t address);                 
    bool        reg_wr       (uint32_t address);                 
    bool        reg_a_valid  (uint32_t address, int16_t size);   
    bool        reg_a_rd     (uint32_t address, int16_t size);   
    bool        reg_a_wr     (uint32_t address, int16_t size);   
 
    void  show_register  (const tsRegDefinition* pregdef);
    void  show_all_registers ();
    static std::string format_memdump (uint8_t* pbuff, uint16_t length);
 
    void  update_payload_size ();
 
    void    latch_timestamp ();
    void    reset_timestamp ();
 
    void sharedInit();
 
    const struct timespec* get_resettime() { return &m_ts_resettime; }
 
    int addRegister(tsRegDefinition* pdef);
 
protected:
    tcRegisterFile(tsRegDefinition* apRegs, bool abBigEndian);
 
    template <typename ValueType, teRegType RegEnum>
    ValueType get_value (uint64_t address) {
        ValueType retv = 0;
        const tsRegDefinition* preg = this->reg_def (address, false);
        if (preg != NULL && preg->type == RegEnum)
        {
            memcpy(&retv, &(preg->numData), sizeof(ValueType));
        }
        return retv;
    }
 
    template <typename ValueType, teRegType RegEnum>
    void update_value(uint64_t address, ValueType data)
    {
        tsRegDefinition* preg = reg_def (address, false);
        if (preg != NULL /*&& preg->type == RegEnum*/) // Don't look at the register type here as; this is a quick and dirty update.
        {
            ValueType uitemp;
            memcpy(&uitemp, &data, sizeof(ValueType));
            memcpy(&(preg->numData), &uitemp, sizeof(ValueType));
 
            // this will ensure that any register change that impacts payload size
            // is caught and handled.
            check_and_update_payload_size(address);
        }
    }
 
    template <typename ValueType, teRegType RegEnum, typename UpdateMsg>
    GEV_STATUS set_value (uint32_t address, ValueType data) {
        GEV_STATUS retv = GEV_STATUS_INVALID_ADDRESS;
        const tsRegDefinition* preg = reg_def (address, false);
 
        if (preg != NULL && preg->type == RegEnum)
        {
            ValueType old_value;
            memcpy(&old_value, &(preg->numData), sizeof(ValueType));
 
            if(mbBigEndian)
                old_value = swap_endian<ValueType>(old_value);
 
            tsRegDefinition pdef = *preg;
            pdef.address = address;
            UpdateMsg *regMsg = new UpdateMsg (&pdef, old_value, data);
 
            // Pass this register write through all of the command handlers.
            // Note: The command handler linked list is mostly setup in tcCommandInterface::tcCommandInterface(),
            // but a few other handlers are setup somewhere else which I cant find yet i.e. tcGigEIO::update()
            // gets called, but I'll be bejiggered if I can figure out how.
            tsUpdate notifyMsg;
            notifyMsg.mpMessage    = regMsg;
            notifyMsg.mpObservable = this;
            notifyChange(notifyMsg);
 
            // If everything went well, then we can update the register.
            // Actually update even if we did get an error. We're making it the handler's
            // responsiblity to put the "old" value into the "fix" value when there is an
            // error, or if for some wierd reason they want something other than the old
            // value, I'm okay with that what do I know here as a mere observable.
            if(mbBigEndian)
                regMsg->m_fixval = swap_endian<ValueType>(regMsg->m_fixval);
 
            update_value<ValueType, RegEnum>(address, regMsg->m_fixval);
 
            retv = regMsg->m_status;
            delete regMsg;
        }
        return retv;
    }
 
private:
    static tcRegisterFile* _instance;
    // Map of key address to RegDefinition pointer. (this is a sparse "array").
    std::map<uint64_t, tsRegDefinition*> maRegisters;
 
    tcPayloadSetter *mpIface;
 
    struct timespec m_ts_resettime;
 
    bool mbBigEndian;
 
    tcSensorBoard *mpSensor;
};
 
 
class tcRegUpdateMsg
{
public:
    tcRegUpdateMsg (const tcRegisterFile::tsRegDefinition *preg)
    {
        m_reg_def = preg;
        m_regtype = preg->type;
        m_address = preg->address;
        m_handled = false;
        m_status  = GEV_STATUS_SUCCESS;
        m_length  = 0;
    }
    const tcRegisterFile::tsRegDefinition *m_reg_def;
    teRegType  m_regtype;   //<! Specifies what kind of data the register holds.
    uint32_t   m_address;   //<! Specifies the registers address.
    bool       m_handled;   //<! Set to true if the register update was handled by an observer. (TODO MAW - I don't think anything uses this field)
    GEV_STATUS m_status;    //<! return errors here if there are any, starts life assuming success.
    uint32_t   m_length;    //<! desired number of bytes to change, 0 = change entire register size
};
 
template<typename T>
class tcRegUpdateTypeMsg : public tcRegUpdateMsg
{
public:
    tcRegUpdateTypeMsg (const tcRegisterFile::tsRegDefinition *preg, T oldval, T newval)
    : tcRegUpdateMsg (preg)
    { m_oldval = oldval; m_newval = newval; m_fixval = newval; }
 
    T m_oldval;      
    T m_newval;      
    T m_fixval;      
};
 
typedef tcRegUpdateTypeMsg<uint64_t> tcRegUpdateUint64Msg;
 
typedef tcRegUpdateTypeMsg<uint32_t> tcRegUpdateUint32Msg;
 
typedef tcRegUpdateTypeMsg<float> tcRegUpdateFloatMsg;
 
typedef tcRegUpdateTypeMsg<std::string> tcRegUpdateStringMsg;
 
typedef tcRegUpdateTypeMsg<void *> tcRegUpdateBufferMsg;
 
}
 
 
 
//===================================================
// GigEV Bootstrap Registers
//===================================================
const uint32_t VERSION_ADDR                 = 0x0000'0000;  //!< This register indicates the version of the GigE Vision specification implemented by this device. Version 1.0 of this specification shall return 0x00010000.
const uint32_t DEVICE_MODE_ADDR             = 0x0000'0004;  
const uint32_t DEVICE_MAC_HIGH0_ADDR        = 0x0000'0008;  //!< This register stores the MAC address (upper 16-bit) of the given network interface.
const uint32_t DEVICE_MAC_LOW0_ADDR         = 0x0000'000C;  
const uint32_t NET_IFACE_CAPABILITY0_ADDR   = 0x0000'0010;  //!< This register indicates the IP configuration scheme supported on the given network interface. Multiple schemes can be supported simultaneously.
const uint32_t NET_IFACE_CONFIG0_ADDR       = 0x0000'0014;  
const uint32_t CURRENT_IP_ADDR0_ADDR        = 0x0000'0024;  //!< This register reports the IP address for the given network interface once it has been configured.
const uint32_t CURRENT_SUBNET0_ADDR         = 0x0000'0034;  
const uint32_t CURRENT_GATEWAY0_ADDR        = 0x0000'0044;  //!< This register indicates the default gateway IP address to be used on the given network interface.
const uint32_t MANUFACTURER_NAME_ADDR       = 0x0000'0048;  
const uint32_t MODEL_NAME_ADDR              = 0x0000'0068;  //!< This registers stores a string containing the device model name. This string uses the character set indicated in the "string character set" register.
const uint32_t DEVICE_VERSION_ADDR          = 0x0000'0088;  
const uint32_t MANUFACTURER_INFO_ADDR       = 0x0000'00A8;  //!< This register stores a string containing additional manufacturer-specific information about the device. This string uses the character set indicated in the "string character set" register.
const uint32_t SERIAL_NUMBER_ADDR           = 0x0000'00D8;  
const uint32_t USER_NAME_ADDR               = 0x0000'00E8;  //!< String providing the device name.
const uint32_t FIRST_URL_ADDR               = 0x0000'0200;  
const uint32_t SECOND_URL_ADDR              = 0x0000'0400;  //!< This register stores the second URsi_meL to the XML device description file. This URL is an alternative if the application was unsuccessful to retrieve the device description file using the first URL. This string uses the character set indicated in the "string character set" register.
const uint32_t NB_INTERFACES_ADDR           = 0x0000'0600;  
const uint32_t PERSISTENT_IP_ADDR0_ADDR     = 0x0000'064C;  //!< This register indicates the Persistent IP address for this network interface. It is only used when the device boots with the Persistent IP configuration scheme.
const uint32_t PERSISTENT_SUBNET0_ADDR      = 0x0000'065C;  
const uint32_t PERSISTENT_GATEWAY0_ADDR     = 0x0000'066C;  //!< This register indicates the persistent default gateway for this network interface. It is only used when the device boots with the Persistent IP configuration scheme.
const uint32_t NB_MSG_CHANNELS_ADDR         = 0x0000'0900;  
const uint32_t NB_STREAM_CHANNELS_ADDR      = 0x0000'0904;  //!< This register reports the number of stream channels supported by this device. A device must support at least one stream channel. A device can support up to 512 stream channels.
const uint32_t NB_ACTIVE_LINKS_ADDR         = 0x0000'0910;  
const uint32_t GVSP_CAPABILITY_ADDR         = 0x0000'092C;  //!< Bit 1 indicates SCSP availability, bit 2 indicates legacy 16 bit block ID support available. 2-31 reserved.
const uint32_t MSG_CAPABILITY_ADDR          = 0x0000'0930;  
const uint32_t GVCP_CAPABILITY_ADDR         = 0x0000'0934;  //!< This register reports the optional GVCP command supported by this device.
const uint32_t HEARTBEAT_TIMEOUT_ADDR       = 0x0000'0938;  
const uint32_t TIMESTAMP_FREQ_HIGH_ADDR     = 0x0000'093C;  //!< This register indicates the number of timestamp tick during 1 second. This corresponds to the timestamp frequency in Hertz. Upper 32-bit.
const uint32_t TIMESTAMP_FREQ_LOW_ADDR      = 0x0000'0940;  
const uint32_t TIMESTAMP_CTRL_ADDR          = 0x0000'0944;  //!< This register is used to control the timestamp counter.
const uint32_t TIMESTAMP_VALUE_HIGH_ADDR    = 0x0000'0948;  
const uint32_t TIMESTAMP_VALUE_LOW_ADDR     = 0x0000'094C;  //!< This register reports the latched value of the timestamp counter. It is necessary to latch the 64-bit timestamp value to guaranty its integrity when performing the two 32-bit read accesses to retrieve the higher and lower 32-bit portions. Lower 32-bit.
const uint32_t GVCP_CONFIGURATION_ADDR      = 0x0000'0954;  //<! Configuration of GVCP optional features.
const uint32_t PENDING_TIMEOUT_ADDR         = 0x0000'0958;  //!< Pending Timeout to report the longest GVCP command execution time before issuing a PENDING_ACK. If PENDING_ACK is not supported, then this is the worst-case execution time before command completion.
const uint32_t CTRL_SWITCHOVER_KEY_ADDR     = 0x0000'095C;  
const uint32_t GVSP_CONFIGURATION_ADDR      = 0x0000'0960;  //!< This register enables the 64-bit block_id64 for GVSP.
const uint32_t PHY_CAPABILITY_ADDR          = 0x0000'0964;  
const uint32_t PHY_CONFIG_ADDR              = 0x0000'0968;  //!< Indicates the currently active physical link configuration
const uint32_t IEEE_1588_STATUS_ADDR        = 0x0000'096C;  
const uint32_t SCHEDULED_ACTION_Q_SIZE_ADDR = 0x0000'0970;  //!< Indicates the number of Scheduled Action Commands that can be queued (size of the queue).
const uint32_t CCP_ADDR                     = 0x0000'0A00;  
const uint32_t PA_PORT_ADDR                 = 0x0000'0A04;  //!< UDP source port of the control channel of the primary application.
const uint32_t PA_IP_ADDR                   = 0x0000'0A14;  
const uint32_t MCP_ADDR                     = 0x0000'0B00;  //!< This register provides port information about the message channel. The message channel is activated when the host_port field is different from 0. Otherwise, the channel is closed.
const uint32_t MCDA_ADDR                    = 0x0000'0B10;  
const uint32_t MCTT_ADDR                    = 0x0000'0B14;  //!< This register provides the transmission timeout value in milliseconds. This indicates the amount of time to wait for acknowledge after a message is sent on the message channel before timeout.
const uint32_t MCRC_ADDR                    = 0x0000'0B18;  
const uint32_t MCSP_ADDR                    = 0x0000'0B1C;  //!< Message Channel Source Port.
const uint32_t SCP0_ADDR                    = 0x0000'0D00;  
const uint32_t SCPS0_ADDR                   = 0x0000'0D04;  //!< This register indicates the packet size in bytes for this stream channel. This is the total packet size, including all headers (Ethernet, IP, UDP and GVSP). It also provides a way to set the IP header "do not fragment" bit and to send stream test packet to the application.
const uint32_t SCPD0_ADDR                   = 0x0000'0D08;  
const uint32_t SCDA0_ADDR                   = 0x0000'0D18;  //!< This register indicates the destination IP address for this stream channel.
const uint32_t SCSP0_ADDR                   = 0x0000'0D1C;  
const uint32_t SCC0_ADDR                    = 0x0000'0D20;  //!< First Stream Channel Capability register.
const uint32_t SCCFG0_ADDR                  = 0x0000'0D24;  
const uint32_t MANIFEST_TABLE_ADDR          = 0x1000'0000;  //!<
 
// GenCP Technology Agnostic Boostrap Registers.
const uint32_t ABRM_GENCP_VERSION_ADDR              = 0x00000;
const uint32_t ABRM_MANUFACTURER_NAME_ADDR          = 0x00004;
const uint32_t ABRM_MODEL_NAME_ADDR                 = 0x00044;
const uint32_t ABRM_FAMILY_NAME_ADDR                = 0x00084;
const uint32_t ABRM_DEVICE_VERSION_ADDR             = 0x000C4;
const uint32_t ABRM_MANUFACTURER_INFO_ADDR          = 0x00104;
const uint32_t ABRM_SERIAL_NUMBER_ADDR              = 0x00144;
const uint32_t ABRM_USER_DEFINED_NAME_ADDR          = 0x00184;
const uint32_t ABRM_DEVICE_CAPABILITY_ADDR          = 0x001C4;
const uint32_t ABRM_MAX_DEVICE_RESPONSE_TIME_ADDR   = 0x001CC;
const uint32_t ABRM_MANIFEST_TABLE_ADDRESS_ADDR     = 0x001D0;
const uint32_t ABRM_SBRM_ADDRESS_ADDR               = 0x001D8;
const uint32_t ABRM_DEVICE_CONFIGURATION_ADDR       = 0x001E0;
const uint32_t ABRM_HEARTBEAT_TIMEOUT_ADDR          = 0x001E8;
const uint32_t ABRM_MESSAGE_CHANNEL_ID_ADDR         = 0x001EC;
const uint32_t ABRM_TIMESTAMP_ADDR                  = 0x001F0;
const uint32_t ABRM_TIMESTAMP_LATCH_ADDR            = 0x001F8;
const uint32_t ABRM_TIMESTAMP_INCREMENT_ADDR        = 0x001FC;
const uint32_t ABRM_ACCESS_PRIVILEGE_ADDR           = 0x00204;
const uint32_t ABRM_PROTOCOL_ENDIANESS_ADDR         = 0x00208;
const uint32_t ABRM_IMPLEMENTATION_ENDIANESS_ADDR   = 0x0020C;
const uint32_t ABRM_RESERVED_ADDR                   = 0x00210;
 
// ABRM Device Capability register flags
#define GENCP_USER_DEFINED_NAME (1 << 0)
#define GENCP_ACCESS_PRIVILEGE  (1 << 1)
#define GENCP_MESSAGE_CHANNEL (1 << 2)
#define GENCP_TIMESTAMP (1 << 3)
#define GENCP_STRING_ENCODING_ASCII (0 << 4)
#define GENCP_STRING_ENCODING_UTF8 (1 << 4)
#define GENCP_STRING_ENCODING_UTF16 (2 << 4)
#define GENCP_FAMILY_NAME (1 << 8)
#define GENCP_SBRM_SUPPORT (1 << 9)
#define GENCP_ENDIANESS_REGISTER (1 << 10)
#define GENCP_WRITTEN_LENGTH_FIELD (1 << 11)
#define GENCP_MULTIEVENT (1 << 12)
 
const uint64_t U3V_DEVICE_CAPABILITY = GENCP_ENDIANESS_REGISTER | GENCP_USER_DEFINED_NAME | GENCP_FAMILY_NAME | GENCP_TIMESTAMP | GENCP_STRING_ENCODING_ASCII | GENCP_SBRM_SUPPORT | GENCP_WRITTEN_LENGTH_FIELD;
 
// ABRM Device Configuration register flags
#define GENCP_CONFIG_HEARTBEAT_ENABLE   (1 << 0)
#define GENCP_CONFIG_MULTIEVENT_ENABLE  (1 << 1)
const uint64_t U3V_DEVICE_CONFIGURATION = 0;
 
// SBRM Addresses
#define SBRM_TABLE_ADDR     (0x10000)
 
// U3V SBRM
const uint32_t U3V_VERSION_ADDR             = SBRM_TABLE_ADDR;
const uint32_t U3V_CP_CABABILITY_ADDR       = SBRM_TABLE_ADDR + 0x04;
const uint32_t U3V_CP_CONFIGURATION_ADDR    = SBRM_TABLE_ADDR + 0x0C;
const uint32_t U3V_MAX_COMMAND_TRANS_ADDR   = SBRM_TABLE_ADDR + 0x14;
const uint32_t U3V_MAX_ACK_TRANS_ADDR       = SBRM_TABLE_ADDR + 0x18;
const uint32_t U3V_NB_STRTEAM_ADDR          = SBRM_TABLE_ADDR + 0x1C;
const uint32_t U3V_SIRM_ADDRESS_ADDR        = SBRM_TABLE_ADDR + 0x20;
const uint32_t U3V_SIRM_LENGTH_ADDR         = SBRM_TABLE_ADDR + 0x28;
const uint32_t U3V_EIRM_ADDRESS_ADDR        = SBRM_TABLE_ADDR + 0x2C;
const uint32_t U3V_EIRM_LENGTH_ADDR         = SBRM_TABLE_ADDR + 0x34;
const uint32_t U3V_IIDC2_ADDRESS_ADDR       = SBRM_TABLE_ADDR + 0x38;
const uint32_t U3V_CURRENT_SPEED_ADDR       = SBRM_TABLE_ADDR + 0x40;
 
// U3V Control Protocol Capability Register
#define U3V_SIRM_AVAILABLE (1 << 0)
#define U3V_EIRM_AVAILABLE (1 << 1)
#define U3V_IIDC2_AVAILABLE (1 << 2)
 
// U3V SBRM Flags/Defaults
#define U3V_CMD_EP_BUFF_SIZE        (1020)      /* Smaller buffer so that the FX3 doesn't get into an error state with something too large for it */
/* WORKAROUND: GenTL CMDs that are 1024 in size caused the FX3 to get into an error state. 
 * Instead of fixing the FX3 code, we are just going to use a smaller buffer size.
 * This bug was triggered by doing a LUTValueAll load file using the HWK1411.
 * 
 * GenTL Violation: Per the spec, U3V_MAX_CMD_LEN/U3V_MAX_ACK_LEN has to be >= to the endpoint max packet size.  We are violating that with this change
 */
 
const uint32_t U3V_VERSION = 0x00010001;
const uint64_t U3V_CP_CAPABILITY = U3V_SIRM_AVAILABLE;
const uint64_t U3V_CP_CONFIGURATION = 0; // No configuration in the standard
const uint32_t U3V_MAX_CMD_LEN = U3V_CMD_EP_BUFF_SIZE;
const uint32_t U3V_MAX_ACK_LEN = U3V_CMD_EP_BUFF_SIZE;
const uint32_t U3V_NB_STREAMS = 1;
 
// SIRM Table.
const uint32_t U3V_SIRM_LENGTH = 0x30;
#define U3V_MAX_HEADER          (52)                    /* Maximum number of bytes in USB3V packet header */
#define U3V_MAX_FOOTER          (32)                    /* Maximum number of bytes in USB3V packet footer */
 
const uint32_t U3V_SIRM_TABLE_ADDR = 0x20000;
const uint32_t U3V_SIRM_INFO_ADDR = U3V_SIRM_TABLE_ADDR;
const uint32_t U3V_SIRM_CTRL_ADDR = U3V_SIRM_TABLE_ADDR + 0x04;
const uint32_t U3V_REQ_PAYLOAD_SIZE_ADDR = U3V_SIRM_TABLE_ADDR + 0x08;
const uint32_t U3V_REQ_LEADER_SIZE_ADDR = U3V_SIRM_TABLE_ADDR + 0x10;
const uint32_t U3V_REQ_TRAILER_SIZE_ADDR = U3V_SIRM_TABLE_ADDR + 0x14;
const uint32_t U3V_MAX_LEADER_ADDR = U3V_SIRM_TABLE_ADDR + 0x18;
const uint32_t U3V_PAYLOAD_SIZE_ADDR = U3V_SIRM_TABLE_ADDR + 0x1C;
const uint32_t U3V_PAYLOAD_COUNT_ADDR = U3V_SIRM_TABLE_ADDR + 0x20;
const uint32_t U3V_PAYLOAD_FINAL1_ADDR = U3V_SIRM_TABLE_ADDR + 0x24;
const uint32_t U3V_PAYLOAD_FINAL2_ADDR = U3V_SIRM_TABLE_ADDR + 0x28;
const uint32_t U3V_MAX_TRAILER_SIZE_ADDR = U3V_SIRM_TABLE_ADDR + 0x2C;
 
// Misc GenCP Flags
#define GENCP_LITTLE_ENDIAN     (0xFFFFFFFF)
 
//===================================================
// Manufacturer Specific Registers
//===================================================
#define XML_REGS_OFFSET (0x30000)
 
// Reference: GenICamSharedRegs.h
const uint32_t DEVICE_FIRMWARE_VERSION_ADDR = XML_REGS_OFFSET + 0x0000'2000;
const uint32_t DEVICE_RESET_ADDR            = XML_REGS_OFFSET + 0x0000'2100;
 
const uint32_t DEVICE_FPGA_VERSION_ADDR     = XML_REGS_OFFSET + 0x0000'3000;
const uint32_t DEVICE_SOFTWARE_DATE_ADDR    = XML_REGS_OFFSET + 0x0000'3008;
const uint32_t DEVICE_FX3_DATE_ADDR         = XML_REGS_OFFSET + 0x0000'3048;
 
const uint32_t AQUISITION_FRAMERATE_ADDR    = XML_REGS_OFFSET + 0x0000'A000;  
const uint32_t EXPOSURE_TIME_ADDR           = XML_REGS_OFFSET + 0x0000'A004;  //!< SFNC 5.7.4 ExposureTime - This register sets the Exposure time (uS).
const uint32_t ROI_WIDTH_ADDR               = XML_REGS_OFFSET + 0x0000'A008;  
const uint32_t ROI_HEIGHT_ADDR              = XML_REGS_OFFSET + 0x0000'A00C;  //!< SFNC 4.19 Height - This register sets the height of the ROI
const uint32_t ROI_OFFSET_X_ADDR            = XML_REGS_OFFSET + 0x0000'A010;  
const uint32_t ROI_OFFSET_Y_ADDR            = XML_REGS_OFFSET + 0x0000'A014;  //!< SFNC 4.21 OffsetY - This register stores the starting row of the ROI
const uint32_t ACQUISITION_START_ADDR       = XML_REGS_OFFSET + 0x0000'A018;  
const uint32_t ACQUISITION_MODE_ADDR        = XML_REGS_OFFSET + 0x0000'A01C;  //!< SFNC 5.5.2 AcquisitionMode - Controls acquisition mode.
const uint32_t PIXEL_FORMAT_ADDR            = XML_REGS_OFFSET + 0x0000'A020;  
const uint32_t PAYLOAD_SIZE_ADDR            = XML_REGS_OFFSET + 0x0000'A024;  //!< SFNC 25.2.5 PayloadSize - Size of frame without headers
const uint32_t BINNING_HORIZONTAL_ADDR      = XML_REGS_OFFSET + 0x0000'A028;  
const uint32_t BINNING_VERTICAL_ADDR        = XML_REGS_OFFSET + 0x0000'A02C;  //!< SFNC 4.28 BinningVertical - Number of pixels to bin in the vertical direction
const uint32_t REVERSE_X_ADDR               = XML_REGS_OFFSET + 0x0000'A030;  
const uint32_t REVERSE_Y_ADDR               = XML_REGS_OFFSET + 0x0000'A034;  //!< SFNC 4.34 ReverseY - "Bool" that flips Y when true
const uint32_t ACQUISITION_NUM_FRAMES_ADDR  = XML_REGS_OFFSET + 0x0000'A038;  
const uint32_t ACQUISITION_STOP_ADDR        = XML_REGS_OFFSET + 0x0000'A03C;  //!< SFNC 5.5.4 AquisitionStop - Start/stop image acquisition using the specified acquision mode in the Acquisition Mode register
const uint32_t DECIMATION_VERTICAL_ADDR     = XML_REGS_OFFSET + 0x0000'A040;  
 
const uint32_t SENSOR_TEMPERATURE_ADDR      = XML_REGS_OFFSET + 0x0000'A044;  //<! Sensor temperature (legacy address)
const uint32_t BOARD_TEMPERATURE_ADDR       = XML_REGS_OFFSET + 0x0000'A048;  //<! Board temperature (legacy address)
const uint32_t EDGE_DETECTION_ADDR          = XML_REGS_OFFSET + 0x0000'A04C;  //<! Enable or disable edge detection.
const uint32_t SHUTTER_MODE_ADDR            = XML_REGS_OFFSET + 0x0000'A050;  //<! SFNC 4.2 SensorShutterMode - Set the shutter mode.
const uint32_t SENSOR_GAINMODE_ADDR         = XML_REGS_OFFSET + 0x0000'A054;  //<!
const uint32_t SENSOR_CALIBRATE_ADDR        = XML_REGS_OFFSET + 0x0000'A058;  //<!
 
const uint32_t TEST_PATTERN_ADDR            = XML_REGS_OFFSET + 0x0000'A05C;  //<! SFNC 4.44 TestPattern - Set the test pattern.
const uint32_t CLOCK_SPEED_ADDR             = XML_REGS_OFFSET + 0x0000'A060;  //<! Set the clock speed to the sensor.
 
const uint32_t SQRT_COMPRESS_ADDR           = XML_REGS_OFFSET + 0x0000'A064;  //<! Set the enable/disable of square root compression
 
const uint32_t HOT_PIXEL_CORRECT_ADDR       = XML_REGS_OFFSET + 0x0000'A068;  //<! Set the hot pixel correction mode.
 
const uint32_t BAD_PIXEL_CTRL_ADDR          = XML_REGS_OFFSET + 0x0000'A070;  //<! Set the enable/disable of the bad pixel correction map
const uint32_t BAD_PIXEL_CTRL_MAP_ADDR      = XML_REGS_OFFSET + 0x0000'A074;  
 
const uint32_t VOLTAGE_SENSOR_SELECT_ADDR   = XML_REGS_OFFSET + 0x0000'A078;  //!< Selects which ADC / voltage sensor to read back
const uint32_t VOLTAGE_SENSOR_VALUE_ADDR    = XML_REGS_OFFSET + 0x0000'A07C;  
 
const uint32_t DEVICE_TEMPERATURE_SELECT_ADDR= XML_REGS_OFFSET + 0x0000'A080;  //!< SFNC 3.60 DeviceTemperatureSelector
const uint32_t DEVICE_TEMPERATURE_ADDR       = XML_REGS_OFFSET + 0x0000'A084;  
 
const uint32_t EXPOSURE_TIME_SELECT_ADDR     = XML_REGS_OFFSET + 0x0000'A08C;  //!< SFNC 5.7.3 ExposureTimeSelector - This optional register allows selecting different exposure times (see SFNC).
 
const uint32_t SENSOR_WIDTH_ADDR             = XML_REGS_OFFSET + 0x0000'A090;  
const uint32_t SENSOR_HEIGHT_ADDR            = XML_REGS_OFFSET + 0x0000'A094;  //!< SFNC 4.3 SensorHeight - Effective height of sensor in pixels
 
const uint32_t FREE_RAM_CFG_ADDR            = XML_REGS_OFFSET + 0x0000'A100;  //<! Free RAM the system can support (for XML to use in calculations rather than being coded there and in ram_cfg.ini)
 
const uint32_t INTERNAL_EXP_MODE_ADDR       = XML_REGS_OFFSET + 0x0000'A200;  //<! External exposure mode control.
 
// LUT Control SFNC 7.x
const uint32_t LUT_SELECTOR_ADDR            = XML_REGS_OFFSET + 0x0000'A300;  //<! SFNC LUTSelector
const uint32_t LUT_ENABLE_ADDR              = XML_REGS_OFFSET + 0x0000'A304;  //<! SFNC LUTEnable
const uint32_t LUT_MAXINDEX_ADDR            = XML_REGS_OFFSET + 0x0000'A308;  //<! Custom LUTMaxIndex - Maximum index of LUT in bytes
const uint32_t LUT_INDEX_ADDR               = XML_REGS_OFFSET + 0x0000'A30C;  //<! SFNC LUTIndex
const uint32_t LUT_MAXVALUE_ADDR            = XML_REGS_OFFSET + 0x0000'A310;  //<! Custom LUTMaxValue - Maximum value to store in LUT
const uint32_t LUT_VALUE_ADDR               = XML_REGS_OFFSET + 0x0000'A314;  //<! SFNC LUTValue
// const uint32_t LUT_VALUEALL_ADDR             = XML_REGS_OFFSET + TODO;  //<! SFNC LUTValueAll - WIP: How does this work?
 
namespace LUTSelector {
    enum eeLUTSelected {
        eeLuminance = 0,
        eeRed = 1,
        eeGreen = 2,
        eeBlue = 3,
        eeDeviceSpecific = 10,
    };
}
 
// Analog Control SFNC 6.x
const uint32_t GAIN_SELECTOR_ADDR           = XML_REGS_OFFSET + 0x0000'A400;  //<! SFNC 6.2 GainSelector
const uint32_t GAIN_ADDR                    = XML_REGS_OFFSET + 0x0000'A404;  //<! SFNC 6.3 Gain[GainSelector]
const uint32_t GAIN_AUTO_ADDR               = XML_REGS_OFFSET + 0x0000'A408;  //<! SFNC 6.4 GainAuto[GainSelector] WIP
const uint32_t GAIN_AUTOBALANCE_ADDR        = XML_REGS_OFFSET + 0x0000'A40C;  //<! SFNC 6.5 GainAutoBalance WIP
const uint32_t BLACK_LEVEL_SELECTOR_ADDR    = XML_REGS_OFFSET + 0x0000'A410;  //<! SFNC 6.6 BlackLevelSelector
const uint32_t BLACK_LEVEL_ADDR             = XML_REGS_OFFSET + 0x0000'A414;  //<! SFNC 6.7 BlackLevel[BlackLevelSelector]
const uint32_t BLACK_LEVEL_AUTO_ADDR        = XML_REGS_OFFSET + 0x0000'A418;  //<! SFNC 6.9 BlackLevelAuto[BlackLevelSelector]
const uint32_t BLACK_LEVEL_AUTOBALANCE_ADDR = XML_REGS_OFFSET + 0x0000'A41C;  //<! SFNC 6.9 BlackLevelAutoBalance WIP
const uint32_t WHITE_CLIP_SELECTOR_ADDR     = XML_REGS_OFFSET + 0x0000'A420;  //<! SFNC 6.10 WhiteClipSelector WIP
const uint32_t WHITE_CLIP_ADDR              = XML_REGS_OFFSET + 0x0000'A424;  //<! SFNC 6.11 WhiteClip[WhiteClipSelector] WIP
const uint32_t BALANCE_RATIO_SELECTOR_ADDR  = XML_REGS_OFFSET + 0x0000'A428;  //<! SFNC 6.12 BalanceRatioSelector WIP
const uint32_t BALANCE_RATIO_ADDR           = XML_REGS_OFFSET + 0x0000'A42C;  //<! SFNC 6.13 BalanceRatio[BalanceRatioSelector] WIP
const uint32_t BALANCE_WHITE_AUTO_ADDR      = XML_REGS_OFFSET + 0x0000'A430;  //<! SFNC 6.14 BalanceWhiteAuto WIP
const uint32_t GAMMA_ADDR                   = XML_REGS_OFFSET + 0x0000'A434;  //<! SFNC 6.15 Gamma WIP
const uint32_t BLACK_LEVEL_BIAS_ADDR        = XML_REGS_OFFSET + 0x0000'A440;  //<! Bias to add after black level is subtracted
 
namespace AnalogControl {
    enum eeAnalogSelected {
        eeAll           = 0,
        eeRed           = 1,
        eeGreen         = 2,
        eeBlue          = 3,
        eeY             = 4,
        eeU             = 5,
        eeV             = 6,
        eeAnalogAll     = 10,
        eeAnalogRed     = 11,
        eeAnalogGreen   = 12,
        eeAnalogBlue    = 13,
        eeAnalogY       = 14,
        eeAnalogU       = 15,
        eeAnalogV       = 16,
        eeDigitalAll    = 20,
        eeDigitalRed    = 21,
        eeDigitalGreen  = 22,
        eeDigitalBlue   = 23,
        eeDigitalY      = 24,
        eeDigitalU      = 25,
        eeDigitalV      = 26,
    };
    enum eeAnalogAuto {
        eeOff           = 0,
        eeOnce          = 1,
        eeContinuous    = 2,
        eeDeviceSpecific = 10,
    };
}
 
// Color Transformation SFNC 8.x
const uint32_t COLOR_TRANSF_SELECTOR_ADDR       = XML_REGS_OFFSET + 0x0000'A500;  //<! SFNC 8.2 ColorTransformationSelector
const uint32_t COLOR_TRANSF_ENABLE_ADDR         = XML_REGS_OFFSET + 0x0000'A504;  //<! SFNC 8.3 ColorTransformationEnable[ColorTransformationSelector]
const uint32_t COLOR_TRANSF_VALUE_SELECTOR_ADDR = XML_REGS_OFFSET + 0x0000'A508;  //<! SFNC 8.4 ColorTransformationValueSelector[ColorTransformationSelector]
const uint32_t COLOR_TRANSF_VALUE_ADDR          = XML_REGS_OFFSET + 0x0000'A50C;  //<! SFNC 8.5 ColorTransformationValue[ColorTransformationSelector][ColorTransformationValueSelector]
 
namespace ColorTransf {
    enum eeColorTransfSelected {
        eeRGBtoRGB = 0,
        eeRGBtoYUV = 1,
        eeDeviceSpecific = 10,
    };
    enum eeColorTransfValueSelected {
        eeGain00    = 0,
        eeGain01    = 1,
        eeGain02    = 2,
        eeGain10    = 3,
        eeGain11    = 4,
        eeGain12    = 5,
        eeGain20    = 6,
        eeGain21    = 7,
        eeGain22    = 8,
        eeOffset0   = 9,
        eeOffset1   = 10,
        eeOffset2   = 11,
    };
}
 
// Trigger Control SFNC 5.6.x
const uint32_t TRIGGER_SELECTOR_ADDR        = XML_REGS_OFFSET + 0x0000'B000;  //<! SFNC TriggerSelector - Trigger selector (basically a mux for the registers that follow it)
const uint32_t TRIGGER_MODE_ADDR            = XML_REGS_OFFSET + 0x0000'B004;  //<! SFNC TriggerMode - Enable/disable for the trigger chosen by selector
const uint32_t TRIGGER_SOURCE_ADDR          = XML_REGS_OFFSET + 0x0000'B008;  //<! SFNC TriggerSource - Source for the trigger chosen by selector
const uint32_t TRIGGER_ACTIVATION_ADDR      = XML_REGS_OFFSET + 0x0000'B00C;  //<! SFNC TriggerActivation - Edge/level selection for the trigger chosen by selector
 
namespace TriggerSelector {
enum eeTriggerSelected {
    eeAcquisitionStart  = 0,
    eeAcquisitionEnd    = 1,
    eeAcquisitionActive = 2,
    eeFrameStart        = 3,
    eeFrameEnd          = 4,
    eeFrameActive       = 5,
    eeFrameBurstStart   = 6,
    eeFrameBurstEnd     = 7,
    eeFrameBurstActive  = 8,
    eeLineStart         = 9,
    eeExposureStart     = 10,
    eeExposureEnd       = 11,
    eeExposureActive    = 12
};
}
namespace TriggerActivation {
enum teTriggerActivation {
    eeRisingEdge  = 0,
    eeFallingEdge = 1,
    eeAnyEdge     = 2,
    eeLevelHigh   = 3,
    eeLevelLow    = 4
};
}
 
// DigitalIOControl SFNC 9.2.x
const uint32_t DIGITAL_IO_LINE_SELECT_ADDR  = XML_REGS_OFFSET + 0x0000'B100;  //<! SFNC 9.2.2 LineSelector - Line selector register for Digital IO Control
const uint32_t DIGITAL_IO_LINE_MODE_ADDR    = XML_REGS_OFFSET + 0x0000'B104;  //<! SFNC 9.2.3 LineMode
const uint32_t DIGITAL_IO_LINE_SOURCE_ADDR  = XML_REGS_OFFSET + 0x0000'B10C;  //<! SFNC 9.2.7 LineSource
const uint32_t USER_OUTPUT_SELECTOR_ADDR    = XML_REGS_OFFSET + 0x0000'B110;  //<! SFNC 9.2.9 UserOutputSelector
const uint32_t USER_OUTPUT_VALUE_ADDR       = XML_REGS_OFFSET + 0x0000'B114;  //<! SFNC 9.2.10 UserOutputValue
const uint32_t DIGITAL_IO_LINE_STATUS_ADDR  = XML_REGS_OFFSET + 0x0000'B118;  //<! SFNC 9.2.5 LineStatus
const uint32_t DIGITAL_IO_LINE_INVERTER_ADDR = XML_REGS_OFFSET + 0x0000'B11C;  //<! SFNC 9.2.4 LineInverter
 
namespace LineSource {
enum teLineSource {
    eeOff   = 0,
    eeZero  = 1,
    eeOne   = 2,
    eeExposureActive = 5,
    eeUserOutput0  = 22,
    eeUserOutput1  = 23,
    eeFabricInput1 = 32,
    eeFabricInput2 = 33,
    eeFabricInput3 = 34,
    eeFabricInput4 = 35
};
}
 
const uint32_t INDICATOR_CONTROL_ADDR = XML_REGS_OFFSET + 0x0000'B120;  
const uint32_t FAN_CONTROL_ADDR       = XML_REGS_OFFSET + 0x0000'B124;  //!< control for FAN
 
const uint32_t IS_CAMERA_COLOR_ADDR   = XML_REGS_OFFSET + 0x0000'B200;  
 
const uint32_t SENS_REG_ADDR_ADDR           = XML_REGS_OFFSET + 0x0000'C000;  //<! Register address to peek/poke
const uint32_t SENS_VAL_ADDR                = XML_REGS_OFFSET + 0x0000'C004;  //<! Register value from peek or to poke
const uint32_t SENS_READ_ADDR               = XML_REGS_OFFSET + 0x0000'C008;  //<! Register address for the "read" command
const uint32_t SENS_WRITE_ADDR              = XML_REGS_OFFSET + 0x0000'C00C;  //<! Register address for the "write" command
 
const uint32_t SENS_MIN_FRAME_PERIOD_ADDR       = XML_REGS_OFFSET + 0x0000'C020;  //<! Register address for the cameras minimum frame interval in microseconds
 
// Reusable sensor specific registers.  Every camera can use these registers for whatever they need. Registers are int32 unless otherwise mentioned.
const uint32_t SENS_SPECIFIC_1_ADDR         = XML_REGS_OFFSET + 0x0000'D000; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_2_ADDR         = XML_REGS_OFFSET + 0x0000'D004; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_3_ADDR         = XML_REGS_OFFSET + 0x0000'D008; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_4_ADDR         = XML_REGS_OFFSET + 0x0000'D00C; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_5_ADDR         = XML_REGS_OFFSET + 0x0000'D010; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_6_ADDR         = XML_REGS_OFFSET + 0x0000'D014; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_7_ADDR         = XML_REGS_OFFSET + 0x0000'D018; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_8_ADDR         = XML_REGS_OFFSET + 0x0000'D01C; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_9_ADDR         = XML_REGS_OFFSET + 0x0000'D020; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_10_ADDR        = XML_REGS_OFFSET + 0x0000'D024; // Sensor specific functionality (string of 64 in size).
const uint32_t SENS_SPECIFIC_11_ADDR        = XML_REGS_OFFSET + 0x0000'D064; // Sensor specific functionality (float).
const uint32_t SENS_SPECIFIC_12_ADDR        = XML_REGS_OFFSET + 0x0000'D068; // Sensor specific functionality (float).
const uint32_t SENS_SPECIFIC_13_ADDR        = XML_REGS_OFFSET + 0x0000'D06C; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_14_ADDR        = XML_REGS_OFFSET + 0x0000'D070; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_15_ADDR        = XML_REGS_OFFSET + 0x0000'D074; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_16_ADDR        = XML_REGS_OFFSET + 0x0000'D078; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_17_ADDR        = XML_REGS_OFFSET + 0x0000'D07C; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_18_ADDR        = XML_REGS_OFFSET + 0x0000'D080; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_19_ADDR        = XML_REGS_OFFSET + 0x0000'D084; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_20_ADDR        = XML_REGS_OFFSET + 0x0000'D088; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_21_ADDR        = XML_REGS_OFFSET + 0x0000'D08C; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_22_ADDR        = XML_REGS_OFFSET + 0x0000'D090; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_23_ADDR        = XML_REGS_OFFSET + 0x0000'D094; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_24_ADDR        = XML_REGS_OFFSET + 0x0000'D098; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_25_ADDR        = XML_REGS_OFFSET + 0x0000'D09C; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_26_ADDR        = XML_REGS_OFFSET + 0x0000'D0A0; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_27_ADDR        = XML_REGS_OFFSET + 0x0000'D0A4; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_28_ADDR        = XML_REGS_OFFSET + 0x0000'D0A8; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_29_ADDR        = XML_REGS_OFFSET + 0x0000'D0AC; // Sensor specific functionality.
const uint32_t SENS_SPECIFIC_30_ADDR        = XML_REGS_OFFSET + 0x0000'D0B0; // Sensor specific functionality.
 
const uint32_t SENS_SPECIFIC_FLOAT_1_ADDR   = XML_REGS_OFFSET + 0x0000'D100; // Sensor specific functionality (float).
const uint32_t SENS_SPECIFIC_FLOAT_2_ADDR   = XML_REGS_OFFSET + 0x0000'D104; // Sensor specific functionality (float).
const uint32_t SENS_SPECIFIC_FLOAT_3_ADDR   = XML_REGS_OFFSET + 0x0000'D108; // Sensor specific functionality (float).
const uint32_t SENS_SPECIFIC_FLOAT_4_ADDR   = XML_REGS_OFFSET + 0x0000'D10c; // Sensor specific functionality (float).
const uint32_t SENS_SPECIFIC_FLOAT_5_ADDR   = XML_REGS_OFFSET + 0x0000'D110; // Sensor specific functionality (float).
 
const uint32_t SENS_PEEKPOKE_ADDR           = XML_REGS_OFFSET + 0x0020'0000;  //<! Arbitrary PEEK register; all addresses above this are translated into a peek address.
const uint32_t SENS_PEEKPOKE_ADDR_END       = XML_REGS_OFFSET + 0x0023'FFFF;  //<! End of poke-able registers.
 
//===================================================
// XML File Registers
//===================================================
const uint32_t XML_FILE_ADDR                = XML_REGS_OFFSET + 0x0001'4000; //!< This is where the XML file is loaded into memory
 
//===================================================
// Debug Buffer Registers
//  Dynamically registered by GenICamStatusReporter
//===================================================
const uint32_t DEBUG_BUFFER_BYTESWRITTEN_ADDR = 0x0030'0000;
const uint32_t DEBUG_BUFFER_ADDR              = 0x0030'1000;
 
 
// Set these addresses correctly.
const uint32_t MANIFEST_TABLE_COUNT_ADDR = MANIFEST_TABLE_ADDR;
const uint32_t MANIFEST_VER_ADDR = MANIFEST_TABLE_ADDR + 0x08;
const uint32_t MANIFEST_TYPE_ADDR = MANIFEST_VER_ADDR + 0x04;
const uint32_t MANIFEST_REG_ADDR = MANIFEST_TYPE_ADDR + 0x04;
const uint32_t MANIFEST_FILE_SIZE_ADDR = MANIFEST_REG_ADDR + 0x08;
const uint32_t MANIFEST_SHA1_ADDR = MANIFEST_FILE_SIZE_ADDR + 0x08;
 
//===================================================
// Beyond Manifest
// TODO What does this mean?
//===================================================
const uint32_t BEYOND_MANIFEST_ADDR = 0x20000000;
const uint32_t TEST_PENDING_ACK_ADDR = BEYOND_MANIFEST_ADDR;
 
const uint32_t HDMI_START_ADDR      = BEYOND_MANIFEST_ADDR + 0x04;
const uint32_t HDMI_STOP_ADDR       = BEYOND_MANIFEST_ADDR + 0x08;
const uint32_t HDMI_OFFSET_X_ADDR   = BEYOND_MANIFEST_ADDR + 0x0c;
const uint32_t HDMI_OFFSET_Y_ADDR   = BEYOND_MANIFEST_ADDR + 0x10;
const uint32_t HDMI_WIDTH_ADDR      = BEYOND_MANIFEST_ADDR + 0x14;
const uint32_t HDMI_HEIGHT_ADDR     = BEYOND_MANIFEST_ADDR + 0x18;
const uint32_t HDMI_OUTPUT_SEL_ADDR = BEYOND_MANIFEST_ADDR + 0x1c;
// const uint32_t HDMI_COLOR_SEL_ADDR  = BEYOND_MANIFEST_ADDR + 0x20;  This is deprecated
const uint32_t HDMI_GAMMA_ADDR      = BEYOND_MANIFEST_ADDR + 0x24;
const uint32_t HDMI_WBRED_ADDR      = BEYOND_MANIFEST_ADDR + 0x28;
const uint32_t HDMI_WBGREEN_ADDR    = BEYOND_MANIFEST_ADDR + 0x2C;
const uint32_t HDMI_WBBLUE_ADDR     = BEYOND_MANIFEST_ADDR + 0x30;
const uint32_t HDMI_TESTPATEN_ADDR  = BEYOND_MANIFEST_ADDR + 0x34;
const uint32_t HDMI_BPP_ADDR        = BEYOND_MANIFEST_ADDR + 0x38;
 
 
//===================================================
// REGISTER FLAG BIT DEFINITIONS
//===================================================
 
 
//{
const uint32_t GIGE_VERSION_1_2     = 0x00010002;   //<! GigE version 1.2 (Not used just for reference)
const uint32_t GIGE_VERSION_2_0     = 0x00020000;   //<! GigE version 2.0 (We use this one)
//}
 
//{
const uint32_t PIXEL_FORMAT_MONO16  = 0x01100007;   //<! 16 bit mono
const uint32_t PIXEL_FORMAT_MONO8   = 0x01080001;   //<! 8 bit mono
const uint32_t PIXEL_FORMAT_MONO12  = 0x01100005;   //<! 12 bit mono
const uint32_t PIXEL_FORMAT_MONO12P  = 0x010C0047;   //<! 12 bit mono packed
const uint32_t PIXEL_FORMAT_MONO12PACKED  = 0x010C0007;   //<! 12 bit mono packed
 
const uint32_t PIXEL_FORMAT_BAYERGR8 = 0x01080008;
const uint32_t PIXEL_FORMAT_BAYERRG8 = 0x01080009;
const uint32_t PIXEL_FORMAT_BAYERGB8 = 0x0108000A;
const uint32_t PIXEL_FORMAT_BAYERBG8 = 0x0108000B;
 
const uint32_t PIXEL_FORMAT_BAYERGR16 = 0x0110002E;
const uint32_t PIXEL_FORMAT_BAYERRG16 = 0x0110002F;
const uint32_t PIXEL_FORMAT_BAYERGB16 = 0x01100030;
const uint32_t PIXEL_FORMAT_BAYERBG16 = 0x01100031;
 
const uint32_t PIXEL_FORMAT_BAYERBG12P = 0x010C0053;
const uint32_t PIXEL_FORMAT_BAYERGB12P = 0x010C0055;
const uint32_t PIXEL_FORMAT_BAYERGR12P = 0x010C0057;
const uint32_t PIXEL_FORMAT_BAYERRG12P = 0x010C0059;
 
const uint32_t PIXEL_FORMAT_BAYERGR12PACKED = 0x010C002A;
const uint32_t PIXEL_FORMAT_BAYERRG12PACKED = 0x010C002B;
const uint32_t PIXEL_FORMAT_BAYERGB12PACKED = 0x010C002C;
const uint32_t PIXEL_FORMAT_BAYERBG12PACKED = 0x010C002D;
 
/* 32-bit value layout */
/* |31            24|23            16|15            08|07            00| */
/* | C| Comp. Layout| Effective Size |            Pixel ID             | */
 
/* Custom flag */
#define PFNC_CUSTOM                              0x80000000
/* Component layout */
#define PFNC_SINGLE_COMPONENT                    0x01000000
#define PFNC_MULTIPLE_COMPONENT                  0x02000000
#define PFNC_COMPONENT_MASK                      0x7F000000
/* Effective size */
#define PFNC_OCCUPY1BIT                          0x00010000
#define PFNC_OCCUPY2BIT                          0x00020000
#define PFNC_OCCUPY4BIT                          0x00040000
#define PFNC_OCCUPY8BIT                          0x00080000
#define PFNC_OCCUPY10BIT                         0x000A0000
#define PFNC_OCCUPY12BIT                         0x000C0000
#define PFNC_OCCUPY16BIT                         0x00100000
#define PFNC_OCCUPY24BIT                         0x00180000
#define PFNC_OCCUPY30BIT                         0x001E0000
#define PFNC_OCCUPY32BIT                         0x00200000
#define PFNC_OCCUPY36BIT                         0x00240000
#define PFNC_OCCUPY40BIT                         0x00280000
#define PFNC_OCCUPY48BIT                         0x00300000
#define PFNC_OCCUPY64BIT                         0x00400000
#define PFNC_PIXEL_SIZE_MASK                     0x00FF0000
#define PFNC_PIXEL_SIZE_SHIFT                    16
/* Pixel ID */
#define PFNC_PIXEL_ID_MASK                       0x0000FFFF
/* Pixel format value dissection helpers */
#define PFNC_PIXEL_SIZE(X)                       ((X & PFNC_PIXEL_SIZE_MASK) >> PFNC_PIXEL_SIZE_SHIFT)
#define PFNC_IS_PIXEL_SINGLE_COMPONENT(X)        ((X & PFNC_COMPONENT_MASK) == PFNC_SINGLE_COMPONENT)
#define PFNC_IS_PIXEL_MULTIPLE_COMPONENT(X)      ((X & PFNC_COMPONENT_MASK) == PFNC_MULTIPLE_COMPONENT)
#define PFNC_IS_PIXEL_CUSTOM(X)                  ((X & PFNC_CUSTOM) == PFNC_CUSTOM)
#define PFNC_PIXEL_ID(X)                         (X & PFNC_PIXEL_ID_MASK)
 
//}
 
//{
const uint32_t PRIVILEGE_EXCLUSIVE  = 0x00000001;  //!< Exclusive control privilege (read-write)
const uint32_t PRIVILEGE_CONTROL    = 0x00000002;  //!< Control privilege (read-write)
//}
 
//{
const uint32_t GVCP_CAP_UN          = 0x80000000;   //<! Device has a user defined name register [O-442cd].
const uint32_t GVCP_CAP_SN          = 0x40000000;   //<! Device has a serial number register [O-441cd].
const uint32_t GVCP_CAP_HD          = 0x20000000;   //<! Heart beat can be disabled.
const uint32_t GVCP_CAP_LS          = 0x10000000;   //<! Device has link speed registers.
const uint32_t GVCP_CAP_CAP         = 0x08000000;   //<! CCP Application Port and IP address registers are supported.
const uint32_t GVCP_CAP_MT          = 0x04000000;   //<! Manifest Table is supported.
const uint32_t GVCP_CAP_TD          = 0x02000000;   //<! Test packet is filled with data from the LFSR generator.
const uint32_t GVCP_CAP_DD          = 0x01000000;   //<! Device has discovery ack delay registers [O-468cd].
const uint32_t GVCP_CAP_WD          = 0x00800000;   //<! When Discovery ACK Delay register is supported, this bit indicates that the register is writable.
const uint32_t GVCP_CAP_ES          = 0x00400000;   //<! Support generation of extended status codes introduces in specification 1.1.
const uint32_t GVCP_CAP_PAS         = 0x00200000;   //<! Primary application switchover capability is supported.
const uint32_t GVCP_CAP_UA          = 0x00100000;   //<! Unconditional ACTION_CMD is supported.
const uint32_t GVCP_CAP_PTP         = 0x00080000;   //<! Support for IEEE 1588 PTP.
const uint32_t GVCP_CAP_ES2         = 0x00040000;   //<! Support generation of extended status codes introduces in specification 2.0.
const uint32_t GVCP_CAP_SAC         = 0x00020000;   //<! Scheduled Action Commands are supported.
const uint32_t GVCP_CAP_A           = 0x00000040;   //<! ACTION_CMD and ACTION_ACK are supported.
const uint32_t GVCP_CAP_PA          = 0x00000020;   //<! PENDING_ACK is supported.
const uint32_t GVCP_CAP_ED          = 0x00000010;   //<! EVENTDATA_CMD and EVENTDATA_ACK are supported.
const uint32_t GVCP_CAP_E           = 0x00000008;   //<! EVENT_CMD and EVENT_ACK are supported.
const uint32_t GVCP_CAP_PR          = 0x00000004;   //<! PACKETRESEND_CMD is supported.
const uint32_t GVCP_CAP_W           = 0x00000002;   //<! WRITEMEM_CMD and WRITEMEM_ACK are supported.
const uint32_t GVCP_CAP_C           = 0x00000001;   //<! Multiple operations in a single message are supported.
const uint32_t GVCP_CAP_VALUE       = GVCP_CAP_UN | GVCP_CAP_SN | GVCP_CAP_CAP | GVCP_CAP_W | GVCP_CAP_PR;
 
//{
const uint32_t GVsP_CAP_SP          = 0x80000000;   //<! Indicates the SCSPx registers (stream channel source port) are available for all supported stream channels.
const uint32_t GVsP_CAP_LB          = 0x40000000;   //<! Indicates this GVSP transmitter or receiver can support 16-bit block_id.
const uint32_t GVsP_CAP_VALUE       = GVsP_CAP_SP | GVsP_CAP_LB;
 
//{
const uint32_t GVsP_CFG_BL          = 0x40000000;   //<! Enable the 64-bit block_id64 for GVSP.
 
//{
const uint32_t PHY_CAP_DLAG         = 0x00000008;   //!< This device supports dynamic link aggregation configuration.
const uint32_t PHY_CAP_SLAG         = 0x00000004;   //!< This device supports static link aggregation configuration.
const uint32_t PHY_CAP_ML           = 0x00000002;   //!< This device supports multiple link (ML) configuration.
const uint32_t PHY_CAP_SL           = 0x00000001;   //!< This device supports single link (SL) configuration.
//}
 
//{
const uint32_t PHY_CONFIG_DLAG      = 3;            //!< Dynamic link aggregation configuration.
const uint32_t PHY_CONFIG_SLAG      = 2;            //!< Static link aggregation configuration.
const uint32_t PHY_CONFIG_ML        = 1;            //!< Multiple link (ML) configuration.
const uint32_t PHY_CONFIG_SL        = 0;            //!< Single link (SL) configuration.
//}
 
//{
const uint32_t DEVMODE_BIGENDIAN    = 0x80000000;   //<! Big Endian (required).
const uint32_t DEVMODE_ASCII        = 0x00000002;   //<! ASCII Character set.
const uint32_t DEVMODE_UTF8         = 0x00000001;   //<! UTF-8 Character set.
//}
 
//{
const uint32_t SHUTTERMODE_ROLLING  = 0x00000000;   //<! Rolling shutter mode.
const uint32_t SHUTTERMODE_GLOBAL   = 0x00000001;   //<! Global shutter mode.
//}
 
//{
const uint32_t NET_IFACE_C_PR       = 0x80000000;   //<! Pause Reception (we don't use this).
const uint32_t NET_IFACE_C_PG       = 0x40000000;   //<! Pause Generation (we don't use this).
const uint32_t NET_IFACE_C_L        = 0x00000004;   //<! Link-local address is activated. Always 1.
const uint32_t NET_IFACE_C_D        = 0x00000002;   //<! DHCP is activated on this interface. Factory default is 1.
const uint32_t NET_IFACE_C_P        = 0x00000001;   //<! Persistent IP is activated on this interface. Factory default is 0.
const uint32_t NET_IFACE_C_MASK     = NET_IFACE_C_L|NET_IFACE_C_D|NET_IFACE_C_P;
//}
 
//{
const uint32_t SCPS_F               = 0x80000000;   //<! Fire a test packet.
const uint32_t SCPS_D               = 0x40000000;   //<! Do not fragment stream data.
const uint32_t SCPS_P               = 0x20000000;   //<! Pixel endianness (not supported).
const uint32_t SCPS_PKT_SIZE_MASK   = 0x0000FFFF;   //<! Bits to mask off the packet size portion of the message.
const uint32_t SCPS_MASK            = SCPS_F|SCPS_D|SCPS_PKT_SIZE_MASK;
//}
 
//{
const uint32_t SC_CAP_BE           = 0x80000000;   //<! Indicates this stream channel supports both big and little-endian.
const uint32_t SC_CAP_R            = 0x40000000;   //<! For GVSP receivers, indicates this stream channel supports the reassembly of fragmented IP packets.
const uint32_t SC_CAP_MZ           = 0x00000010;   //<! Multi zone support, 1 indicate this stream channel supports the SCZx and SCZDx
const uint32_t SC_CAP_PRD          = 0x00000008;   //<! Indicates if an alternate destination exists for Packet resend request.
const uint32_t SC_CAP_AIT          = 0x00000004;   //<! For GVSP transmitters, indicates that the stream channel supports the All-in Transmission mode.
const uint32_t SC_CAP_US           = 0x00000002;   //<! For GVSP transmitters, indicates that the stream channel supports unconditional streaming capabilities.
const uint32_t SC_CAP_EC           = 0x00000001;   //<! Indicates that the stream channel supports the deprecated extended chunk data payload type.
const uint32_t SC_CAP_VALUE        = 0;
//}
 
//{
const uint32_t TIMESTAMP_CTRL_L     = 0x00000002;   //<! Latch current time into Timestamp Value registers.
const uint32_t TIMESTAMP_CTRL_R     = 0x00000001;   //<! Reset timestamp 64-bit counter to 0.
//}
 
 
#endif // REGISTERFILE_H