Critical Link MityCam SoC Firmware  1.0
Critical Link MityCam SoC Firmware
GigERegisters.h
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1 /*
2  * GigERegisters.h
3  *
4  * Created on: Oct 3, 2017
5  * Author: mitydsp
6  */
7 
8 #include "GigE.h"
10 
11 #ifndef GIGEREGISTERS_H_
12 #define GIGEREGISTERS_H_
13 
14 namespace GigERegisters {
15 
16 // IMPORTANT: Registers must be in monotonically increasing address order.
17 
23 {
25  REGDEF_INT (DEVICE_MODE , RO, DEVMODE_BIGENDIAN | DEVMODE_UTF8),
26  REGDEF_INT (DEVICE_MAC_HIGH0 , RO, 0),
27  REGDEF_INT (DEVICE_MAC_LOW0 , RO, 0),
28  REGDEF_INT (NET_IFACE_CAPABILITY0 , RO, NET_IFACE_C_L | NET_IFACE_C_D | NET_IFACE_C_P),
29  REGDEF_INT (NET_IFACE_CONFIG0 , RW, NET_IFACE_C_L | NET_IFACE_C_D),
30  REGDEF_INT (CURRENT_IP_ADDR0 , RO, 0),
31  REGDEF_INT (CURRENT_SUBNET0 , RO, 0),
32  REGDEF_INT (CURRENT_GATEWAY0 , RO, 0),
33  REGDEF_STR (MANUFACTURER_NAME , RO, 32 , "Critical Link LLC"),
34  REGDEF_STR (MODEL_NAME , RO, 32 , "CIS1910"),
35  REGDEF_STR (DEVICE_VERSION , RO, 32 , ""),
36  REGDEF_STR (MANUFACTURER_INFO , RO, 48 , ""),
37  REGDEF_STR (SERIAL_NUMBER , RO, 16 , ""),
38  REGDEF_STR (USER_NAME , RW, 16 , ""),
39  REGDEF_STR (FIRST_URL , RO, 512, ""),
40  REGDEF_STR (SECOND_URL , RO, 512, ""),
41  REGDEF_INT (NB_INTERFACES , RO, 1),
42  REGDEF_INT (PERSISTENT_IP_ADDR0 , RW, 0),
43  REGDEF_INT (PERSISTENT_GATEWAY0 , RW, 0),
44  REGDEF_INT (PERSISTENT_SUBNET0 , RW, 0),
45 
46  REGDEF_INT (NB_MSG_CHANNELS , RO, 0),
47  REGDEF_INT (NB_STREAM_CHANNELS , RO, 1),
48  REGDEF_INT (NB_ACTIVE_LINKS , RO, 1), //zzzgaj changes not always 1 can be 0 if no connections.
49  REGDEF_INT (GVSP_CAPABILITY , RO, GVsP_CAP_VALUE),
50  REGDEF_INT (MSG_CAPABILITY , RO, 0),
51  REGDEF_INT (GVCP_CAPABILITY , RO, GVCP_CAP_VALUE),
52  REGDEF_INT (HEARTBEAT_TIMEOUT , RW, 0x00000BB8),
53  REGDEF_INT (TIMESTAMP_FREQ_HIGH , RO, 0),
54  REGDEF_INT (TIMESTAMP_FREQ_LOW , RO, 1000000), // Micro second resolution.
55  REGDEF_INT (TIMESTAMP_CTRL , WO, 0),
56  REGDEF_INT (TIMESTAMP_VALUE_HIGH , RO, 0),
57  REGDEF_INT (TIMESTAMP_VALUE_LOW , RO, 0),
58  REGDEF_INT (PENDING_TIMEOUT , RO, 5000), // I don't really know what this time should be? Don't want it too long or too short.
59  REGDEF_INT (GVSP_CONFIGURATION , RW, 0), // Must start as 0 if we want to say we're GigE 1.x compatible.
60  REGDEF_INT (PHY_CAPABILITY , RO, PHY_CAP_SL),
61  REGDEF_INT (PHY_CONFIG , RO, PHY_CONFIG_SL),
62  REGDEF_INT (CCP , RW, 0x00000000),
63  REGDEF_INT (PA_PORT , RO, 0),
64  REGDEF_INT (PA_IP , RO, 0),
65 
66  REGDEF_INT (SCP0 , RW, 0),
67  REGDEF_INT (SCPS0 , RW, GVSP_DFLT_PKT_SIZE),
68  REGDEF_INT (SCPD0 , RW, 0),
69  REGDEF_INT (SCDA0 , RW, 0),
70  REGDEF_INT (SCSP0 , RO, 0),
71  REGDEF_INT (SCC0 , RO, SC_CAP_VALUE),
72 
73 #include "GenICamSharedRegs.h"
74 
76 };
77 
78 }
79 
80 #endif /* GIGEREGISTERS_H_ */
GigE.h
SC_CAP_VALUE
const uint32_t SC_CAP_VALUE
Definition: RegisterFile.h:1105
GIGE_VERSION_2_0
const uint32_t GIGE_VERSION_2_0
Definition: RegisterFile.h:925
REGDEF_INT
#define REGDEF_INT(name, access, dflt)
Definition: RegisterFile.h:99
DEVMODE_UTF8
const uint32_t DEVMODE_UTF8
Definition: RegisterFile.h:1064
REGDEF_END_OF_TABLE
#define REGDEF_END_OF_TABLE
Definition: RegisterFile.h:103
NET_IFACE_C_L
const uint32_t NET_IFACE_C_L
Definition: RegisterFile.h:1079
NET_IFACE_C_P
const uint32_t NET_IFACE_C_P
Definition: RegisterFile.h:1081
GVsP_CAP_VALUE
const uint32_t GVsP_CAP_VALUE
Definition: RegisterFile.h:1034
SocCamera::tcRegisterFile::tsRegDefinition
Definition: RegisterFile.h:151
GVSP_DFLT_PKT_SIZE
const int GVSP_DFLT_PKT_SIZE
Definition: GigE.h:9
GVCP_CAP_VALUE
const uint32_t GVCP_CAP_VALUE
Definition: RegisterFile.h:1027
PHY_CAP_SL
const uint32_t PHY_CAP_SL
This device supports single link (SL) configuration.
Definition: RegisterFile.h:1047
GigERegisters
Definition: GigERegisters.h:14
DEVMODE_BIGENDIAN
const uint32_t DEVMODE_BIGENDIAN
Flags for DEVICE_MODE register.
Definition: RegisterFile.h:1062
NET_IFACE_C_D
const uint32_t NET_IFACE_C_D
Definition: RegisterFile.h:1080
GenICamSharedRegs.h
VERSION
#define VERSION
Definition: config.h:68
PHY_CONFIG_SL
const uint32_t PHY_CONFIG_SL
Single link (SL) configuration.
Definition: RegisterFile.h:1056
RegisterFile.h
REGDEF_STR
#define REGDEF_STR(name, access, size, dflt)
Definition: RegisterFile.h:101