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Critical Link MityCam SoC Firmware
1.0
Critical Link MityCam SoC Firmware
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#include "RAMStreamer.h"Macros | |
| #define | READY_MASK (1 << 31) |
| #define | RESET_BIT (1 << 0) |
| #define | INTERRUPT_ENABLE (1 << 1) |
| #define | PACKING_SHIFT (4) |
| #define | PACKED_BIT (1 << PACKING_SHIFT) |
| #define | PACKING_BITS (3 << PACKING_SHIFT) |
| #define | CTRL_REG_OFFSET 1 |
| #define | START_ADDR_OFFSET 2 |
| #define | END_ADDR_OFFSET 3 |
| #define | FRAME_SIZE_OFFSET 4 |
| #define | INT_LEVEL_OFFSET 5 |
| #define | NUM_FRAMES_OFFSET 6 |
| #define | READY_TO_TAKE_OUT_OF_RESET_BIT (1 << 28) |
| #define | STICKY_BITS ((1 << 2) | (1 << 3)) |
| #define CTRL_REG_OFFSET 1 |
| #define END_ADDR_OFFSET 3 |
| #define FRAME_SIZE_OFFSET 4 |
| #define INT_LEVEL_OFFSET 5 |
| #define INTERRUPT_ENABLE (1 << 1) |
| #define NUM_FRAMES_OFFSET 6 |
| #define PACKED_BIT (1 << PACKING_SHIFT) |
| #define PACKING_BITS (3 << PACKING_SHIFT) |
| #define PACKING_SHIFT (4) |
| #define READY_MASK (1 << 31) |
| #define READY_TO_TAKE_OUT_OF_RESET_BIT (1 << 28) |
| #define RESET_BIT (1 << 0) |
| #define START_ADDR_OFFSET 2 |
| #define STICKY_BITS ((1 << 2) | (1 << 3)) |