Critical Link MityCam SoC Firmware  1.0
Critical Link MityCam SoC Firmware
RegisterNames.h
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1 // This file is autogenerated Wed Mar 23 08:30:37 EDT 2022
2 // by ./mknames.sh ./src/CommandInterface/RegisterFile.h src/CommandInterface/RegisterNames.h
3 // user: mikew on host mikew-cyberpc
4 // directory: /tmp/mitycam_sdk/ARM/camera_software
5 
6 #ifdef DEFINE_REG_NAMES
7 reg_addr_name_map[VERSION_ADDR] = "VERSION_ADDR";
8 reg_addr_name_map[DEVICE_MODE_ADDR] = "DEVICE_MODE_ADDR";
9 reg_addr_name_map[DEVICE_MAC_HIGH0_ADDR] = "DEVICE_MAC_HIGH0_ADDR";
10 reg_addr_name_map[DEVICE_MAC_LOW0_ADDR] = "DEVICE_MAC_LOW0_ADDR";
11 reg_addr_name_map[NET_IFACE_CAPABILITY0_ADDR] = "NET_IFACE_CAPABILITY0_ADDR";
12 reg_addr_name_map[NET_IFACE_CONFIG0_ADDR] = "NET_IFACE_CONFIG0_ADDR";
13 reg_addr_name_map[CURRENT_IP_ADDR0_ADDR] = "CURRENT_IP_ADDR0_ADDR";
14 reg_addr_name_map[CURRENT_SUBNET0_ADDR] = "CURRENT_SUBNET0_ADDR";
15 reg_addr_name_map[CURRENT_GATEWAY0_ADDR] = "CURRENT_GATEWAY0_ADDR";
16 reg_addr_name_map[MANUFACTURER_NAME_ADDR] = "MANUFACTURER_NAME_ADDR";
17 reg_addr_name_map[MODEL_NAME_ADDR] = "MODEL_NAME_ADDR";
18 reg_addr_name_map[DEVICE_VERSION_ADDR] = "DEVICE_VERSION_ADDR";
19 reg_addr_name_map[MANUFACTURER_INFO_ADDR] = "MANUFACTURER_INFO_ADDR";
20 reg_addr_name_map[SERIAL_NUMBER_ADDR] = "SERIAL_NUMBER_ADDR";
21 reg_addr_name_map[USER_NAME_ADDR] = "USER_NAME_ADDR";
22 reg_addr_name_map[FIRST_URL_ADDR] = "FIRST_URL_ADDR";
23 reg_addr_name_map[SECOND_URL_ADDR] = "SECOND_URL_ADDR";
24 reg_addr_name_map[NB_INTERFACES_ADDR] = "NB_INTERFACES_ADDR";
25 reg_addr_name_map[PERSISTENT_IP_ADDR0_ADDR] = "PERSISTENT_IP_ADDR0_ADDR";
26 reg_addr_name_map[PERSISTENT_SUBNET0_ADDR] = "PERSISTENT_SUBNET0_ADDR";
27 reg_addr_name_map[PERSISTENT_GATEWAY0_ADDR] = "PERSISTENT_GATEWAY0_ADDR";
28 reg_addr_name_map[NB_MSG_CHANNELS_ADDR] = "NB_MSG_CHANNELS_ADDR";
29 reg_addr_name_map[NB_STREAM_CHANNELS_ADDR] = "NB_STREAM_CHANNELS_ADDR";
30 reg_addr_name_map[NB_ACTIVE_LINKS_ADDR] = "NB_ACTIVE_LINKS_ADDR";
31 reg_addr_name_map[GVSP_CAPABILITY_ADDR] = "GVSP_CAPABILITY_ADDR";
32 reg_addr_name_map[MSG_CAPABILITY_ADDR] = "MSG_CAPABILITY_ADDR";
33 reg_addr_name_map[GVCP_CAPABILITY_ADDR] = "GVCP_CAPABILITY_ADDR";
34 reg_addr_name_map[HEARTBEAT_TIMEOUT_ADDR] = "HEARTBEAT_TIMEOUT_ADDR";
35 reg_addr_name_map[TIMESTAMP_FREQ_HIGH_ADDR] = "TIMESTAMP_FREQ_HIGH_ADDR";
36 reg_addr_name_map[TIMESTAMP_FREQ_LOW_ADDR] = "TIMESTAMP_FREQ_LOW_ADDR";
37 reg_addr_name_map[TIMESTAMP_CTRL_ADDR] = "TIMESTAMP_CTRL_ADDR";
38 reg_addr_name_map[TIMESTAMP_VALUE_HIGH_ADDR] = "TIMESTAMP_VALUE_HIGH_ADDR";
39 reg_addr_name_map[TIMESTAMP_VALUE_LOW_ADDR] = "TIMESTAMP_VALUE_LOW_ADDR";
40 reg_addr_name_map[GVCP_CONFIGURATION_ADDR] = "GVCP_CONFIGURATION_ADDR";
41 reg_addr_name_map[PENDING_TIMEOUT_ADDR] = "PENDING_TIMEOUT_ADDR";
42 reg_addr_name_map[CTRL_SWITCHOVER_KEY_ADDR] = "CTRL_SWITCHOVER_KEY_ADDR";
43 reg_addr_name_map[GVSP_CONFIGURATION_ADDR] = "GVSP_CONFIGURATION_ADDR";
44 reg_addr_name_map[PHY_CAPABILITY_ADDR] = "PHY_CAPABILITY_ADDR";
45 reg_addr_name_map[PHY_CONFIG_ADDR] = "PHY_CONFIG_ADDR";
46 reg_addr_name_map[IEEE_1588_STATUS_ADDR] = "IEEE_1588_STATUS_ADDR";
47 reg_addr_name_map[SCHEDULED_ACTION_Q_SIZE_ADDR] = "SCHEDULED_ACTION_Q_SIZE_ADDR";
48 reg_addr_name_map[CCP_ADDR] = "CCP_ADDR";
49 reg_addr_name_map[PA_PORT_ADDR] = "PA_PORT_ADDR";
50 reg_addr_name_map[PA_IP_ADDR] = "PA_IP_ADDR";
51 reg_addr_name_map[MCP_ADDR] = "MCP_ADDR";
52 reg_addr_name_map[MCDA_ADDR] = "MCDA_ADDR";
53 reg_addr_name_map[MCTT_ADDR] = "MCTT_ADDR";
54 reg_addr_name_map[MCRC_ADDR] = "MCRC_ADDR";
55 reg_addr_name_map[MCSP_ADDR] = "MCSP_ADDR";
56 reg_addr_name_map[SCP0_ADDR] = "SCP0_ADDR";
57 reg_addr_name_map[SCPS0_ADDR] = "SCPS0_ADDR";
58 reg_addr_name_map[SCPD0_ADDR] = "SCPD0_ADDR";
59 reg_addr_name_map[SCDA0_ADDR] = "SCDA0_ADDR";
60 reg_addr_name_map[SCSP0_ADDR] = "SCSP0_ADDR";
61 reg_addr_name_map[SCC0_ADDR] = "SCC0_ADDR";
62 reg_addr_name_map[SCCFG0_ADDR] = "SCCFG0_ADDR";
63 reg_addr_name_map[MANIFEST_TABLE_ADDR] = "MANIFEST_TABLE_ADDR";
64 reg_addr_name_map[ABRM_GENCP_VERSION_ADDR] = "ABRM_GENCP_VERSION_ADDR";
65 reg_addr_name_map[ABRM_MANUFACTURER_NAME_ADDR] = "ABRM_MANUFACTURER_NAME_ADDR";
66 reg_addr_name_map[ABRM_MODEL_NAME_ADDR] = "ABRM_MODEL_NAME_ADDR";
67 reg_addr_name_map[ABRM_FAMILY_NAME_ADDR] = "ABRM_FAMILY_NAME_ADDR";
68 reg_addr_name_map[ABRM_DEVICE_VERSION_ADDR] = "ABRM_DEVICE_VERSION_ADDR";
69 reg_addr_name_map[ABRM_MANUFACTURER_INFO_ADDR] = "ABRM_MANUFACTURER_INFO_ADDR";
70 reg_addr_name_map[ABRM_SERIAL_NUMBER_ADDR] = "ABRM_SERIAL_NUMBER_ADDR";
71 reg_addr_name_map[ABRM_USER_DEFINED_NAME_ADDR] = "ABRM_USER_DEFINED_NAME_ADDR";
72 reg_addr_name_map[ABRM_DEVICE_CAPABILITY_ADDR] = "ABRM_DEVICE_CAPABILITY_ADDR";
73 reg_addr_name_map[ABRM_MAX_DEVICE_RESPONSE_TIME_ADDR] = "ABRM_MAX_DEVICE_RESPONSE_TIME_ADDR";
74 reg_addr_name_map[ABRM_MANIFEST_TABLE_ADDRESS_ADDR] = "ABRM_MANIFEST_TABLE_ADDRESS_ADDR";
75 reg_addr_name_map[ABRM_SBRM_ADDRESS_ADDR] = "ABRM_SBRM_ADDRESS_ADDR";
76 reg_addr_name_map[ABRM_DEVICE_CONFIGURATION_ADDR] = "ABRM_DEVICE_CONFIGURATION_ADDR";
77 reg_addr_name_map[ABRM_HEARTBEAT_TIMEOUT_ADDR] = "ABRM_HEARTBEAT_TIMEOUT_ADDR";
78 reg_addr_name_map[ABRM_MESSAGE_CHANNEL_ID_ADDR] = "ABRM_MESSAGE_CHANNEL_ID_ADDR";
79 reg_addr_name_map[ABRM_TIMESTAMP_ADDR] = "ABRM_TIMESTAMP_ADDR";
80 reg_addr_name_map[ABRM_TIMESTAMP_LATCH_ADDR] = "ABRM_TIMESTAMP_LATCH_ADDR";
81 reg_addr_name_map[ABRM_TIMESTAMP_INCREMENT_ADDR] = "ABRM_TIMESTAMP_INCREMENT_ADDR";
82 reg_addr_name_map[ABRM_ACCESS_PRIVILEGE_ADDR] = "ABRM_ACCESS_PRIVILEGE_ADDR";
83 reg_addr_name_map[ABRM_PROTOCOL_ENDIANESS_ADDR] = "ABRM_PROTOCOL_ENDIANESS_ADDR";
84 reg_addr_name_map[ABRM_IMPLEMENTATION_ENDIANESS_ADDR] = "ABRM_IMPLEMENTATION_ENDIANESS_ADDR";
85 reg_addr_name_map[ABRM_RESERVED_ADDR] = "ABRM_RESERVED_ADDR";
86 reg_addr_name_map[U3V_VERSION_ADDR] = "U3V_VERSION_ADDR";
87 reg_addr_name_map[U3V_CP_CABABILITY_ADDR] = "U3V_CP_CABABILITY_ADDR";
88 reg_addr_name_map[U3V_CP_CONFIGURATION_ADDR] = "U3V_CP_CONFIGURATION_ADDR";
89 reg_addr_name_map[U3V_MAX_COMMAND_TRANS_ADDR] = "U3V_MAX_COMMAND_TRANS_ADDR";
90 reg_addr_name_map[U3V_MAX_ACK_TRANS_ADDR] = "U3V_MAX_ACK_TRANS_ADDR";
91 reg_addr_name_map[U3V_NB_STRTEAM_ADDR] = "U3V_NB_STRTEAM_ADDR";
92 reg_addr_name_map[U3V_SIRM_ADDRESS_ADDR] = "U3V_SIRM_ADDRESS_ADDR";
93 reg_addr_name_map[U3V_SIRM_LENGTH_ADDR] = "U3V_SIRM_LENGTH_ADDR";
94 reg_addr_name_map[U3V_EIRM_ADDRESS_ADDR] = "U3V_EIRM_ADDRESS_ADDR";
95 reg_addr_name_map[U3V_EIRM_LENGTH_ADDR] = "U3V_EIRM_LENGTH_ADDR";
96 reg_addr_name_map[U3V_IIDC2_ADDRESS_ADDR] = "U3V_IIDC2_ADDRESS_ADDR";
97 reg_addr_name_map[U3V_CURRENT_SPEED_ADDR] = "U3V_CURRENT_SPEED_ADDR";
98 reg_addr_name_map[U3V_SIRM_TABLE_ADDR] = "U3V_SIRM_TABLE_ADDR";
99 reg_addr_name_map[U3V_SIRM_INFO_ADDR] = "U3V_SIRM_INFO_ADDR";
100 reg_addr_name_map[U3V_SIRM_CTRL_ADDR] = "U3V_SIRM_CTRL_ADDR";
101 reg_addr_name_map[U3V_REQ_PAYLOAD_SIZE_ADDR] = "U3V_REQ_PAYLOAD_SIZE_ADDR";
102 reg_addr_name_map[U3V_REQ_LEADER_SIZE_ADDR] = "U3V_REQ_LEADER_SIZE_ADDR";
103 reg_addr_name_map[U3V_REQ_TRAILER_SIZE_ADDR] = "U3V_REQ_TRAILER_SIZE_ADDR";
104 reg_addr_name_map[U3V_MAX_LEADER_ADDR] = "U3V_MAX_LEADER_ADDR";
105 reg_addr_name_map[U3V_PAYLOAD_SIZE_ADDR] = "U3V_PAYLOAD_SIZE_ADDR";
106 reg_addr_name_map[U3V_PAYLOAD_COUNT_ADDR] = "U3V_PAYLOAD_COUNT_ADDR";
107 reg_addr_name_map[U3V_PAYLOAD_FINAL1_ADDR] = "U3V_PAYLOAD_FINAL1_ADDR";
108 reg_addr_name_map[U3V_PAYLOAD_FINAL2_ADDR] = "U3V_PAYLOAD_FINAL2_ADDR";
109 reg_addr_name_map[U3V_MAX_TRAILER_SIZE_ADDR] = "U3V_MAX_TRAILER_SIZE_ADDR";
110 reg_addr_name_map[DEVICE_FIRMWARE_VERSION_ADDR] = "DEVICE_FIRMWARE_VERSION_ADDR";
111 reg_addr_name_map[DEVICE_RESET_ADDR] = "DEVICE_RESET_ADDR";
112 reg_addr_name_map[DEVICE_FPGA_VERSION_ADDR] = "DEVICE_FPGA_VERSION_ADDR";
113 reg_addr_name_map[DEVICE_SOFTWARE_DATE_ADDR] = "DEVICE_SOFTWARE_DATE_ADDR";
114 reg_addr_name_map[DEVICE_FX3_DATE_ADDR] = "DEVICE_FX3_DATE_ADDR";
115 reg_addr_name_map[AQUISITION_FRAMERATE_ADDR] = "AQUISITION_FRAMERATE_ADDR";
116 reg_addr_name_map[EXPOSURE_TIME_ADDR] = "EXPOSURE_TIME_ADDR";
117 reg_addr_name_map[ROI_WIDTH_ADDR] = "ROI_WIDTH_ADDR";
118 reg_addr_name_map[ROI_HEIGHT_ADDR] = "ROI_HEIGHT_ADDR";
119 reg_addr_name_map[ROI_OFFSET_X_ADDR] = "ROI_OFFSET_X_ADDR";
120 reg_addr_name_map[ROI_OFFSET_Y_ADDR] = "ROI_OFFSET_Y_ADDR";
121 reg_addr_name_map[ACQUISITION_START_ADDR] = "ACQUISITION_START_ADDR";
122 reg_addr_name_map[ACQUISITION_MODE_ADDR] = "ACQUISITION_MODE_ADDR";
123 reg_addr_name_map[PIXEL_FORMAT_ADDR] = "PIXEL_FORMAT_ADDR";
124 reg_addr_name_map[PAYLOAD_SIZE_ADDR] = "PAYLOAD_SIZE_ADDR";
125 reg_addr_name_map[BINNING_HORIZONTAL_ADDR] = "BINNING_HORIZONTAL_ADDR";
126 reg_addr_name_map[BINNING_VERTICAL_ADDR] = "BINNING_VERTICAL_ADDR";
127 reg_addr_name_map[REVERSE_X_ADDR] = "REVERSE_X_ADDR";
128 reg_addr_name_map[REVERSE_Y_ADDR] = "REVERSE_Y_ADDR";
129 reg_addr_name_map[ACQUISITION_NUM_FRAMES_ADDR] = "ACQUISITION_NUM_FRAMES_ADDR";
130 reg_addr_name_map[ACQUISITION_STOP_ADDR] = "ACQUISITION_STOP_ADDR";
131 reg_addr_name_map[DECIMATION_VERTICAL_ADDR] = "DECIMATION_VERTICAL_ADDR";
132 reg_addr_name_map[SENSOR_TEMPERATURE_ADDR] = "SENSOR_TEMPERATURE_ADDR";
133 reg_addr_name_map[BOARD_TEMPERATURE_ADDR] = "BOARD_TEMPERATURE_ADDR";
134 reg_addr_name_map[EDGE_DETECTION_ADDR] = "EDGE_DETECTION_ADDR";
135 reg_addr_name_map[SHUTTER_MODE_ADDR] = "SHUTTER_MODE_ADDR";
136 reg_addr_name_map[SENSOR_GAINMODE_ADDR] = "SENSOR_GAINMODE_ADDR";
137 reg_addr_name_map[SENSOR_CALIBRATE_ADDR] = "SENSOR_CALIBRATE_ADDR";
138 reg_addr_name_map[TEST_PATTERN_ADDR] = "TEST_PATTERN_ADDR";
139 reg_addr_name_map[CLOCK_SPEED_ADDR] = "CLOCK_SPEED_ADDR";
140 reg_addr_name_map[SQRT_COMPRESS_ADDR] = "SQRT_COMPRESS_ADDR";
141 reg_addr_name_map[HOT_PIXEL_CORRECT_ADDR] = "HOT_PIXEL_CORRECT_ADDR";
142 reg_addr_name_map[BAD_PIXEL_CTRL_ADDR] = "BAD_PIXEL_CTRL_ADDR";
143 reg_addr_name_map[BAD_PIXEL_CTRL_MAP_ADDR] = "BAD_PIXEL_CTRL_MAP_ADDR";
144 reg_addr_name_map[VOLTAGE_SENSOR_SELECT_ADDR] = "VOLTAGE_SENSOR_SELECT_ADDR";
145 reg_addr_name_map[VOLTAGE_SENSOR_VALUE_ADDR] = "VOLTAGE_SENSOR_VALUE_ADDR";
146 reg_addr_name_map[DEVICE_TEMPERATURE_SELECT_ADDR] = "DEVICE_TEMPERATURE_SELECT_ADDR";
147 reg_addr_name_map[DEVICE_TEMPERATURE_ADDR] = "DEVICE_TEMPERATURE_ADDR";
148 reg_addr_name_map[EXPOSURE_TIME_SELECT_ADDR] = "EXPOSURE_TIME_SELECT_ADDR";
149 reg_addr_name_map[SENSOR_WIDTH_ADDR] = "SENSOR_WIDTH_ADDR";
150 reg_addr_name_map[SENSOR_HEIGHT_ADDR] = "SENSOR_HEIGHT_ADDR";
151 reg_addr_name_map[FREE_RAM_CFG_ADDR] = "FREE_RAM_CFG_ADDR";
152 reg_addr_name_map[INTERNAL_EXP_MODE_ADDR] = "INTERNAL_EXP_MODE_ADDR";
153 reg_addr_name_map[LUT_SELECTOR_ADDR] = "LUT_SELECTOR_ADDR";
154 reg_addr_name_map[LUT_ENABLE_ADDR] = "LUT_ENABLE_ADDR";
155 reg_addr_name_map[LUT_MAXINDEX_ADDR] = "LUT_MAXINDEX_ADDR";
156 reg_addr_name_map[LUT_INDEX_ADDR] = "LUT_INDEX_ADDR";
157 reg_addr_name_map[LUT_MAXVALUE_ADDR] = "LUT_MAXVALUE_ADDR";
158 reg_addr_name_map[LUT_VALUE_ADDR] = "LUT_VALUE_ADDR";
159 reg_addr_name_map[GAIN_SELECTOR_ADDR] = "GAIN_SELECTOR_ADDR";
160 reg_addr_name_map[GAIN_ADDR] = "GAIN_ADDR";
161 reg_addr_name_map[GAIN_AUTO_ADDR] = "GAIN_AUTO_ADDR";
162 reg_addr_name_map[GAIN_AUTOBALANCE_ADDR] = "GAIN_AUTOBALANCE_ADDR";
163 reg_addr_name_map[BLACK_LEVEL_SELECTOR_ADDR] = "BLACK_LEVEL_SELECTOR_ADDR";
164 reg_addr_name_map[BLACK_LEVEL_ADDR] = "BLACK_LEVEL_ADDR";
165 reg_addr_name_map[BLACK_LEVEL_AUTO_ADDR] = "BLACK_LEVEL_AUTO_ADDR";
166 reg_addr_name_map[BLACK_LEVEL_AUTOBALANCE_ADDR] = "BLACK_LEVEL_AUTOBALANCE_ADDR";
167 reg_addr_name_map[WHITE_CLIP_SELECTOR_ADDR] = "WHITE_CLIP_SELECTOR_ADDR";
168 reg_addr_name_map[WHITE_CLIP_ADDR] = "WHITE_CLIP_ADDR";
169 reg_addr_name_map[BALANCE_RATIO_SELECTOR_ADDR] = "BALANCE_RATIO_SELECTOR_ADDR";
170 reg_addr_name_map[BALANCE_RATIO_ADDR] = "BALANCE_RATIO_ADDR";
171 reg_addr_name_map[BALANCE_WHITE_AUTO_ADDR] = "BALANCE_WHITE_AUTO_ADDR";
172 reg_addr_name_map[GAMMA_ADDR] = "GAMMA_ADDR";
173 reg_addr_name_map[BLACK_LEVEL_BIAS_ADDR] = "BLACK_LEVEL_BIAS_ADDR";
174 reg_addr_name_map[COLOR_TRANSF_SELECTOR_ADDR] = "COLOR_TRANSF_SELECTOR_ADDR";
175 reg_addr_name_map[COLOR_TRANSF_ENABLE_ADDR] = "COLOR_TRANSF_ENABLE_ADDR";
176 reg_addr_name_map[COLOR_TRANSF_VALUE_SELECTOR_ADDR] = "COLOR_TRANSF_VALUE_SELECTOR_ADDR";
177 reg_addr_name_map[COLOR_TRANSF_VALUE_ADDR] = "COLOR_TRANSF_VALUE_ADDR";
178 reg_addr_name_map[TRIGGER_SELECTOR_ADDR] = "TRIGGER_SELECTOR_ADDR";
179 reg_addr_name_map[TRIGGER_MODE_ADDR] = "TRIGGER_MODE_ADDR";
180 reg_addr_name_map[TRIGGER_SOURCE_ADDR] = "TRIGGER_SOURCE_ADDR";
181 reg_addr_name_map[TRIGGER_ACTIVATION_ADDR] = "TRIGGER_ACTIVATION_ADDR";
182 reg_addr_name_map[DIGITAL_IO_LINE_SELECT_ADDR] = "DIGITAL_IO_LINE_SELECT_ADDR";
183 reg_addr_name_map[DIGITAL_IO_LINE_MODE_ADDR] = "DIGITAL_IO_LINE_MODE_ADDR";
184 reg_addr_name_map[DIGITAL_IO_LINE_SOURCE_ADDR] = "DIGITAL_IO_LINE_SOURCE_ADDR";
185 reg_addr_name_map[USER_OUTPUT_SELECTOR_ADDR] = "USER_OUTPUT_SELECTOR_ADDR";
186 reg_addr_name_map[USER_OUTPUT_VALUE_ADDR] = "USER_OUTPUT_VALUE_ADDR";
187 reg_addr_name_map[DIGITAL_IO_LINE_STATUS_ADDR] = "DIGITAL_IO_LINE_STATUS_ADDR";
188 reg_addr_name_map[DIGITAL_IO_LINE_INVERTER_ADDR] = "DIGITAL_IO_LINE_INVERTER_ADDR";
189 reg_addr_name_map[INDICATOR_CONTROL_ADDR] = "INDICATOR_CONTROL_ADDR";
190 reg_addr_name_map[FAN_CONTROL_ADDR] = "FAN_CONTROL_ADDR";
191 reg_addr_name_map[IS_CAMERA_COLOR_ADDR] = "IS_CAMERA_COLOR_ADDR";
192 reg_addr_name_map[SENS_REG_ADDR_ADDR] = "SENS_REG_ADDR_ADDR";
193 reg_addr_name_map[SENS_VAL_ADDR] = "SENS_VAL_ADDR";
194 reg_addr_name_map[SENS_READ_ADDR] = "SENS_READ_ADDR";
195 reg_addr_name_map[SENS_WRITE_ADDR] = "SENS_WRITE_ADDR";
196 reg_addr_name_map[SENS_MIN_FRAME_PERIOD_ADDR] = "SENS_MIN_FRAME_PERIOD_ADDR";
197 reg_addr_name_map[SENS_SPECIFIC_1_ADDR] = "SENS_SPECIFIC_1_ADDR";
198 reg_addr_name_map[SENS_SPECIFIC_2_ADDR] = "SENS_SPECIFIC_2_ADDR";
199 reg_addr_name_map[SENS_SPECIFIC_3_ADDR] = "SENS_SPECIFIC_3_ADDR";
200 reg_addr_name_map[SENS_SPECIFIC_4_ADDR] = "SENS_SPECIFIC_4_ADDR";
201 reg_addr_name_map[SENS_SPECIFIC_5_ADDR] = "SENS_SPECIFIC_5_ADDR";
202 reg_addr_name_map[SENS_SPECIFIC_6_ADDR] = "SENS_SPECIFIC_6_ADDR";
203 reg_addr_name_map[SENS_SPECIFIC_7_ADDR] = "SENS_SPECIFIC_7_ADDR";
204 reg_addr_name_map[SENS_SPECIFIC_8_ADDR] = "SENS_SPECIFIC_8_ADDR";
205 reg_addr_name_map[SENS_SPECIFIC_9_ADDR] = "SENS_SPECIFIC_9_ADDR";
206 reg_addr_name_map[SENS_SPECIFIC_10_ADDR] = "SENS_SPECIFIC_10_ADDR";
207 reg_addr_name_map[SENS_SPECIFIC_11_ADDR] = "SENS_SPECIFIC_11_ADDR";
208 reg_addr_name_map[SENS_SPECIFIC_12_ADDR] = "SENS_SPECIFIC_12_ADDR";
209 reg_addr_name_map[SENS_SPECIFIC_13_ADDR] = "SENS_SPECIFIC_13_ADDR";
210 reg_addr_name_map[SENS_SPECIFIC_14_ADDR] = "SENS_SPECIFIC_14_ADDR";
211 reg_addr_name_map[SENS_SPECIFIC_15_ADDR] = "SENS_SPECIFIC_15_ADDR";
212 reg_addr_name_map[SENS_SPECIFIC_16_ADDR] = "SENS_SPECIFIC_16_ADDR";
213 reg_addr_name_map[SENS_SPECIFIC_17_ADDR] = "SENS_SPECIFIC_17_ADDR";
214 reg_addr_name_map[SENS_SPECIFIC_18_ADDR] = "SENS_SPECIFIC_18_ADDR";
215 reg_addr_name_map[SENS_SPECIFIC_19_ADDR] = "SENS_SPECIFIC_19_ADDR";
216 reg_addr_name_map[SENS_SPECIFIC_20_ADDR] = "SENS_SPECIFIC_20_ADDR";
217 reg_addr_name_map[SENS_SPECIFIC_21_ADDR] = "SENS_SPECIFIC_21_ADDR";
218 reg_addr_name_map[SENS_SPECIFIC_22_ADDR] = "SENS_SPECIFIC_22_ADDR";
219 reg_addr_name_map[SENS_SPECIFIC_23_ADDR] = "SENS_SPECIFIC_23_ADDR";
220 reg_addr_name_map[SENS_SPECIFIC_24_ADDR] = "SENS_SPECIFIC_24_ADDR";
221 reg_addr_name_map[SENS_SPECIFIC_25_ADDR] = "SENS_SPECIFIC_25_ADDR";
222 reg_addr_name_map[SENS_SPECIFIC_26_ADDR] = "SENS_SPECIFIC_26_ADDR";
223 reg_addr_name_map[SENS_SPECIFIC_27_ADDR] = "SENS_SPECIFIC_27_ADDR";
224 reg_addr_name_map[SENS_SPECIFIC_28_ADDR] = "SENS_SPECIFIC_28_ADDR";
225 reg_addr_name_map[SENS_SPECIFIC_29_ADDR] = "SENS_SPECIFIC_29_ADDR";
226 reg_addr_name_map[SENS_SPECIFIC_30_ADDR] = "SENS_SPECIFIC_30_ADDR";
227 reg_addr_name_map[SENS_SPECIFIC_FLOAT_1_ADDR] = "SENS_SPECIFIC_FLOAT_1_ADDR";
228 reg_addr_name_map[SENS_SPECIFIC_FLOAT_2_ADDR] = "SENS_SPECIFIC_FLOAT_2_ADDR";
229 reg_addr_name_map[SENS_SPECIFIC_FLOAT_3_ADDR] = "SENS_SPECIFIC_FLOAT_3_ADDR";
230 reg_addr_name_map[SENS_SPECIFIC_FLOAT_4_ADDR] = "SENS_SPECIFIC_FLOAT_4_ADDR";
231 reg_addr_name_map[SENS_SPECIFIC_FLOAT_5_ADDR] = "SENS_SPECIFIC_FLOAT_5_ADDR";
232 reg_addr_name_map[SENS_PEEKPOKE_ADDR] = "SENS_PEEKPOKE_ADDR";
233 reg_addr_name_map[SENS_PEEKPOKE_ADDR_END] = "SENS_PEEKPOKE_ADDR_END";
234 reg_addr_name_map[XML_FILE_ADDR] = "XML_FILE_ADDR";
235 reg_addr_name_map[DEBUG_BUFFER_BYTESWRITTEN_ADDR] = "DEBUG_BUFFER_BYTESWRITTEN_ADDR";
236 reg_addr_name_map[DEBUG_BUFFER_ADDR] = "DEBUG_BUFFER_ADDR";
237 reg_addr_name_map[MANIFEST_TABLE_COUNT_ADDR] = "MANIFEST_TABLE_COUNT_ADDR";
238 reg_addr_name_map[MANIFEST_VER_ADDR] = "MANIFEST_VER_ADDR";
239 reg_addr_name_map[MANIFEST_TYPE_ADDR] = "MANIFEST_TYPE_ADDR";
240 reg_addr_name_map[MANIFEST_REG_ADDR] = "MANIFEST_REG_ADDR";
241 reg_addr_name_map[MANIFEST_FILE_SIZE_ADDR] = "MANIFEST_FILE_SIZE_ADDR";
242 reg_addr_name_map[MANIFEST_SHA1_ADDR] = "MANIFEST_SHA1_ADDR";
243 reg_addr_name_map[BEYOND_MANIFEST_ADDR] = "BEYOND_MANIFEST_ADDR";
244 reg_addr_name_map[TEST_PENDING_ACK_ADDR] = "TEST_PENDING_ACK_ADDR";
245 reg_addr_name_map[HDMI_START_ADDR] = "HDMI_START_ADDR";
246 reg_addr_name_map[HDMI_STOP_ADDR] = "HDMI_STOP_ADDR";
247 reg_addr_name_map[HDMI_OFFSET_X_ADDR] = "HDMI_OFFSET_X_ADDR";
248 reg_addr_name_map[HDMI_OFFSET_Y_ADDR] = "HDMI_OFFSET_Y_ADDR";
249 reg_addr_name_map[HDMI_WIDTH_ADDR] = "HDMI_WIDTH_ADDR";
250 reg_addr_name_map[HDMI_HEIGHT_ADDR] = "HDMI_HEIGHT_ADDR";
251 reg_addr_name_map[HDMI_OUTPUT_SEL_ADDR] = "HDMI_OUTPUT_SEL_ADDR";
252 reg_addr_name_map[HDMI_GAMMA_ADDR] = "HDMI_GAMMA_ADDR";
253 reg_addr_name_map[HDMI_WBRED_ADDR] = "HDMI_WBRED_ADDR";
254 reg_addr_name_map[HDMI_WBGREEN_ADDR] = "HDMI_WBGREEN_ADDR";
255 reg_addr_name_map[HDMI_WBBLUE_ADDR] = "HDMI_WBBLUE_ADDR";
256 reg_addr_name_map[HDMI_TESTPATEN_ADDR] = "HDMI_TESTPATEN_ADDR";
257 reg_addr_name_map[HDMI_BPP_ADDR] = "HDMI_BPP_ADDR";
258 #else
259 #error DO NOT INCLUDE THIS FILE
260 #endif
261 #undef DEFINE_REG_NAMES
BALANCE_RATIO_ADDR
const uint32_t BALANCE_RATIO_ADDR
Definition: RegisterFile.h:697
GAIN_AUTO_ADDR
const uint32_t GAIN_AUTO_ADDR
Definition: RegisterFile.h:688
U3V_REQ_TRAILER_SIZE_ADDR
const uint32_t U3V_REQ_TRAILER_SIZE_ADDR
Definition: RegisterFile.h:592
SENSOR_CALIBRATE_ADDR
const uint32_t SENSOR_CALIBRATE_ADDR
Definition: RegisterFile.h:639
BINNING_VERTICAL_ADDR
const uint32_t BINNING_VERTICAL_ADDR
SFNC 4.28 BinningVertical - Number of pixels to bin in the vertical direction.
Definition: RegisterFile.h:627
HDMI_BPP_ADDR
const uint32_t HDMI_BPP_ADDR
Definition: RegisterFile.h:913
SENS_SPECIFIC_10_ADDR
const uint32_t SENS_SPECIFIC_10_ADDR
Definition: RegisterFile.h:841
USER_OUTPUT_VALUE_ADDR
const uint32_t USER_OUTPUT_VALUE_ADDR
Definition: RegisterFile.h:800
DEVICE_MAC_HIGH0_ADDR
const uint32_t DEVICE_MAC_HIGH0_ADDR
This register stores the MAC address (upper 16-bit) of the given network interface.
Definition: RegisterFile.h:443
ABRM_MANUFACTURER_NAME_ADDR
const uint32_t ABRM_MANUFACTURER_NAME_ADDR
Definition: RegisterFile.h:501
SCC0_ADDR
const uint32_t SCC0_ADDR
First Stream Channel Capability register.
Definition: RegisterFile.h:495
SCCFG0_ADDR
const uint32_t SCCFG0_ADDR
First Stream Channel Configuration register.
Definition: RegisterFile.h:496
SENS_PEEKPOKE_ADDR_END
const uint32_t SENS_PEEKPOKE_ADDR_END
Definition: RegisterFile.h:870
SENS_SPECIFIC_FLOAT_3_ADDR
const uint32_t SENS_SPECIFIC_FLOAT_3_ADDR
Definition: RegisterFile.h:865
U3V_PAYLOAD_SIZE_ADDR
const uint32_t U3V_PAYLOAD_SIZE_ADDR
Definition: RegisterFile.h:594
SENS_SPECIFIC_FLOAT_5_ADDR
const uint32_t SENS_SPECIFIC_FLOAT_5_ADDR
Definition: RegisterFile.h:867
GAIN_AUTOBALANCE_ADDR
const uint32_t GAIN_AUTOBALANCE_ADDR
Definition: RegisterFile.h:689
U3V_SIRM_ADDRESS_ADDR
const uint32_t U3V_SIRM_ADDRESS_ADDR
Definition: RegisterFile.h:554
TIMESTAMP_VALUE_HIGH_ADDR
const uint32_t TIMESTAMP_VALUE_HIGH_ADDR
This register reports the latched value of the timestamp counter. It is necessary to latch the 64-bit...
Definition: RegisterFile.h:472
MANUFACTURER_NAME_ADDR
const uint32_t MANUFACTURER_NAME_ADDR
This registers stores a string containing the manufacturer name. This string uses the character set i...
Definition: RegisterFile.h:450
VOLTAGE_SENSOR_SELECT_ADDR
const uint32_t VOLTAGE_SENSOR_SELECT_ADDR
Selects which ADC / voltage sensor to read back.
Definition: RegisterFile.h:651
HDMI_WIDTH_ADDR
const uint32_t HDMI_WIDTH_ADDR
Definition: RegisterFile.h:904
MANIFEST_SHA1_ADDR
const uint32_t MANIFEST_SHA1_ADDR
Definition: RegisterFile.h:891
SENS_SPECIFIC_29_ADDR
const uint32_t SENS_SPECIFIC_29_ADDR
Definition: RegisterFile.h:860
TIMESTAMP_FREQ_LOW_ADDR
const uint32_t TIMESTAMP_FREQ_LOW_ADDR
This register indicates the number of timestamp tick during 1 second. This corresponds to the timesta...
Definition: RegisterFile.h:470
SENS_REG_ADDR_ADDR
const uint32_t SENS_REG_ADDR_ADDR
Definition: RegisterFile.h:824
SENS_SPECIFIC_4_ADDR
const uint32_t SENS_SPECIFIC_4_ADDR
Definition: RegisterFile.h:835
SENS_SPECIFIC_13_ADDR
const uint32_t SENS_SPECIFIC_13_ADDR
Definition: RegisterFile.h:844
MANIFEST_REG_ADDR
const uint32_t MANIFEST_REG_ADDR
Definition: RegisterFile.h:889
ACQUISITION_STOP_ADDR
const uint32_t ACQUISITION_STOP_ADDR
SFNC 5.5.4 AquisitionStop - Start/stop image acquisition using the specified acquision mode in the Ac...
Definition: RegisterFile.h:631
SENS_VAL_ADDR
const uint32_t SENS_VAL_ADDR
Definition: RegisterFile.h:825
EXPOSURE_TIME_ADDR
const uint32_t EXPOSURE_TIME_ADDR
SFNC 5.7.4 ExposureTime - This register sets the Exposure time (uS).
Definition: RegisterFile.h:617
BLACK_LEVEL_ADDR
const uint32_t BLACK_LEVEL_ADDR
Definition: RegisterFile.h:691
GVSP_CONFIGURATION_ADDR
const uint32_t GVSP_CONFIGURATION_ADDR
This register enables the 64-bit block_id64 for GVSP.
Definition: RegisterFile.h:477
ABRM_MANUFACTURER_INFO_ADDR
const uint32_t ABRM_MANUFACTURER_INFO_ADDR
Definition: RegisterFile.h:505
NB_STREAM_CHANNELS_ADDR
const uint32_t NB_STREAM_CHANNELS_ADDR
This register reports the number of stream channels supported by this device. A device must support a...
Definition: RegisterFile.h:463
TIMESTAMP_VALUE_LOW_ADDR
const uint32_t TIMESTAMP_VALUE_LOW_ADDR
This register reports the latched value of the timestamp counter. It is necessary to latch the 64-bit...
Definition: RegisterFile.h:473
LUT_INDEX_ADDR
const uint32_t LUT_INDEX_ADDR
Definition: RegisterFile.h:670
ABRM_IMPLEMENTATION_ENDIANESS_ADDR
const uint32_t ABRM_IMPLEMENTATION_ENDIANESS_ADDR
Definition: RegisterFile.h:520
MSG_CAPABILITY_ADDR
const uint32_t MSG_CAPABILITY_ADDR
Indicates the MCSP capability. Bit 0 is MCSP_Supported.
Definition: RegisterFile.h:466
ABRM_RESERVED_ADDR
const uint32_t ABRM_RESERVED_ADDR
Definition: RegisterFile.h:521
SENS_SPECIFIC_9_ADDR
const uint32_t SENS_SPECIFIC_9_ADDR
Definition: RegisterFile.h:840
SENS_SPECIFIC_27_ADDR
const uint32_t SENS_SPECIFIC_27_ADDR
Definition: RegisterFile.h:858
CLOCK_SPEED_ADDR
const uint32_t CLOCK_SPEED_ADDR
Definition: RegisterFile.h:642
BALANCE_WHITE_AUTO_ADDR
const uint32_t BALANCE_WHITE_AUTO_ADDR
Definition: RegisterFile.h:698
U3V_IIDC2_ADDRESS_ADDR
const uint32_t U3V_IIDC2_ADDRESS_ADDR
Definition: RegisterFile.h:558
U3V_SIRM_TABLE_ADDR
const uint32_t U3V_SIRM_TABLE_ADDR
Definition: RegisterFile.h:587
PERSISTENT_SUBNET0_ADDR
const uint32_t PERSISTENT_SUBNET0_ADDR
This register indicates the Persistent subnet mask associated with the Persistent IP address on this ...
Definition: RegisterFile.h:460
BLACK_LEVEL_SELECTOR_ADDR
const uint32_t BLACK_LEVEL_SELECTOR_ADDR
Definition: RegisterFile.h:690
U3V_MAX_LEADER_ADDR
const uint32_t U3V_MAX_LEADER_ADDR
Definition: RegisterFile.h:593
SQRT_COMPRESS_ADDR
const uint32_t SQRT_COMPRESS_ADDR
Definition: RegisterFile.h:644
EDGE_DETECTION_ADDR
const uint32_t EDGE_DETECTION_ADDR
Definition: RegisterFile.h:636
BLACK_LEVEL_BIAS_ADDR
const uint32_t BLACK_LEVEL_BIAS_ADDR
Definition: RegisterFile.h:700
U3V_MAX_ACK_TRANS_ADDR
const uint32_t U3V_MAX_ACK_TRANS_ADDR
Definition: RegisterFile.h:552
PA_PORT_ADDR
const uint32_t PA_PORT_ADDR
UDP source port of the control channel of the primary application.
Definition: RegisterFile.h:483
SENS_SPECIFIC_8_ADDR
const uint32_t SENS_SPECIFIC_8_ADDR
Definition: RegisterFile.h:839
U3V_NB_STRTEAM_ADDR
const uint32_t U3V_NB_STRTEAM_ADDR
Definition: RegisterFile.h:553
COLOR_TRANSF_VALUE_SELECTOR_ADDR
const uint32_t COLOR_TRANSF_VALUE_SELECTOR_ADDR
Definition: RegisterFile.h:737
U3V_REQ_LEADER_SIZE_ADDR
const uint32_t U3V_REQ_LEADER_SIZE_ADDR
Definition: RegisterFile.h:591
GVCP_CAPABILITY_ADDR
const uint32_t GVCP_CAPABILITY_ADDR
This register reports the optional GVCP command supported by this device.
Definition: RegisterFile.h:467
SENSOR_GAINMODE_ADDR
const uint32_t SENSOR_GAINMODE_ADDR
Definition: RegisterFile.h:638
INDICATOR_CONTROL_ADDR
const uint32_t INDICATOR_CONTROL_ADDR
control indicators / LEDS on camera
Definition: RegisterFile.h:819
MCRC_ADDR
const uint32_t MCRC_ADDR
This register indicates the number of retransmissions allowed when a message channel message times ou...
Definition: RegisterFile.h:488
GVSP_CAPABILITY_ADDR
const uint32_t GVSP_CAPABILITY_ADDR
Bit 1 indicates SCSP availability, bit 2 indicates legacy 16 bit block ID support available....
Definition: RegisterFile.h:465
SENS_SPECIFIC_26_ADDR
const uint32_t SENS_SPECIFIC_26_ADDR
Definition: RegisterFile.h:857
BAD_PIXEL_CTRL_ADDR
const uint32_t BAD_PIXEL_CTRL_ADDR
Definition: RegisterFile.h:648
SERIAL_NUMBER_ADDR
const uint32_t SERIAL_NUMBER_ADDR
String providing the serial number of this device.
Definition: RegisterFile.h:454
HDMI_WBRED_ADDR
const uint32_t HDMI_WBRED_ADDR
Definition: RegisterFile.h:909
FAN_CONTROL_ADDR
const uint32_t FAN_CONTROL_ADDR
control for FAN
Definition: RegisterFile.h:820
U3V_PAYLOAD_FINAL1_ADDR
const uint32_t U3V_PAYLOAD_FINAL1_ADDR
Definition: RegisterFile.h:596
GAIN_SELECTOR_ADDR
const uint32_t GAIN_SELECTOR_ADDR
Definition: RegisterFile.h:686
U3V_EIRM_ADDRESS_ADDR
const uint32_t U3V_EIRM_ADDRESS_ADDR
Definition: RegisterFile.h:556
DEVICE_FPGA_VERSION_ADDR
const uint32_t DEVICE_FPGA_VERSION_ADDR
Definition: RegisterFile.h:612
SENS_PEEKPOKE_ADDR
const uint32_t SENS_PEEKPOKE_ADDR
Definition: RegisterFile.h:869
SENS_SPECIFIC_17_ADDR
const uint32_t SENS_SPECIFIC_17_ADDR
Definition: RegisterFile.h:848
SENSOR_HEIGHT_ADDR
const uint32_t SENSOR_HEIGHT_ADDR
SFNC 4.3 SensorHeight - Effective height of sensor in pixels.
Definition: RegisterFile.h:660
DEVICE_RESET_ADDR
const uint32_t DEVICE_RESET_ADDR
Definition: RegisterFile.h:610
CCP_ADDR
const uint32_t CCP_ADDR
This register is used to grant privilege to an application.
Definition: RegisterFile.h:482
SENS_SPECIFIC_24_ADDR
const uint32_t SENS_SPECIFIC_24_ADDR
Definition: RegisterFile.h:855
ABRM_FAMILY_NAME_ADDR
const uint32_t ABRM_FAMILY_NAME_ADDR
Definition: RegisterFile.h:503
ABRM_MANIFEST_TABLE_ADDRESS_ADDR
const uint32_t ABRM_MANIFEST_TABLE_ADDRESS_ADDR
Definition: RegisterFile.h:510
DEVICE_TEMPERATURE_ADDR
const uint32_t DEVICE_TEMPERATURE_ADDR
SFNC 3.61 DeviceTemperature.
Definition: RegisterFile.h:655
DECIMATION_VERTICAL_ADDR
const uint32_t DECIMATION_VERTICAL_ADDR
SFNC 4.32 DecimationVertical - Number of rows to skip in the vertical direction.
Definition: RegisterFile.h:632
ACQUISITION_MODE_ADDR
const uint32_t ACQUISITION_MODE_ADDR
SFNC 5.5.2 AcquisitionMode - Controls acquisition mode.
Definition: RegisterFile.h:623
LUT_SELECTOR_ADDR
const uint32_t LUT_SELECTOR_ADDR
Definition: RegisterFile.h:667
COLOR_TRANSF_VALUE_ADDR
const uint32_t COLOR_TRANSF_VALUE_ADDR
Definition: RegisterFile.h:738
U3V_REQ_PAYLOAD_SIZE_ADDR
const uint32_t U3V_REQ_PAYLOAD_SIZE_ADDR
Definition: RegisterFile.h:590
SENS_SPECIFIC_5_ADDR
const uint32_t SENS_SPECIFIC_5_ADDR
Definition: RegisterFile.h:836
SCHEDULED_ACTION_Q_SIZE_ADDR
const uint32_t SCHEDULED_ACTION_Q_SIZE_ADDR
Indicates the number of Scheduled Action Commands that can be queued (size of the queue).
Definition: RegisterFile.h:481
U3V_SIRM_CTRL_ADDR
const uint32_t U3V_SIRM_CTRL_ADDR
Definition: RegisterFile.h:589
TIMESTAMP_FREQ_HIGH_ADDR
const uint32_t TIMESTAMP_FREQ_HIGH_ADDR
This register indicates the number of timestamp tick during 1 second. This corresponds to the timesta...
Definition: RegisterFile.h:469
SENSOR_TEMPERATURE_ADDR
const uint32_t SENSOR_TEMPERATURE_ADDR
Definition: RegisterFile.h:634
SENS_SPECIFIC_FLOAT_4_ADDR
const uint32_t SENS_SPECIFIC_FLOAT_4_ADDR
Definition: RegisterFile.h:866
VERSION_ADDR
const uint32_t VERSION_ADDR
This register indicates the version of the GigE Vision specification implemented by this device....
Definition: RegisterFile.h:441
SENSOR_WIDTH_ADDR
const uint32_t SENSOR_WIDTH_ADDR
SFNC 4.2 SensorWidth - Effective width of sensor in pixels.
Definition: RegisterFile.h:659
NB_INTERFACES_ADDR
const uint32_t NB_INTERFACES_ADDR
This register indicates the number of physical network interfaces supported by this device....
Definition: RegisterFile.h:458
SENS_SPECIFIC_FLOAT_2_ADDR
const uint32_t SENS_SPECIFIC_FLOAT_2_ADDR
Definition: RegisterFile.h:864
SCSP0_ADDR
const uint32_t SCSP0_ADDR
This register indicates the source port of the GVSP stream.
Definition: RegisterFile.h:494
USER_OUTPUT_SELECTOR_ADDR
const uint32_t USER_OUTPUT_SELECTOR_ADDR
Definition: RegisterFile.h:799
GAIN_ADDR
const uint32_t GAIN_ADDR
Definition: RegisterFile.h:687
ABRM_DEVICE_VERSION_ADDR
const uint32_t ABRM_DEVICE_VERSION_ADDR
Definition: RegisterFile.h:504
SENS_SPECIFIC_12_ADDR
const uint32_t SENS_SPECIFIC_12_ADDR
Definition: RegisterFile.h:843
ROI_HEIGHT_ADDR
const uint32_t ROI_HEIGHT_ADDR
SFNC 4.19 Height - This register sets the height of the ROI.
Definition: RegisterFile.h:619
PHY_CONFIG_ADDR
const uint32_t PHY_CONFIG_ADDR
Indicates the currently active physical link configuration.
Definition: RegisterFile.h:479
NB_ACTIVE_LINKS_ADDR
const uint32_t NB_ACTIVE_LINKS_ADDR
This register reports the number of physical links that are currently active.
Definition: RegisterFile.h:464
SENS_SPECIFIC_16_ADDR
const uint32_t SENS_SPECIFIC_16_ADDR
Definition: RegisterFile.h:847
DIGITAL_IO_LINE_STATUS_ADDR
const uint32_t DIGITAL_IO_LINE_STATUS_ADDR
Definition: RegisterFile.h:801
BOARD_TEMPERATURE_ADDR
const uint32_t BOARD_TEMPERATURE_ADDR
Definition: RegisterFile.h:635
REVERSE_Y_ADDR
const uint32_t REVERSE_Y_ADDR
SFNC 4.34 ReverseY - "Bool" that flips Y when true.
Definition: RegisterFile.h:629
ABRM_TIMESTAMP_LATCH_ADDR
const uint32_t ABRM_TIMESTAMP_LATCH_ADDR
Definition: RegisterFile.h:516
MANIFEST_TABLE_ADDR
const uint32_t MANIFEST_TABLE_ADDR
Definition: RegisterFile.h:497
HDMI_START_ADDR
const uint32_t HDMI_START_ADDR
Definition: RegisterFile.h:900
U3V_PAYLOAD_COUNT_ADDR
const uint32_t U3V_PAYLOAD_COUNT_ADDR
Definition: RegisterFile.h:595
CURRENT_GATEWAY0_ADDR
const uint32_t CURRENT_GATEWAY0_ADDR
This register indicates the default gateway IP address to be used on the given network interface.
Definition: RegisterFile.h:449
GVCP_CONFIGURATION_ADDR
const uint32_t GVCP_CONFIGURATION_ADDR
Definition: RegisterFile.h:474
MANIFEST_TYPE_ADDR
const uint32_t MANIFEST_TYPE_ADDR
Definition: RegisterFile.h:888
SENS_SPECIFIC_22_ADDR
const uint32_t SENS_SPECIFIC_22_ADDR
Definition: RegisterFile.h:853
ABRM_SBRM_ADDRESS_ADDR
const uint32_t ABRM_SBRM_ADDRESS_ADDR
Definition: RegisterFile.h:511
TEST_PATTERN_ADDR
const uint32_t TEST_PATTERN_ADDR
Definition: RegisterFile.h:641
VOLTAGE_SENSOR_VALUE_ADDR
const uint32_t VOLTAGE_SENSOR_VALUE_ADDR
retrieves selected ADC voltage sensor value
Definition: RegisterFile.h:652
SENS_SPECIFIC_FLOAT_1_ADDR
const uint32_t SENS_SPECIFIC_FLOAT_1_ADDR
Definition: RegisterFile.h:863
PHY_CAPABILITY_ADDR
const uint32_t PHY_CAPABILITY_ADDR
Indicates the physical link configuration supported by this device.
Definition: RegisterFile.h:478
FIRST_URL_ADDR
const uint32_t FIRST_URL_ADDR
This register stores the first URL to the XML device description file. This URL must be used as the f...
Definition: RegisterFile.h:456
U3V_SIRM_LENGTH_ADDR
const uint32_t U3V_SIRM_LENGTH_ADDR
Definition: RegisterFile.h:555
ABRM_HEARTBEAT_TIMEOUT_ADDR
const uint32_t ABRM_HEARTBEAT_TIMEOUT_ADDR
Definition: RegisterFile.h:513
HDMI_OFFSET_X_ADDR
const uint32_t HDMI_OFFSET_X_ADDR
Definition: RegisterFile.h:902
ABRM_DEVICE_CAPABILITY_ADDR
const uint32_t ABRM_DEVICE_CAPABILITY_ADDR
Definition: RegisterFile.h:508
ROI_OFFSET_Y_ADDR
const uint32_t ROI_OFFSET_Y_ADDR
SFNC 4.21 OffsetY - This register stores the starting row of the ROI.
Definition: RegisterFile.h:621
DEVICE_FIRMWARE_VERSION_ADDR
const uint32_t DEVICE_FIRMWARE_VERSION_ADDR
Definition: RegisterFile.h:609
REVERSE_X_ADDR
const uint32_t REVERSE_X_ADDR
SFNC 4.33 ReverseX - "Bool" that flips X when true.
Definition: RegisterFile.h:628
PENDING_TIMEOUT_ADDR
const uint32_t PENDING_TIMEOUT_ADDR
Pending Timeout to report the longest GVCP command execution time before issuing a PENDING_ACK....
Definition: RegisterFile.h:475
ABRM_MAX_DEVICE_RESPONSE_TIME_ADDR
const uint32_t ABRM_MAX_DEVICE_RESPONSE_TIME_ADDR
Definition: RegisterFile.h:509
CURRENT_SUBNET0_ADDR
const uint32_t CURRENT_SUBNET0_ADDR
This register provides the subnet mask of the given interface.
Definition: RegisterFile.h:448
TIMESTAMP_CTRL_ADDR
const uint32_t TIMESTAMP_CTRL_ADDR
This register is used to control the timestamp counter.
Definition: RegisterFile.h:471
SCP0_ADDR
const uint32_t SCP0_ADDR
This register provides port information for this stream channel. The stream channel is activated when...
Definition: RegisterFile.h:490
HDMI_WBBLUE_ADDR
const uint32_t HDMI_WBBLUE_ADDR
Definition: RegisterFile.h:911
ABRM_TIMESTAMP_ADDR
const uint32_t ABRM_TIMESTAMP_ADDR
Definition: RegisterFile.h:515
U3V_CURRENT_SPEED_ADDR
const uint32_t U3V_CURRENT_SPEED_ADDR
Definition: RegisterFile.h:559
DEVICE_MAC_LOW0_ADDR
const uint32_t DEVICE_MAC_LOW0_ADDR
This register stores the MAC address (lower 32-bit) of the given network interface.
Definition: RegisterFile.h:444
IEEE_1588_STATUS_ADDR
const uint32_t IEEE_1588_STATUS_ADDR
Reports the state of the IEEE 1588 clock.
Definition: RegisterFile.h:480
HDMI_OFFSET_Y_ADDR
const uint32_t HDMI_OFFSET_Y_ADDR
Definition: RegisterFile.h:903
SECOND_URL_ADDR
const uint32_t SECOND_URL_ADDR
This register stores the second URsi_meL to the XML device description file. This URL is an alternati...
Definition: RegisterFile.h:457
DEBUG_BUFFER_BYTESWRITTEN_ADDR
const uint32_t DEBUG_BUFFER_BYTESWRITTEN_ADDR
Definition: RegisterFile.h:881
SENS_SPECIFIC_2_ADDR
const uint32_t SENS_SPECIFIC_2_ADDR
Definition: RegisterFile.h:833
ACQUISITION_NUM_FRAMES_ADDR
const uint32_t ACQUISITION_NUM_FRAMES_ADDR
SFNC 5.5.4 AquisitionFrameCount - Number of frames to be captured in MultiFrame mode.
Definition: RegisterFile.h:630
LUT_VALUE_ADDR
const uint32_t LUT_VALUE_ADDR
Definition: RegisterFile.h:672
SCPD0_ADDR
const uint32_t SCPD0_ADDR
This register indicates the delay (in timestamp counter unit) to insert between each packet for this ...
Definition: RegisterFile.h:492
TRIGGER_MODE_ADDR
const uint32_t TRIGGER_MODE_ADDR
Definition: RegisterFile.h:764
U3V_PAYLOAD_FINAL2_ADDR
const uint32_t U3V_PAYLOAD_FINAL2_ADDR
Definition: RegisterFile.h:597
AQUISITION_FRAMERATE_ADDR
const uint32_t AQUISITION_FRAMERATE_ADDR
This register controls the acquisition rate. This is actually the frame interval in usecs.
Definition: RegisterFile.h:616
MODEL_NAME_ADDR
const uint32_t MODEL_NAME_ADDR
This registers stores a string containing the device model name. This string uses the character set i...
Definition: RegisterFile.h:451
DEVICE_TEMPERATURE_SELECT_ADDR
const uint32_t DEVICE_TEMPERATURE_SELECT_ADDR
SFNC 3.60 DeviceTemperatureSelector.
Definition: RegisterFile.h:654
SENS_SPECIFIC_23_ADDR
const uint32_t SENS_SPECIFIC_23_ADDR
Definition: RegisterFile.h:854
MCTT_ADDR
const uint32_t MCTT_ADDR
This register provides the transmission timeout value in milliseconds. This indicates the amount of t...
Definition: RegisterFile.h:487
TRIGGER_ACTIVATION_ADDR
const uint32_t TRIGGER_ACTIVATION_ADDR
Definition: RegisterFile.h:766
DIGITAL_IO_LINE_SOURCE_ADDR
const uint32_t DIGITAL_IO_LINE_SOURCE_ADDR
Definition: RegisterFile.h:798
SHUTTER_MODE_ADDR
const uint32_t SHUTTER_MODE_ADDR
Definition: RegisterFile.h:637
SENS_WRITE_ADDR
const uint32_t SENS_WRITE_ADDR
Definition: RegisterFile.h:827
PERSISTENT_IP_ADDR0_ADDR
const uint32_t PERSISTENT_IP_ADDR0_ADDR
This register indicates the Persistent IP address for this network interface. It is only used when th...
Definition: RegisterFile.h:459
MANUFACTURER_INFO_ADDR
const uint32_t MANUFACTURER_INFO_ADDR
This register stores a string containing additional manufacturer-specific information about the devic...
Definition: RegisterFile.h:453
U3V_CP_CONFIGURATION_ADDR
const uint32_t U3V_CP_CONFIGURATION_ADDR
Definition: RegisterFile.h:550
DIGITAL_IO_LINE_SELECT_ADDR
const uint32_t DIGITAL_IO_LINE_SELECT_ADDR
Definition: RegisterFile.h:796
EXPOSURE_TIME_SELECT_ADDR
const uint32_t EXPOSURE_TIME_SELECT_ADDR
SFNC 5.7.3 ExposureTimeSelector - This optional register allows selecting different exposure times (s...
Definition: RegisterFile.h:657
SENS_SPECIFIC_15_ADDR
const uint32_t SENS_SPECIFIC_15_ADDR
Definition: RegisterFile.h:846
SENS_READ_ADDR
const uint32_t SENS_READ_ADDR
Definition: RegisterFile.h:826
SENS_SPECIFIC_7_ADDR
const uint32_t SENS_SPECIFIC_7_ADDR
Definition: RegisterFile.h:838
HOT_PIXEL_CORRECT_ADDR
const uint32_t HOT_PIXEL_CORRECT_ADDR
Definition: RegisterFile.h:646
HDMI_GAMMA_ADDR
const uint32_t HDMI_GAMMA_ADDR
Definition: RegisterFile.h:908
SENS_SPECIFIC_14_ADDR
const uint32_t SENS_SPECIFIC_14_ADDR
Definition: RegisterFile.h:845
ACQUISITION_START_ADDR
const uint32_t ACQUISITION_START_ADDR
SFNC 5.5.3 AcquisitionStart - Start/stop image acquisition using the specified acquision mode in the ...
Definition: RegisterFile.h:622
TRIGGER_SELECTOR_ADDR
const uint32_t TRIGGER_SELECTOR_ADDR
Definition: RegisterFile.h:763
SENS_SPECIFIC_21_ADDR
const uint32_t SENS_SPECIFIC_21_ADDR
Definition: RegisterFile.h:852
SCPS0_ADDR
const uint32_t SCPS0_ADDR
This register indicates the packet size in bytes for this stream channel. This is the total packet si...
Definition: RegisterFile.h:491
DEVICE_VERSION_ADDR
const uint32_t DEVICE_VERSION_ADDR
This register stores a string containing the version of the device. This string uses the character se...
Definition: RegisterFile.h:452
U3V_CP_CABABILITY_ADDR
const uint32_t U3V_CP_CABABILITY_ADDR
Definition: RegisterFile.h:549
FREE_RAM_CFG_ADDR
const uint32_t FREE_RAM_CFG_ADDR
Definition: RegisterFile.h:662
PA_IP_ADDR
const uint32_t PA_IP_ADDR
Source IP address of the control channel of the primary application.
Definition: RegisterFile.h:484
CURRENT_IP_ADDR0_ADDR
const uint32_t CURRENT_IP_ADDR0_ADDR
This register reports the IP address for the given network interface once it has been configured.
Definition: RegisterFile.h:447
ROI_OFFSET_X_ADDR
const uint32_t ROI_OFFSET_X_ADDR
SFNC 4.20 OffsetX - This register stores the starting column of the ROI.
Definition: RegisterFile.h:620
MCDA_ADDR
const uint32_t MCDA_ADDR
This register indicates the destination IP address for the message channel.
Definition: RegisterFile.h:486
TRIGGER_SOURCE_ADDR
const uint32_t TRIGGER_SOURCE_ADDR
Definition: RegisterFile.h:765
INTERNAL_EXP_MODE_ADDR
const uint32_t INTERNAL_EXP_MODE_ADDR
Definition: RegisterFile.h:664
NB_MSG_CHANNELS_ADDR
const uint32_t NB_MSG_CHANNELS_ADDR
This register reports the number of message channel supported by this device. In the current version ...
Definition: RegisterFile.h:462
MANIFEST_TABLE_COUNT_ADDR
const uint32_t MANIFEST_TABLE_COUNT_ADDR
Definition: RegisterFile.h:886
BAD_PIXEL_CTRL_MAP_ADDR
const uint32_t BAD_PIXEL_CTRL_MAP_ADDR
Set whether to display bad pixel map (as 1s/0s) for debugging.
Definition: RegisterFile.h:649
ABRM_PROTOCOL_ENDIANESS_ADDR
const uint32_t ABRM_PROTOCOL_ENDIANESS_ADDR
Definition: RegisterFile.h:519
SENS_SPECIFIC_30_ADDR
const uint32_t SENS_SPECIFIC_30_ADDR
Definition: RegisterFile.h:861
SENS_SPECIFIC_20_ADDR
const uint32_t SENS_SPECIFIC_20_ADDR
Definition: RegisterFile.h:851
BLACK_LEVEL_AUTO_ADDR
const uint32_t BLACK_LEVEL_AUTO_ADDR
Definition: RegisterFile.h:692
TEST_PENDING_ACK_ADDR
const uint32_t TEST_PENDING_ACK_ADDR
Definition: RegisterFile.h:898
U3V_MAX_COMMAND_TRANS_ADDR
const uint32_t U3V_MAX_COMMAND_TRANS_ADDR
Definition: RegisterFile.h:551
BALANCE_RATIO_SELECTOR_ADDR
const uint32_t BALANCE_RATIO_SELECTOR_ADDR
Definition: RegisterFile.h:696
ABRM_GENCP_VERSION_ADDR
const uint32_t ABRM_GENCP_VERSION_ADDR
Definition: RegisterFile.h:500
BEYOND_MANIFEST_ADDR
const uint32_t BEYOND_MANIFEST_ADDR
Definition: RegisterFile.h:897
SENS_SPECIFIC_3_ADDR
const uint32_t SENS_SPECIFIC_3_ADDR
Definition: RegisterFile.h:834
NET_IFACE_CONFIG0_ADDR
const uint32_t NET_IFACE_CONFIG0_ADDR
This register indicates which IP configurations schemes are currently activated on the given network ...
Definition: RegisterFile.h:446
U3V_VERSION_ADDR
const uint32_t U3V_VERSION_ADDR
Definition: RegisterFile.h:548
MCP_ADDR
const uint32_t MCP_ADDR
This register provides port information about the message channel. The message channel is activated w...
Definition: RegisterFile.h:485
PERSISTENT_GATEWAY0_ADDR
const uint32_t PERSISTENT_GATEWAY0_ADDR
This register indicates the persistent default gateway for this network interface....
Definition: RegisterFile.h:461
ABRM_DEVICE_CONFIGURATION_ADDR
const uint32_t ABRM_DEVICE_CONFIGURATION_ADDR
Definition: RegisterFile.h:512
DIGITAL_IO_LINE_INVERTER_ADDR
const uint32_t DIGITAL_IO_LINE_INVERTER_ADDR
Definition: RegisterFile.h:802
SENS_SPECIFIC_11_ADDR
const uint32_t SENS_SPECIFIC_11_ADDR
Definition: RegisterFile.h:842
BINNING_HORIZONTAL_ADDR
const uint32_t BINNING_HORIZONTAL_ADDR
SFNC 4.26 BinningHorizontal - Number of pixels to bin in the horizontal direction.
Definition: RegisterFile.h:626
MANIFEST_FILE_SIZE_ADDR
const uint32_t MANIFEST_FILE_SIZE_ADDR
Definition: RegisterFile.h:890
HEARTBEAT_TIMEOUT_ADDR
const uint32_t HEARTBEAT_TIMEOUT_ADDR
This registers indicates the current heartbeat timeout in milliseconds.
Definition: RegisterFile.h:468
SENS_SPECIFIC_25_ADDR
const uint32_t SENS_SPECIFIC_25_ADDR
Definition: RegisterFile.h:856
CTRL_SWITCHOVER_KEY_ADDR
const uint32_t CTRL_SWITCHOVER_KEY_ADDR
Key to authenticate primary application switchover requests.
Definition: RegisterFile.h:476
LUT_ENABLE_ADDR
const uint32_t LUT_ENABLE_ADDR
Definition: RegisterFile.h:668
SENS_SPECIFIC_28_ADDR
const uint32_t SENS_SPECIFIC_28_ADDR
Definition: RegisterFile.h:859
ABRM_ACCESS_PRIVILEGE_ADDR
const uint32_t ABRM_ACCESS_PRIVILEGE_ADDR
Definition: RegisterFile.h:518
LUT_MAXINDEX_ADDR
const uint32_t LUT_MAXINDEX_ADDR
Definition: RegisterFile.h:669
U3V_MAX_TRAILER_SIZE_ADDR
const uint32_t U3V_MAX_TRAILER_SIZE_ADDR
Definition: RegisterFile.h:598
DEVICE_FX3_DATE_ADDR
const uint32_t DEVICE_FX3_DATE_ADDR
Definition: RegisterFile.h:614
ABRM_SERIAL_NUMBER_ADDR
const uint32_t ABRM_SERIAL_NUMBER_ADDR
Definition: RegisterFile.h:506
MCSP_ADDR
const uint32_t MCSP_ADDR
Message Channel Source Port.
Definition: RegisterFile.h:489
HDMI_TESTPATEN_ADDR
const uint32_t HDMI_TESTPATEN_ADDR
Definition: RegisterFile.h:912
DEVICE_SOFTWARE_DATE_ADDR
const uint32_t DEVICE_SOFTWARE_DATE_ADDR
Definition: RegisterFile.h:613
SCDA0_ADDR
const uint32_t SCDA0_ADDR
This register indicates the destination IP address for this stream channel.
Definition: RegisterFile.h:493
SENS_SPECIFIC_18_ADDR
const uint32_t SENS_SPECIFIC_18_ADDR
Definition: RegisterFile.h:849
WHITE_CLIP_SELECTOR_ADDR
const uint32_t WHITE_CLIP_SELECTOR_ADDR
Definition: RegisterFile.h:694
PAYLOAD_SIZE_ADDR
const uint32_t PAYLOAD_SIZE_ADDR
SFNC 25.2.5 PayloadSize - Size of frame without headers.
Definition: RegisterFile.h:625
ABRM_USER_DEFINED_NAME_ADDR
const uint32_t ABRM_USER_DEFINED_NAME_ADDR
Definition: RegisterFile.h:507
SENS_SPECIFIC_19_ADDR
const uint32_t SENS_SPECIFIC_19_ADDR
Definition: RegisterFile.h:850
USER_NAME_ADDR
const uint32_t USER_NAME_ADDR
String providing the device name.
Definition: RegisterFile.h:455
DEBUG_BUFFER_ADDR
const uint32_t DEBUG_BUFFER_ADDR
Definition: RegisterFile.h:882
HDMI_HEIGHT_ADDR
const uint32_t HDMI_HEIGHT_ADDR
Definition: RegisterFile.h:905
XML_FILE_ADDR
const uint32_t XML_FILE_ADDR
This is where the XML file is loaded into memory.
Definition: RegisterFile.h:875
U3V_EIRM_LENGTH_ADDR
const uint32_t U3V_EIRM_LENGTH_ADDR
Definition: RegisterFile.h:557
ROI_WIDTH_ADDR
const uint32_t ROI_WIDTH_ADDR
SFNC 4.18 Width - This register sets the width of the ROI.
Definition: RegisterFile.h:618
ABRM_MODEL_NAME_ADDR
const uint32_t ABRM_MODEL_NAME_ADDR
Definition: RegisterFile.h:502
HDMI_STOP_ADDR
const uint32_t HDMI_STOP_ADDR
Definition: RegisterFile.h:901
WHITE_CLIP_ADDR
const uint32_t WHITE_CLIP_ADDR
Definition: RegisterFile.h:695
SENS_SPECIFIC_1_ADDR
const uint32_t SENS_SPECIFIC_1_ADDR
Definition: RegisterFile.h:832
PIXEL_FORMAT_ADDR
const uint32_t PIXEL_FORMAT_ADDR
SFNC 4.35 PixelFormat - Contains the pixel format.
Definition: RegisterFile.h:624
HDMI_WBGREEN_ADDR
const uint32_t HDMI_WBGREEN_ADDR
Definition: RegisterFile.h:910
LUT_MAXVALUE_ADDR
const uint32_t LUT_MAXVALUE_ADDR
Definition: RegisterFile.h:671
DEVICE_MODE_ADDR
const uint32_t DEVICE_MODE_ADDR
This register indicates the character set used by the various strings present in the bootstrap regist...
Definition: RegisterFile.h:442
U3V_SIRM_INFO_ADDR
const uint32_t U3V_SIRM_INFO_ADDR
Definition: RegisterFile.h:588
GAMMA_ADDR
const uint32_t GAMMA_ADDR
Definition: RegisterFile.h:699
BLACK_LEVEL_AUTOBALANCE_ADDR
const uint32_t BLACK_LEVEL_AUTOBALANCE_ADDR
Definition: RegisterFile.h:693
COLOR_TRANSF_ENABLE_ADDR
const uint32_t COLOR_TRANSF_ENABLE_ADDR
Definition: RegisterFile.h:736
HDMI_OUTPUT_SEL_ADDR
const uint32_t HDMI_OUTPUT_SEL_ADDR
Definition: RegisterFile.h:906
MANIFEST_VER_ADDR
const uint32_t MANIFEST_VER_ADDR
Definition: RegisterFile.h:887
COLOR_TRANSF_SELECTOR_ADDR
const uint32_t COLOR_TRANSF_SELECTOR_ADDR
Definition: RegisterFile.h:735
SENS_MIN_FRAME_PERIOD_ADDR
const uint32_t SENS_MIN_FRAME_PERIOD_ADDR
Definition: RegisterFile.h:829
ABRM_MESSAGE_CHANNEL_ID_ADDR
const uint32_t ABRM_MESSAGE_CHANNEL_ID_ADDR
Definition: RegisterFile.h:514
IS_CAMERA_COLOR_ADDR
const uint32_t IS_CAMERA_COLOR_ADDR
True if this is a color capable camera.
Definition: RegisterFile.h:822
SENS_SPECIFIC_6_ADDR
const uint32_t SENS_SPECIFIC_6_ADDR
Definition: RegisterFile.h:837
NET_IFACE_CAPABILITY0_ADDR
const uint32_t NET_IFACE_CAPABILITY0_ADDR
This register indicates the IP configuration scheme supported on the given network interface....
Definition: RegisterFile.h:445
DIGITAL_IO_LINE_MODE_ADDR
const uint32_t DIGITAL_IO_LINE_MODE_ADDR
Definition: RegisterFile.h:797
ABRM_TIMESTAMP_INCREMENT_ADDR
const uint32_t ABRM_TIMESTAMP_INCREMENT_ADDR
Definition: RegisterFile.h:517