U3VRegisters.h

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/*
 * GigERegisters.h
 *
 *  Created on: Oct 3, 2017
 *      Author: mitydsp
 */
 
#include "RegisterFile.h"
 
#ifndef U3VREGISTERS_H_
#define U3VREGISTERS_H_
 
namespace U3VRegisters {
 
#define GENCP_VERSION       (0x00010000)
 
#define FX3_ALIGNMENT_COUNT (2)
static const uint32_t FX3_ALIGNMENT = (2 << (FX3_ALIGNMENT_COUNT-1));
 
// IMPORTANT: Registers must be in monotonically increasing address order.
 
static SocCamera::tcRegisterFile::tsRegDefinition u3vregs[] =
{
 
        REGDEF_INT(ABRM_GENCP_VERSION            , RO, GENCP_VERSION),
        REGDEF_STR(ABRM_MANUFACTURER_NAME        , RO, 64, "Critical Link LLC"),
        // These should get loaded/copied from a file at startup during U3V init function.
        REGDEF_STR(ABRM_MODEL_NAME               , RO, 64, "CMV8000"),
        REGDEF_STR(ABRM_FAMILY_NAME              , RO, 64, "MityCAM"),
        REGDEF_STR(ABRM_DEVICE_VERSION           , RO, 64, "0"),
        REGDEF_STR(ABRM_MANUFACTURER_INFO        , RO, 64, "The best camera's in town."),
        REGDEF_STR(ABRM_SERIAL_NUMBER            , RO, 64, "Fake42"),
        REGDEF_STR(ABRM_USER_DEFINED_NAME        , RW, 64, ""), // Conditional register: we won't support this to start.
        REGDEF_I64(ABRM_DEVICE_CAPABILITY        , RO, U3V_DEVICE_CAPABILITY), // Define the device capabilities; defaults to the minimum set of that used by the standard
        REGDEF_INT(ABRM_MAX_DEVICE_RESPONSE_TIME , RO, 1000),
        REGDEF_I64(ABRM_MANIFEST_TABLE_ADDRESS   , RO, MANIFEST_TABLE_ADDR), // Use the existing manifest table.
        REGDEF_I64(ABRM_SBRM_ADDRESS             , RO, SBRM_TABLE_ADDR),
        REGDEF_I64(ABRM_DEVICE_CONFIGURATION     , RW, U3V_DEVICE_CONFIGURATION),
        REGDEF_INT(ABRM_HEARTBEAT_TIMEOUT        , RW, 0),
        REGDEF_INT(ABRM_MESSAGE_CHANNEL_ID       , RW, 0),
 
        REGDEF_I64(ABRM_TIMESTAMP                , RO, 0),
        REGDEF_INT(ABRM_TIMESTAMP_LATCH          , RW, 0),
        REGDEF_I64(ABRM_TIMESTAMP_INCREMENT      , RO, 100), // FIXME: There is some kind of precision/accuracy issue latching the result in a timely fashion so this continues to fail the precision test
        REGDEF_INT(ABRM_ACCESS_PRIVILEGE         , RW, 0),
 
        REGDEF_INT(ABRM_PROTOCOL_ENDIANESS       , RW, GENCP_LITTLE_ENDIAN),
        REGDEF_INT(ABRM_IMPLEMENTATION_ENDIANESS , RW, GENCP_LITTLE_ENDIAN),
 
        REGDEF_INT(U3V_VERSION              , RO, U3V_VERSION),
        REGDEF_I64(U3V_CP_CABABILITY        , RO, U3V_CP_CAPABILITY),
        REGDEF_I64(U3V_CP_CONFIGURATION     , RW, U3V_CP_CONFIGURATION),
        REGDEF_INT(U3V_MAX_COMMAND_TRANS    , RO, U3V_MAX_CMD_LEN),
        REGDEF_INT(U3V_MAX_ACK_TRANS        , RO, U3V_MAX_ACK_LEN),
        REGDEF_INT(U3V_NB_STRTEAM           , RO, U3V_NB_STREAMS),
        REGDEF_I64(U3V_SIRM_ADDRESS         , RO, U3V_SIRM_TABLE_ADDR),
        REGDEF_INT(U3V_SIRM_LENGTH          , RO, U3V_SIRM_LENGTH),
        REGDEF_I64(U3V_EIRM_ADDRESS         , RO, 0),
        REGDEF_INT(U3V_EIRM_LENGTH          , RO, 0),
        REGDEF_I64(U3V_IIDC2_ADDRESS        , RO, 0),
        REGDEF_INT(U3V_CURRENT_SPEED        , RO, 0),
        
        REGDEF_INT(U3V_SIRM_INFO, RO, (FX3_ALIGNMENT_COUNT << 24)), // 4 byte alignment
        REGDEF_INT(U3V_SIRM_CTRL, RW, 0),
        REGDEF_I64(U3V_REQ_PAYLOAD_SIZE, RO, 0),    // To be set/updated based on the frame parameters.
        REGDEF_INT(U3V_REQ_LEADER_SIZE, RO, U3V_MAX_HEADER),
        REGDEF_INT(U3V_REQ_TRAILER_SIZE, RO, U3V_MAX_FOOTER),
        REGDEF_INT(U3V_MAX_LEADER, RW, 0),
        REGDEF_INT(U3V_PAYLOAD_SIZE, RW, 0),
        REGDEF_INT(U3V_PAYLOAD_COUNT, RW, 0),
        REGDEF_INT(U3V_PAYLOAD_FINAL1, RW, 0),
        REGDEF_INT(U3V_PAYLOAD_FINAL2, RW, 0),
        REGDEF_INT(U3V_MAX_TRAILER_SIZE, RW, 0),
 
#include "GenICamSharedRegs.h"
 
        REGDEF_INT(TEST_PENDING_ACK, RW, 0),
        REGDEF_INT(HDMI_START, RW, 0),
        REGDEF_INT(HDMI_STOP, RW, 0),
        REGDEF_INT(HDMI_OFFSET_X, RW, 0),
        REGDEF_INT(HDMI_OFFSET_Y, RW, 0),
        REGDEF_INT(HDMI_WIDTH, RW, 0),
        REGDEF_INT(HDMI_HEIGHT, RW, 0),
        REGDEF_INT(HDMI_OUTPUT_SEL, RW, 2),
//        REGDEF_INT(HDMI_COLOR_SEL, RW, 0), this is deprecated
        REGDEF_FLT(HDMI_GAMMA, RW, 1.0f),
        REGDEF_FLT(HDMI_WBRED, RW, 1.0f),
        REGDEF_FLT(HDMI_WBGREEN, RW, 1.0f),
        REGDEF_FLT(HDMI_WBBLUE, RW, 1.0f),
        REGDEF_INT(HDMI_TESTPATEN, RW, 0),
 
        REGDEF_END_OF_TABLE
};
 
}
 
#endif /* U3VREGISTERS_H_ */