Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

--- Title:IndustrialIO_top.vhd

--- Description: 

---

---     o  0

---     | /       Copyright (c) 2010

---    (CL)---o   Critical Link, LLC

---      \

---       O

---

--- Company: Critical Link, LLC.

--- Date: 03/7/2010

--- Version: 1.20

---

--- Revision History

---   1.00 - Initial revision

---   1.10 - REVISION TO AGREE WITH CUSTOM BOARD ANALOG1

---   1.20 - REVISION FOLLOWING GREGORY GLUSZEK (CL) SUGGESTIONS about GPIOS.

library WORK;

library IEEE;

library UNISIM;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use UNISIM.VCOMPONENTS.ALL;

use WORK.MityDSP_L138_pkg.ALL;

entity PQMUIO_top is

   generic ( BOARD_REV     : string := "C"; -- "A", "B", or "C"

             DECODE_BITS   : integer range 1 to 9 := 9;

             CAMERA_CONFIG : string := "NONE"; -- "RAW" - route camera I/O hack to RAW Video input interface 

             DISP_CONFIG   : string := "LCD"; -- "LCD", "DVI" or "NONE"

             LCD_TYPE      : string := "SHARP"  -- "SHARP" or "NEC"

   );

   port (

      i_ema_clk	      : in std_logic; -- 100 MHz EMIF clock

      -- DSP EMIFA BUS Interface

      i_ema_cs0_n   : in std_logic; -- RESERVED for SDRAM Controller

      i_ema_cs2_n   : in std_logic; -- ARM core CE space

      i_ema_cs3_n   : in std_logic; -- NAND FLASH space, not used

      i_ema_cs4_n   : in std_logic; -- DSP core CE space

      i_ema_cs5_n   : in std_logic; -- Reserved core space, not used

      i_ema_oe_n    : in std_logic;

      i_ema_we_n    : in std_logic;

      io_ema_wait_n : inout std_logic_vector(1 downto 0);

      io_ema_d      : inout std_logic_vector(15 downto 0);

      i_ema_a       : in std_logic_vector(13 downto 0);

      i_ema_ba      : in std_logic_vector(1 downto 0);

      i_ema_wen_dqm : in std_logic_vector(1 downto 0); 

      i_ema_cas     : in std_logic; -- reserved for SDRAM controller, not used

      i_ema_ras     : in std_logic; -- reserved for SDRAM controller, not used

      i_ema_sdcke   : in std_logic; -- reserved for SDRAM controller, not used

      i_ema_rnw     : in std_logic; -- reserved for SDRAM controller, not used    

      -- DSP IRQ lines

      o_nmi_n       : out std_logic;

      o_int         : out std_logic_vector(1 downto 0);

		-- dac cal&offset control signals 

		o_dac_cal_ctrl: out std_logic_vector(5 downto 0);

		-- ext gpio control signals

		o_ext_gpio: out std_logic_vector(1 downto 0);

		-- ia write enable signals

		o_ia_wr: out std_logic_vector(3 downto 0);

		-- channel configuration control signals

		o_chann_config: out std_logic_vector(2 downto 0);

		-- FSPI_1 signals

		o_fspi1_mosi: out std_logic;

		i_fspi1_miso: in std_logic;

		o_fspi1_clk: out std_logic;

		o_fspi1_cs: out std_logic_vector (7 downto 0);

		-- FSPI_2 signals

		o_fspi2_mosi: out std_logic;

		i_fspi2_miso: in std_logic;

		o_fspi2_clk: out std_logic;

		o_fspi2_cs: out std_logic_vector (7 downto 0);

		-- sampling clock manager

		i_from_out_conv: in std_logic;

		o_to_in_conv: out std_logic

  );

end PQMUIO_top;

architecture rtl of PQMUIO_top is

...

...

--NEW SIGNALS I ADDED

signal s_dac_cal_ctrl : std_logic_vector(5 downto 0);

signal s_ext_gpio : std_logic_vector(1 downto 0);

signal s_ia_wr : std_logic_vector(3 downto 0);

signal s_chann_config : std_logic_vector(2 downto 0);

begin -- architecture: rtl

-------------------------------------------------------------------------

-- DAC CALIBRATION CONTROL GPIO CORE

-------------------------------------------------------------------------

dac_cal_ctrl_inst: gpio 

generic map(

NUM_BANKS => 1,

NUM_IO_PER_BANK =>6

)

port map(

      clk             => ema_clk,

      i_ABus          => addr_r,

      i_DBus          => edi_r,

      o_DBus          => edo_arm(CORE_DAC_CAL_CTRL_MODULE),

      i_wr_en         => wr_r,

      i_rd_en         => rd_r,

      i_cs            => arm_cs5_r(CORE_DAC_CAL_CTRL_MODULE),

      o_irq           => irq_map(CORE_DAC_CAL_CTRL_IRQ_LEVEL)(CORE_DAC_CAL_CTRL_IRQ_VECTOR),

      i_ilevel        => conv_std_logic_vector(CORE_DAC_CAL_CTRL_IRQ_LEVEL, 2),     

      i_ivector       => conv_std_logic_vector(CORE_DAC_CAL_CTRL_IRQ_VECTOR, 4),   

      i_io            => s_dac_cal_ctrl, -- GPIO read values. Loop back output values so they can be read from software.

      t_io            => open,-- Do not care about direction of GPIOs

      o_io            => s_dac_cal_ctrl,-- GPIO write value

      i_initdir       => "111111",

      i_initoutval    => "000000"	

);

o_dac_cal_ctrl <= s_dac_cal_ctrl;

...

...

end rtl;