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-- Company:
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-- Engineer:
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--
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-- Create Date: 14:44:44 03/27/2014
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-- Design Name:
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-- Module Name: clock - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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library UNISIM;
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use UNISIM.VComponents.all;
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entity core is
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port
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(-- Clock in ports
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CLK_IN1 : in std_logic;
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-- Clock out ports
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CLK_OUT1 : out std_logic; -- Multiplied clock
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CLK_OUT2 : out std_logic; -- Buffered Clock
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ADC_CLK_OUT : out std_logic;
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-- Status and control signals
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RESET : in std_logic;
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INPUT_CLK_STOPPED : out std_logic;
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LOCKED : out std_logic
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);
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end core;
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architecture clock_gen of core is
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attribute CORE_GENERATION_INFO : string;
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attribute CORE_GENERATION_INFO of clock_gen : architecture is "core,clk_wiz_v3_6,{component_name=core,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=151.515151515,clkin2_period=151.515151515,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=true,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
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-- Input clock buffering / unused connectors
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signal clkin1 : std_logic;
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-- Output clock buffering
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signal clk_out1_internal : std_logic;
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signal clk_out2_internal : std_logic;
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signal clkfb : std_logic;
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signal clkfx : std_logic;
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signal clk0 : std_logic;
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signal clk1 : std_logic;
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signal clkfbout : std_logic;
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signal locked_internal : std_logic;
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signal status_internal : std_logic_vector(7 downto 0);
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begin
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-- Input buffering
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--------------------------------------
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clkin1_buf : IBUFG
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port map
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(O => clkin1,
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I => CLK_IN1);
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ADC_CLK_OUT<= clkin1;
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-- -- Clocking primitive
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-- --------------------------------------
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--
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-- -- Instantiation of the DCM primitive
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-- -- * Unused inputs are tied off
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-- -- * Unused outputs are labeled unused
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dcm_sp_inst: DCM_SP
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generic map
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(CLKDV_DIVIDE => 2.000,
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CLKFX_DIVIDE => 1,
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CLKFX_MULTIPLY => 2,
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CLKIN_DIVIDE_BY_2 => FALSE,
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CLKIN_PERIOD => 151.515151515,
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CLKOUT_PHASE_SHIFT => "NONE",
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CLK_FEEDBACK => "1X",
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DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
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PHASE_SHIFT => 0,
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STARTUP_WAIT => FALSE)
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port map
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-- Input clock
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(CLKIN => clkin1,
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CLKFB => clkfb,
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-- Output clocks
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CLK0 => clk0,
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CLK90 => open,
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CLK180 => open,
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CLK270 => open,
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CLK2X => open,
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CLK2X180 => open,
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CLKFX => clkfx,
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CLKFX180 => open,
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CLKDV => open,
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-- Ports for dynamic phase shift
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PSCLK => '0',
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PSEN => '0',
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PSINCDEC => '0',
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PSDONE => open,
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-- Other control and status signals
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LOCKED => locked_internal,
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STATUS => status_internal,
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RST => RESET,
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-- Unused pin, tie low
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DSSEN => '0');
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INPUT_CLK_STOPPED <= status_internal(1);
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LOCKED <= locked_internal;
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-- Output buffering
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-------------------------------------
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clkfb <= clk_out1_internal;
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clkout1_buf : BUFG
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port map
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(O => clk_out1_internal, -- buffered
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I => clk0);
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clkout2_buf : BUFG
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port map
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(O => clk_out2_internal, -- multiplied
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I => clkfx);
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CLK_OUT2 <= clk_out1_internal; -- buffered
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CLK_OUT1 <= clk_out2_internal; -- multiplied
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end clock_gen;
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