Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

/*

 * Critical Link MityOMAP-L138 SoM Baseboard initializtaion file

 *

 */

#include <linux/kernel.h>

#include <linux/init.h>

#include <linux/gpio.h>

#include <linux/platform_device.h>

#include <linux/spi/spi.h>

#include <linux/spi/flash.h>

#include <linux/delay.h>

#include <linux/mtd/mtd.h>

#include <linux/usb/musb.h>

#include <linux/mtd/partitions.h>

#include <asm/mach-types.h>

#include <asm/mach/arch.h>

#include <asm/setup.h>

#include <mach/mux.h>

#include <mach/da8xx.h>

#include <linux/can/platform/mcp251x.h>

#define BASEBOARD_NAME "System9000 Baseboard version 0.7"

/*

*  12/16/13	Added SPI1_FPGA_CS_N, commented out GPIO(6,2) in sys9000_gpio_pins

*           Added arrays for SPI1 bus to 9000FPGA

*/

#define SPI1_FLASH_CS_N		GPIO_TO_PIN(2, 15)	// System configuration flash (optional)

#define SPI1_FPGA_CS_N		GPIO_TO_PIN(6, 2)	// SOM to FPGA SPI1 cs

/*

 * GPIO pins

 */

static short sys9000_gpio_pins[] __initdata = {

	DA850_GPIO0_1,		// SYNC_PLL_CLK2_LOS

	DA850_GPIO0_3,		// SYNC_PLL_LOL

	DA850_GPIO0_5,		// SYNC_PLL_CLK1_LOS

	DA850_GPIO0_7,		// SYNC_MASTER_EN

	DA850_GPIO0_8,		// SOM_GP0_8

	DA850_GPIO0_9,		// TEST_LED_0

	DA850_GPIO0_10,		// SYS_GOOD_LED_YEL

	DA850_GPIO0_11,		// SYS_GOOD_LED_GRN

	DA850_GPIO0_12,		// SYNC_LED_YEL

	DA850_GPIO0_13,		// SYNC_LED_GRN

	DA850_GPIO0_14,		// REC_LED_RED

	DA850_GPIO0_15,		// REC_LED_GRN

//	DA850_GPIO1_4,		// TEST_POINT_1 ...I2C0, needed for voltage regulator

//	DA850_GPIO1_5,		// TEST_POINT_0 ...I2C0

	DA850_GPIO4_0, 		// VCAL_EN

	DA850_GPIO4_1,  	// VCAL_EN_n

	DA850_GPIO4_2,		// ECAL_EN_n

	DA850_GPIO4_3,		// ECAL_EN_n

	DA850_GPIO4_4, 		// VCAL_ZERO

	DA850_GPIO4_5,  	// VCAL_OUT_EN

	DA850_GPIO4_6,		// VCAL_SPARE

	DA850_GPIO4_7,		// SSD_DET_N

	DA850_GPIO5_14,		// TEST_LED_1

	DA850_GPIO6_0,		// SOM_GP6_0

	DA850_GPIO6_1,		// SOM_GP6_1

	DA850_GPIO6_2,		// SOM_GP6_2, fpga spi cs

	DA850_GPIO6_3,		// SOM_GP6_3

	DA850_GPIO6_4,		// SOM_GP6_4

	DA850_GPIO6_6,		// SOM_GP6_6

	DA850_GPIO6_7,		// SOM_GP6_7

	DA850_GPIO6_8,		// SOM_GP6_8

	DA850_GPIO6_9,		// SOM_GP6_9

	DA850_GPIO6_10,		// SOM_GP6_10

	DA850_GPIO6_11,		// SOM_GP6_11

	DA850_GPIO7_0,		// LDAC0_n

	DA850_GPIO7_1,		// LDAC1_n

	DA850_GPIO7_2,		// LDAC2_n

	DA850_GPIO7_3,		// LDAC3_n

	DA850_GPIO7_4,		// LDAC4_n

	DA850_GPIO7_5,		// LDAC5_n

	DA850_GPIO7_6,		// LDAC6_n

	DA850_GPIO7_8,		// CARD_DET3

	DA850_GPIO7_9,		// CARD_DET2

	DA850_GPIO7_10,		// CARD_DET1

	DA850_GPIO7_11,		// CARD_DET0

	DA850_GPIO7_12,		// DIO_0_OUT

	DA850_GPIO7_13,		// DIO_0_IN

	DA850_GPIO7_14,		// DIO_1_OUT

	DA850_GPIO7_15,		// DIO_1_IN

	DA850_GPIO8_8,		// SYS_RST_N

	DA850_GPIO8_10, 	// Factory Reset In

	DA850_GPIO8_12, 	// HW_REV_0

	DA850_GPIO8_13, 	// HW_REV_1

	DA850_GPIO8_14, 	// HW_REV_2

	DA850_GPIO8_15, 	// HW_REV_3

	-1,

};

/*

 * SPI Devices:

 *	SPI1_CS1: Flash M25PE80

 */

static struct mtd_partition sys9000_spi_flash_partitions[] = {

	[0] = {

		.name		= "sys9000_fpga",

		.offset		= 0,

		.size		= SZ_4M,

	},

	[1] = {

		.name		= "sys9000_extra",

		.offset		= MTDPART_OFS_APPEND,

		.size		= MTDPART_SIZ_FULL,

	},

};

// Copied from board-mityomapl138.c in this directory

static struct flash_platform_data sys9000_spi_flash_data = {

	.name		= "m25p80",

	.parts		= sys9000_spi_flash_partitions,

	.nr_parts	= ARRAY_SIZE(sys9000_spi_flash_partitions),

	.type		= "m25p64-nonjedec",

};

static struct davinci_spi_config spi_M25PE80_config = {

	.io_type	= SPI_IO_TYPE_DMA,

	.c2tdelay	= 8,

	.t2cdelay	= 8,

};

// Added 12/16/13 SPI1 interface to Sys9000 FPGA

static struct davinci_spi_config spi_9000FPGA_config = {

	.io_type	= SPI_IO_TYPE_DMA,		// restored 04/21/14

//	.io_type	= SPI_IO_TYPE_POLL,		// Changed 02/11/14

	.c2tdelay	= 0,

	.t2cdelay	= 0,

};

static struct spi_board_info sys9000_spi1_info[] = {

	[0] = {

		.modalias		    = "m25p80",

		.platform_data		= &sys9000_spi_flash_data,

		.controller_data	= &spi_M25PE80_config,

		.mode			    = SPI_MODE_0,

		.max_speed_hz		= 30000000,

		.bus_num		    = 1,

		.chip_select		= 1,

	},

	// Added 12/16/13 user space spidev for SPI2 Cs2

	// Removed 04/21/14

//	[1] = {

//		.modalias		 = "spidev",

//		.controller_data = &spi_9000FPGA_config,

//		.max_speed_hz	 = 33000000,

//		.bus_num		 = 1,

//		.chip_select	 = 2,

//	},

};

// Added 12/16/13 SPI1_FPGA_CS_N

static u8 spi1_cs[] = {

	SPI_INTERN_CS,

	SPI1_FLASH_CS_N,

//	SPI1_FPGA_CS_N			// removed 04/21/14

};

static void __init baseboard_setup_spi(void)

{

	int ret;

	ret = gpio_request(SPI1_FLASH_CS_N, "Sys9000 SPI1 FLASH CS1\n");

	if (ret)

		pr_warning("%s: can not open Sys9000 Flash SPI CS %d\n", __func__, SPI1_FLASH_CS_N);

// Removed 04/21/14

//	ret = gpio_request(SPI1_FPGA_CS_N, "Sys9000 SPI1 Sys9000FPGA CS\n");

//	if (ret)

//		pr_warning("%s: can not open Sys9000FPGASPI CS %d\n", __func__, SPI1_FPGA_CS_N);

	ret = spi_register_board_info(sys9000_spi1_info,

					ARRAY_SIZE(sys9000_spi1_info));

	if (ret)

		pr_warning("%s: Unable to register SPI1 Info: %d\n", __func__,

				ret);

}

static int __init baseboard_pre_init(void)

{

	pr_info("%s: Entered\n", __func__);

	da8xx_spi_pdata[1].chip_sel = spi1_cs;

	da8xx_spi_pdata[1].num_chipselect = ARRAY_SIZE(spi1_cs);

	davinci_soc_info.emac_pdata->phy_id = "0:03";

	return 0;

}

postcore_initcall_sync(baseboard_pre_init);

static int __init baseboard_init(void)

{

	pr_info("%s [%s]...\n", __func__, BASEBOARD_NAME);

	davinci_cfg_reg_list(sys9000_gpio_pins);

	baseboard_setup_spi();

	return 0;

}

arch_initcall_sync(baseboard_init);