Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

Like to seek your help on an uPP related question. I plan to burst out I and Q data from memory using the two uPP channels to the FPGA. In fact, I plan to drain most of the 256MB RAM using multiple DMA calls (if required). I see from the Wiki (uPP Design Considerations) that using PLL0_SYSCLK2 is recommended, so I can do that. I can implement two FIFO in the FPGA as elastic buffer for the I/Q data and generate wait signal back to the L138 for flow control. My question is if I can rely on the data from the two uPP channels will be aligned with each other going into the two FIFO in the FPGA; or how I can make sure this will happen?

Thank you for the Wiki giving valuable advice on uPP, but seems like it is still incomplete. Do you have more information that you can update me with. I do not mind if the info is in sketch form.

Thank you in advance!