How to implement bidirectional BLVDS in the FPGA (Spartan-6 )
Added by Dene Olsen about 14 years ago
I need to implement a data bus as part of an interface to the Xilinx FPGA, and it must be a bidirectional BLVDS interface. I looked in the Xilinx document: Spartan-6 FPGA SelectIO Resources, v1.3.
On p. 37, there is a diagram that describes BLVDS output termination. However, this diagram assumes a unidirectional implementation.
Does anyone know what termination network to use (including both sides) to implement a bidirectional BLVDS data bus?
Altera FPGAs recommend 100k pullups on both ends of the bus for the p-side, 100k or 130k pulldowns on both ends of the bus for the n-side, a 100 ohm termination at both ends of the bus between the p-sides & n-sides, and 50 ohm series terminations for each p-side and n-side transceiver pin.
Thanks in advance,
Dene Olsen
Replies (1)
RE: How to implement bidirectional BLVDS in the FPGA (Spartan-6 ) - Added by Dene Olsen about 14 years ago
I received a reply back from Xilinx tech support.
They indicated that the approach for Spartan-6 would be similar to Virtex-E devices, and pointed me to an app note covering bidirectional BLVDS.
If anyone is interested, the app note is at: [[http://www.xilinx.com/support/documentation/application_notes/xapp243.pdf]]
