uPP routing
Added by Scott Whitney over 12 years ago
Hello,
We are trying to debug a uPP application and routed the chan A and Chan B signals through the fpga to connector J104. The Industrial IO data sheet lists 10 of these pins as LVDS pairs and mentions added termination resistors for these. Our fpga designer routed the Chan A signals, start, enable, wait and clock to pins 5,6,7 and 8. The clock looks terribly noisy and only at 1 kHz, I see no start, or wait, and an intermittent enable sometimes 4 msecs and sometimes 10 msecs. Could the termination resistors for these pairs have been added to out IO board? Is there any reason to believe I cannot route these signals to this connector? thanks, Scott
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