Activity
From 03/09/2014 to 04/07/2014
04/07/2014
- 12:00 PM Software Development: RE: Net: No ETH PHY detected!!!
- I used the serial flashing program to erase the memory before flashing u-boot again and this time phy eth is detected...
- Hello,
I have a mitydspl138 board. I accidentally overwrote some of the u-boot memory. I used the serial programme... - 07:43 AM FPGA Development: RE: UPP Sample Code needed
- For the FPGA interface, you could take a look at the "Vision Framework Design FIles":https://support.criticallink.com...
- 07:39 AM Software Development: RE: DSP- EDMA Transmission problem
- Hello Mr. Krawczyk,
You can interface with the UPP directly as you have described and by looking through the TRM, ...
04/03/2014
- 09:35 AM Software Development: RE: DSP- EDMA Transmission problem
- Hello Mike,
The UPP seems to be an optimal solution. However, It looks like configuring the UPP is a bit complex. I ... - Hi everyone,
I need a sample FPGA code for UPP(Supported by Critical Link) with it's UCF file(including timing const...
04/01/2014
- 05:23 PM Software Development: RE: DSP- EDMA Transmission problem
- Actually,
I was going to suggest transferring to IRAM, or if you need to transfer to DDR, doing a chained transfer... - 04:53 PM Software Development: RE: DSP- EDMA Transmission problem
- To be more precise,
Is there any way to change the EDMA3 configuration to reduce transfer time ? I want to transfer ...
03/31/2014
- 05:20 AM Software Development: RE: DSP- EDMA Transmission problem
- Hello again,
I am writing because I have the following problem:
I succesfully transfer the data, but the transfer t...
03/26/2014
- 03:16 PM Software Development: RE: DSP- EDMA Transmission problem
- Solved !
You can use the IRAM section. It is disabled as cache in the current configuration .tcf file.
Best regards
03/24/2014
- 09:57 AM Software Development: RE: GEL-file for MityDSP-L138F
- Yes. By default, the core should be 1.2V on power up.
-Mike
- Hi,
that gel-file need to use for mitydsp-L138F with 1.2 V Core?
Thanks
03/23/2014
- 08:05 PM FPGA Development: RE: Manage LX16 and LX45 at runtime
- Thanks a lot Mike!
As usual, your support is impressive!
Ticket close.
-François - 05:18 PM FPGA Development: RE: Manage LX16 and LX45 at runtime
- The model number for the part should be readable in the factory configuration information in the I2C prom. The model...
- We have a product based on MityDSP-L138F using either LX16 and LX45 fpga cores.
Q1) Can we detect which FPGA core ...
03/19/2014
- Hello everyone,
I have a MityARM 1808F and I am facing a strange issue which is as follows:
* when I am trying to c...
03/11/2014
- 05:13 PM Software Development: RE: DSP- EDMA Transmission problem
- Hello Mike,
Thank you very much for your response.
I have a question before I transfer to other place than L2 Cac...
03/10/2014
- 07:25 AM Software Development: RE: DSP- EDMA Transmission problem
- Do you see this affect if you transfer to a different place in DDR (instead of the L2 SRAM)?
Are you still enabl... - 07:19 AM Software Development: RE: DSP- EDMA Transmission problem
- Hello Michael,
It looks like edma is causing that. When I turned the edma off and used the data without transferring...
03/09/2014
- 03:44 PM Software Development: RE: DSP- EDMA Transmission problem
- It sort of sounds like there is a memory leak somewhere. Are you thinking it's in the DspQDMA routines?
-Mike - 03:29 PM Software Development: RE: DSP- EDMA Transmission problem
- Hello again,
There is another symptom in my application that occurs. I am viewing the size of heap in the MEM in the...
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