SPI Access Options

The MityDSP-L138 family of System on Modules can allow access to both of the SPI buses integrated into the OMAP-L138 processor. Please reference the OMAP-L138 CPU datasheet for further details about the SPI peripherals and pin-mux options (

For FPGA enabled MityDSP-L138F modules Critical Link provides a SPI Slave FPGA core as well as the accompanying Linux Kernel driver. This allows further SPI buses to be added to an FPGA enabled module independently from the OMAP-L138 direct ones.

On-Module OMAP-L138 SPI Bus Usage

By default all modules must use SPI1 - CS0 for the 8MB (Now 16 MB) of on-module SPI NOR memory ( This memory is typically used to store the following files; boot loader (UBL), UBoot, OS Kernel and in the case of FPGA enabled modules the FPGA image may be stored as well.

SPI1 Signals

Signal Name Module Pin CPU Ball # Note(s)
SPI1_MISO 43 H17
SPI1_MOSI 45 G17
SPI1_ENA / GP212 47 H16 Not used for SPI-NOR
SPI1_CLK 49 D19
SPI1_SCS1 51 E16 Available for user SPI device
SPI1_SCS0 53 D17 Allocated for SPI-NOR

If further chip selects are desired SPI1_SCS4 & SPI1_SCS5 are available at pins 59 and 61 as long as the other mux modes of those pins is not required. However it is possible to use ANY OMAP-L138 direct GPIO for a SPI chip select. Proper care must be taken to enter them properly in the baseboard configuration file for the kernel and/or UBoot. The Industrial IO board kernel uses the GPIO's for chip selects as an example. gitweb

SPI0 Signals

The SPI0 bus is unused by the module itself. However the SPI0 signals are all pin-muxed with MII interface signals to the OMAP-L138 CPU. The only way to access SPI0 is to drop support for MII and switch to an RMII based Ethernet phy implementation.

Here is the list of SPI0 clk and data pins:

Signal Name Module Pin CPU Ball # Note(s)

For chip selects you can either us general OMAP GPIO pins or you can use the "dedicated" chip select pins, again muxed with the MII peripheral:

Signal Name Module Pin CPU Ball # Note(s)
SPI0_SCS2 (MII_RXD0) 77 D16
SPI0_SCS3 (MII_RXD1) 79 E17
SPI0_SCS4(MII_RXD2) 81 D18
SPI0_SCS5 (MII_RXD3) 83 C19

Note that SPI0_SCS0 and SPI0_SCS1 are also the MDIO DAT and MDIO CLK signals which if using Ethernet you would want to leave as their MDIO modes.

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