Vision Framework FPGA Development¶

This page provides the instructions needed to setup an FPGA development environment for the MityDSP-L138F Vision Framework. These instructions are written up for a linux development environment, but may be applicable to a Windows environment assuming you can place the files in the MDK board support package and the vision framework tarball on a location accessible to a Windows based machine.

Install / Fetch the required tools¶

1. Install Xilinx Webpack (or ISE) version 13.2 or higher.
2. Install the MDK Board Support Package
3. Download the Vision Framework Application Tarball

Building the FPGA¶

1. untar the vision framework tarball.
   

   user @ linuxvm: tar xjf vision_framework_2011_12_05.tar.bz2
   

2. Launch the Xilinx ISE tool.
   

   user @ linuxvm : source /opt/Xilinx/13.2/ISE_DS/settings32.sh
   user @ linuxvm : ise &
   

3. Open the DVI interface project. Select File->Open Project. Navigate to vision_framework/hw/fpga/buildlx16_dvi and select the vision.xise project file. You will see a dialog, most likely, complaining about missing files. Select the base_module.vhd and click a browser and navigate to MDK_2011-12-05/fpga/vhdl and select the base_module.vhd. Several VHDL files should be automatically assigned. Now select "Remove unassigned files from project" and continue (we will fix these other issues later).
4. Add the vision_framework/hw/fpga/vhdl/EMIFA_dcm.xco file to the project.
5. Add the vision_framework/hw/fpga/vhdl/fifo_64x18.xco file to the project.
6. Add the vision_framework/hw/fpga/vhdl/upp_fifo_1Kx18.xco file to the project.
7. Set Synthesis settings to load provided netlists. Select the IndustrialIO_top.vhd file. Under the Design tab, right click on "synthesize - xst" and select "Process Properties". Set the Property display level to "Advanced". Find the "-sd Cores Search Directories" and add the folder "/path/to/MDK_2011-12-05/fpga/cores/build_spartan6".
8. Set the Implement settings to load provided netlists. Select the IndustrialIO_top.vhd file. Under the Design tab, right click on "Implement Design" and select "Process Properties". Find the "-sd Macro Search Path" and add the folder "/path/to/MDK_2011-12-05/fpga/cores/build_spartan6".
9. Rebuild the FPGA. Select Generate Programming File. Right click and run "Rerun All".

At this point, if successful, you should have a .bit file that may be used to program the FPGA via the JTAG emulator using Impact. If you want to load the FPGA at runtime in software, or via u-Boot, then you must create a .bin file from the .bit file. The steps to create the .bin file are:

1. Click on Configure Target Device and select "Generate Target PROM/ACE File". Right click and select "Run".
2. Select File->New Project. Select Create a new project and hit "OK". Select "Prepare a PROM File" and Click OK.
3. Select Generic Parallel PROM. Click the Green Right arrow.
4. Select a 512K sized PROM and click "Add Storage Device". Click the Right Arrow.
5. Change the output name to "vision.bin" and set a reasonable output file location.
6. Change the file format from "MCS" to "BIN (Swap Bits On)". Now click "OK".
7. Select the IndustrialIO_top.bit file and click "open".
8. Select "No" to adding other devices.
9. Click "OK" on the revision history dialog.
10. Finally, double-click on the "Generate File" option to create the .bin file.