Customizing the On Board Silicon Labs PLLs¶
The MitySBC-A5 includes 2 si5338 4 channel (differential) Phase Lock Loop Chips.
Each PLL chip is provided a copy of a 25 MHz reference clock that is also provided to the HPS and the SDM. The PLL chip is powered with 1.8V and uses 1.8V on the I2C control port.
The default configuration for the PLLs is as follows
| PLL Ref Des | I2C1 Address | Clock Index | Frequency (MHz) | Standard | Connection | Notes |
|---|---|---|---|---|---|---|
| U29 | 0x70 | 0 | 100 | LVDS (DC) | FPGA M105/K105 | HPS LPDDR4 EMIF Refclk |
| U29 | 0x70 | 1 | 100 | LVDS (DC) | FPGA BW78/CA78 | FPGA LPDDR4 EMIF Refclk |
| U29 | 0x70 | 2 | N/A (disabled) | LVDS (DC) | FPGA Y87/Y84 | MIPI Bank 3A Refclk |
| U29 | 0x70 | 3 | 20 | LVDS (DC) | FPGA AC68/AC72 | MIPI Bank 3B Refclk |
| U27 | 0x71 | 0 | 156.25 | LVDS (AC) | FPGA BB120/BB115 | QSFP+ RefClk |
| U27 | 0x71 | 1 | 100 | LVDS (AC) | FPGA AP120/AP115 | USB 3 SS Refclk |
| U27 | 0x71 | 2 | 150 | LVDS (AC) | FPGA AP16/AP21 | DisplayPort Refclk |
| U27 | 0x71 | 3 | N/A (disabled) | LVDS (AC) | FPGA AT120/AT115 | GXB Spare Refclk |
The root filesystem includes a perl script developed by Intel in /usr/bin/si5338_cfg to program the SI5338 device from the HPS.
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