Mity CPU Platforms » MitySOM-A5

07/13/2026

01:13 PM FPGA Development: RE: Not being able to Make jic

Good morning,
I have readded the PCIe RP IP, but it I still can't regenerate/update the a5e because the tool complai... Eleonora Haralanova

07/10/2026

03:55 PM FPGA Development: RE: Not being able to Make jic

I believe the PCIe RP IP needs to be regenerated / re-added if you switch between production silicon or R0 silicon so... Mike Fiorenza

03:36 PM FPGA Development: RE: Not being able to Make jic

Yes,
The actual label on the SOM is A5ED-B64-144-SRC-X, but the box says A5ED-B64-144-SRI-X
I checked the SBC also... Eleonora Haralanova

02:57 PM FPGA Development: RE: Not being able to Make jic

Eleonora,
Can you read the label / sticker that is on the SOM module? I believe the device you actually have insta... Mike Fiorenza

01:46 PM FPGA Development: RE: Not being able to Make jic

It actually came back with different FPGA - the one that you have
jtagconfig
1) USB-BlasterII [USB-1]
4BA06477... Eleonora Haralanova

07/09/2026

09:21 PM FPGA Development: RE: Not being able to Make jic

No the SD card is irrelevant at this stage. JTAG talks directly to the SoC device.
Have you confirmed the device y... Mike Fiorenza

09:15 PM FPGA Development: RE: Not being able to Make jic

I get the correct device
quartus_pfg -i output_files/a5e.hps.jic | grep "Device"
Device name: A5ED065BB32A
Devic... Eleonora Haralanova

08:39 PM FPGA Development: RE: Not being able to Make jic

Correction to my last statement, jtagconfig doesn't list the temperature / speed grade (because it is not a gating fa... Mike Fiorenza

08:34 PM FPGA Development: RE: Not being able to Make jic

Hi Eleonora,
Yes *A5ED065BB32AI4S* is the correct part number for *A5ED-B64-144-SRI* .
Please confirm the outpu... Mike Fiorenza

08:18 PM FPGA Development: RE: Not being able to Make jic

Hello Mike,
Deleting the u-boot-socfpga and bootloade.stamp and running make jic did give me test/ folder and produc... Eleonora Haralanova

07/08/2026

09:52 PM FPGA Development: RE: Not being able to Make jic

Hi Eleonora,
The test/Kconfig error most likely means the U-Boot source tree under software/bootloader/u-boot-socf... Mike Fiorenza

07:08 PM FPGA Development: Not being able to Make jic

Hi,
I have the example design for PCIE Rootport. It was in a special folder for my use. I made some changes and I'm... Eleonora Haralanova