MitySOM-A5E Altera Agilex 5 SOC and DevKit Wiki Page¶

• Table of contents
• MitySOM-A5E Altera Agilex 5 SOC and DevKit Wiki Page
• Repositories
• Architecture
• Development Kit
  • Pre-Built SD Card Images
  • Recommended Build Flow
• Software
  • U-Boot
• FPGA / VHDL
• Hardware Design
• Reference Material
  • FPGA/ARM
  • Software

Support is included for the MitySOM-A5. See The Critical Link website for top level summaries of this platform.

• MitySOM-A5E DataSheet [pdf]
• MitySOM-A5E Dev Board DataSheet [pdf]
• MitySOM-A5E Carrier Board Design Guide: Please contact Critical Link

Errata and Product Change Notifications for the MitySOM-A5E can be found in the Hardware Design section of this wiki.

Repositories¶

The following are links to the repositories that Critical Link provides for the kernel, u-boot, yocto, and sample project.

Type	Repo	Branch
Kernel	git://support.criticallink.com/home/git/linux-socfpga.git	socfpga-6.1.68-lts
U-Boot	git://support.criticallink.com/home/git/u-boot-socfpga.git	socfpga_v2023.10
Yocto Layer	git://support.criticallink.com/home/git/meta-mitysom.git	nanbield
Quartus Example Projects (Quartus Pro 21.3)	git://support.criticallink.com/home/git/mitysom-a5e-ref.git	24.1pro-stable

Architecture¶

• MitySOM-A5E Architecture
• MitySOM-A5E Development Kit Architecture

Development Kit¶

• Development Board Schematics and Revision Information
• Development Board Interface Validation Status

Pre-Built SD Card Images¶

The following are links to pre-built binaries for the development SD card image for each SOM. Each also includes each built versions of the preloader, uboot, and root filesystem for each image.

• Quartus Pro 24.1 2024/TBD

Recommended Build Flow¶

• Prerequisites
• Building the FPGA
• Building the Bootloader(U-Boot)
• Building the Filesystem
• Building the SD Card Image

Software¶

• Boot Media
• JTAG Debug Interface
• SOM Temperature Sensor
• Building the Linux Kernel for MitySOM-A5E outside of Yocto

U-Boot¶

FPGA / VHDL¶

• FPGA Overview
• Example Projects
• On-SoM Clocks
• Programming the DevKit Silicon Labs PLL

Hardware Design¶

• Errata and Module Product Change Notifications
• Power Supply Requirements
• Mounting Hole Locations
• Power Supply and Heat Dissipation
• CAD Files and Information
• Connector Information
• MitySOM-A5E Pin-Out Spreadsheet
• KSZ RGMII Phy Design Considerations

Reference Material¶

FPGA/ARM¶

Software¶

• Yocto Project Mega-Manual
• Critical Link U-Boot Repo
• Critical Link Kernel Repo
• Yocto Project

Updated 12 days ago by Daniel Vincelette

Recent Updates: