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MitySOM-A5E FPGA Signal Routing Delays

MitySOM-A5E Standard

General Notes Regarding FPGA Signal Routing to the SEAM Connectors (J1 and J2) for the MitySOM-A5E Standard module:
  • All differential pairs target < 5 mil variance between the P and N signal
  • FPGA IO pins are length matched among the following groups to a target of < 5 mil
    • HSIO Bank 3A Pins
    • HSIO Bank 2A Top sub-bank pins
    • HSIO Bank 2A Bottom sub-bank pins
    • HSIO Bank 2B Top sub-bank pins
    • HSIO Bank 2B Bottom sub-bank pins
    • HPS GPIO0 pins
    • HPS GPIO1 pins
    • HVIO Bank 5A pins
    • HVIO Bank 5B pins
    • HVIO Bank 6A pins
    • HVIO Bank 6B pins
    • HVIO Bank 6C pins
    • HVIO Bank 6D pins
  • Transceiver Lanes and reference clock lanes are not group matched, only P/N matched.

The J1_J2_to_FPGA_IO_MitySOM-A5E_Standard_Rev1.xlsx spreadsheet includes detailed routing delay information for all the FPGA IO pins that are directly connected to the SEAM interface connectors for revision -1 of the MitySOM-A5E Standard PCAs.

The J1_J2_to_FPGA_IO_MitySOM-A5E_Standard_Rev2.xlsx spreadsheet includes detailed routing delay information for all the FPGA IO pins that are directly connected to the SEAM interface connectors for revision -2 of the MitySOM-A5E Standard PCAs.

MitySOM-A5E Mini

General Notes Regarding FPGA Signal Routing to the SEAM Connectors (J1 and J2) for the MitySOM-A5E Standard module:
  • All differential pairs target < 5 mil variance between the P and N signal
  • FPGA IO pins are length matched among the following groups to a target of < 5 mil
    • HSIO Bank 3A Pins
    • HPS GPIO0 pins
    • HPS GPIO1 pins
  • Transceiver Lanes and reference clock lanes are not group matched, only P/N matched.

Note that due to the size limitations of the MitySOM Mini, the HVIO banks are not tightly length matched. If you are designing a highspeed interface on the MitySOM-A5E Mini HVIO banks, you should review the spreadsheet mentioned below and consider accounting for skew difference on your carrier board design.

The J1_to_FPGA_IO_MitySOM_A5E-Mini_Rev2.xlsx spreadsheet includes detailed routing delay information for all the FPGA IO pins that are directly connected to the SEAM interface connectors for revision -2 of the MitySOM-A5E Mini PCAs.

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