Programming the DevKit Skyworks PLL¶

MitySOM-A5E Standard Development Kit¶

The MitySOM-A5E Standard Development Kit carrier card includes an SI5332A-D-GM3 12 channel Phase Lock Loop clock generation chip.

The PLL chip is provided a (coherent) copy of the 25 MHz reference clock sourced by the MitySOM-A5E Standard. This same clock is also fed back to the SOM on an HPS IO pin to support clocking the HPS and it's PLLs. The PLL chip is powered with 1.8V and uses 1.8V on the I2C control port.

The PLL chip is not pre-programmed on the carrier card. The PLL chip should be programmed using the I2C interface. Several, including the base, reference projects include a uBoot script ("config_pll.scr") that will program and enable the output clocks according to the table below:

PLL Ref Des	I2C_EMAC1_SDA Address	Clock Index	Frequency	Standard	Connection	Notes
U68	0x6A	0	150 MHz	HCSL	REFCLK_GTSR4A_RX_P/N	For Display Port
U68	0x6A	1	N/A	Disabled	REFCLK_GTSR4C_CH1_P/N	Can be enabled for FMC GTS clocking
U68	0x6A	2	156.25 MHz	HCSL	REFCLK_GTSL1C_CH1_P/N	To Support SFP+ operation
U68	0x6A	3	N/A	Disabled	REFCLK_GTSL1B_RX_P/N	Spare
U68	0x6A	4	N/A	Disabled	REFCLK_GTSR4B_RX_P/N	Can be enabled for FMC GTS clocking
U68	0x6A	5	100 MHz	HCSL	REFCLK_GTSL1C_RX_P/N	To support USB3, M.2 M-key and M.2 E-key PCIe
U68	0x6A	6	125 MHz	LVDS	HSIO	To support MIPI reference clocks
U68	0x6A	7	125 MHz	LVDS	HSIO	To support MIPI reference clocks
U68	0x6A	8	125 MHz	LVDS	HSIO	To support SGMII reference clock
U68	0x6A	9	N/A	Disabled	HSIO	To support SGMII reference clock
U68	0x6A	10	100 MHz	HCSL	m.2 M-Key Connector	Reference Clock for m.2 M-key interface
U68	0x6A	11	100 MHz	HCSL	m.2 E-Key Connector	Reference Clock for m.2 E-key interface

Altering the PLL configuration¶

Users may create their own uBoot scripts to change the configuration of the PLL chip. The chip configuration files can be build using the Skyworks ClockBuilder Pro application. The application can be used to generate output programming files as well as a CSV file containing the necessary register settings.

The linux script on this page, pgm-pll-uboot.sh , can be used to convert the generated CSV file into a set of uBoot commands for programming the PLL.

MitySOM-A5E Mini Development Kit¶

The MitySOM-A5E Mini development kit carrier card includes a si5338 4 channel (differential) Phase Lock Loop Chip.

The PLL chip is provided a (coherent) copy of the 25 MHz reference clock sourced by the MitySOM-A5E Mini. This same clock is also fed back to the SOM on an HPS IO pin to support clocking the HPS and it's PLLs. The PLL chip is powered with 1.8V and uses 1.8V on the I2C control port.

The default PLL configuration for the revision 1 carrier board is as follows:

PLL Ref Des	I2C1 Address	Clock Index	Frequency (MHz)	Standard	Connection	Notes
U10	0x70	0	156.25	LVDS (AC)	FPGA REFCLK_GTSL1B_RX (BA66/BA69)	Intended for SFP+ Port
U10	0x70	1	150	LVDS (AC)	FPGA REFCLK_GTSL1C_RX (AU66/AU69)	Intended for Display Port
U10	0x70	2	100	LVDS (AC)	FPGA REFCLK_GTSL1C_CH1 (AR66/AR69)	Spare
U10	0x70	3	20	LVDS (DC)	FPGA DIFF_IO_3A_T19 (P22/V22)	Intended for MIPI or LVDS

The default PLL configuration for the revision 2 carrier board is as follows:

PLL Ref Des	I2C1 Address	Clock Index	Frequency (MHz)	Standard	Connection	Notes
U10	0x70	0	150	HCSL (AC)	FPGA REFCLK_GTSL1B_RX (BA66/BA69)	Intended for Display Port
U10	0x70	1	156.25	HCSL (AC)	FPGA REFCLK_GTSL1C_RX (AU66/AU69)	Intended for SFP+ Port
U10	0x70	2	100	HCSL (AC)	FPGA REFCLK_GTSL1C_CH1 (AR66/AR69)	Intended for USB 3.0
U10	0x70	3	20	LVDS (DC)	FPGA DIFF_IO_3A_T18 (K21/K24)	Intended for MIPI or LVDS

The root filesystem includes a perl script developed by Intel in /usr/bin/si5338_cfg that may be used to program the SI5338 device from the HPS should an alternate clocking scheme be needed.

In addition, there is a fixed 100 MHz HCSL clock driver feeding FPGA REFCLK_GTSR4C_RX (AY17/AY19) in order to support the PCIe interface.