Boot Media¶

The Agilex 5 boot-up / start-up sequence starts by loading the Secure Device Manager (SDM). The SDM is responsible for managing (re)configuration of the FPGA and initializing the Hard Processor Subsystem (HPS) First Stage Boot Loader (FSBL). The SDM program / bitstream is loaded from an on-board Quad SPI (QSPI) NOR Flash device via the Agilex 5 MSEL selection of "011".

The SDM must always be loaded from the on-board QSPI NOR-Flash.

Once the SDM is loaded, two initialization sequences can be used: configuring the complete FPGA fabric first ("FPGA First"), or configuring the HPS FSBL first ("HPS First"). Customers are encouraged to review the Agilex 5 Device Configuration User Guide for more detailed information.

FPGA First¶

In FPGA First mode, the SDM bitstream includes a complete bitstream for the entire FPGA fabric -- including the HPS EMIF interface. This means that the FPGA configuration bitstream must reside in the QSPI NOR Flash. The initialization sequence can be summarized by the following steps:

1. System Power ON
2. SDM firmware image loaded from QSPI NOR Flash
3. Complete FPGA fabric configured from SDM bitstream loaded from QSPI NOR Flash, including the SDRAM interface to the HPS.
4. FSBL for HPS loaded from SDM bitstream loaded from QSPI NOR Flash
5. Secondary bootloader (e.g., uBoot) or Kernel Image loaded from any HPS accessible media (micro-SD card, NAND, eMMC, Ethernet, etc.).
6. OS loaded from any HPS accessible media (micro-SD card, NAND, eMMC, Ethernet, etc.).

HPS First¶

In HPS First mode, the SDM bitstream includes a partial bitstream for the FPGA fabric, enough to configure the HPS EMIF Interface. The HPS FSBL is then loaded, and the remaining FPGA fabric is configured by the HPS at a later time. This means that the bulk of the FPGA configuration bitstream can be loaded from any HPS accessible media. The initialization sequence can be summarized by the following steps:

1. System Power On
2. SDM firmware image loaded from QSPI NOR Flash
3. FPGA Fabric configuration for HPS EMIF/SDRAM interface loaded from SDM bistream from QSPI NOR Flash.
4. FSBL for HPS is laoded from the SDM bitstream loaded from QSPI NOR Flash
5. Secondary bootloader (e.g., uBoot) or Kernel Image loaded from any HPS accessible media
6. OS loaded from any HPS accessible media (micro-SD card, NAND, eMMC, Ethernet, etc.).
7. Complete FPGA bitstream loaded from any HPS accessible media (micro-SD card, NAND, eMMC, Ethernet, etc.).

Note that steps 6 and 7 listed about may be reversed. A secondary bootloader could also initiate full FPGA configuration prior to loading / launching the final OS or end application.