Building the FPGA project and Bootloader with Quartus Pro 24.1¶

1. Prerequisites 2. Building the FPGA and Bootloader 3. Building the Filesystem 4. Building the SD Card

Introduction¶

The reference project for the MitySOM-A5E and DevKit requires the Quartus Pro 24.1 tools installed and in your path.
For compiling the bootloader, it is required to have the GCC-ARM-11.2 Toolchain installed as well. Instructions for installing and sourcing are below:

wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
rm -f gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
export PATH=`pwd`/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu/bin:$PATH
export ARCH=arm64
export CROSS_COMPILE=aarch64-none-linux-gnu-

Description	Repository	Branch
Quartus Example Projects	git://support.criticallink.com/home/git/mitysom-a5e-ref.git	pro_24.1_stable

Quick steps to build¶

Clone the repository¶

git clone -b pro_24.1_stable git://support.criticallink.com/home/git/mitysom-a5e-ref.git

Navigate into the root of the Quartus project¶

cd mitysom-a5e-ref/base_project

Generate the project¶

The project is set up to be customizable from TCL. To generate the default configuration run the following:

make generate_from_tcl

Build the FPGA project and Bootloader¶

make jic

This will result in output_files/base_project.hps.jic. The default configuration for the project is for an HPS FIRST style configuration. The base_project.hps.jic file contains the SDM and SPL initial boot software and a partial bitstream to support configuring the HPS EMIF and HPS IO pins. The full FPGA bitstream is found in the output_files/base_project.core.rbf file, which can be loaded off of other boot media (such as the SD-Card on the Dev Kit board) by the HPS during uBoot or by the Linux Kernel.

The JIC file contains the FPGA design and the preloader which is programming into the QSPI NOR. You must update the QSPI NOR / JIC file anytime changes are made to the HPS block in your platform designer is altered.

Program the QSPI NOR with the FPGA design / Preloader¶

The JIC can be programmed using the Altera USB-II Blaster with the following command:

quartus_pgm -m jtag -o "ip;output_files/base_project.hps.jic@2" 

Note, the above command is valid if the system is powered and the SDM has loaded a valid configuration bitstream already. The SDM inserts a second JTAG device (the ARM complex) before the FPGA bitstream. If the SOM has not been programmed or has not loaded a valid bitstream, change the above command to:

quartus_pgm -m jtag -o "ip;output_files/base_project.hps.jic@1" 

Bootloader¶

The preloader is part of the JIC file previously programmed. U-boot (second stage bootloader) is output in software/bootloader/u-boot-socfpga/u-boot.itb after running the make jic command above.

Bootloader Environment¶

The bootloader environment script can be found in software/boot.cmd. This is bootloader script that is ran as part of the boot process. The script can be compiled by running the following:

make uboot_script

The compiled output script will be in software/boot.scr

1. Prerequisites 2. Building the FPGA and Bootloader 3. Building the Filesystem 4. Building the SD Card