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MitySOM-C10G DevKit Base Project

This project configures the MitySOM-C10G to include a NIOS-V/g project with the following peripherals:

  • On board DDR3
  • Internal Memory (256 KB)
  • UART Console to DevKit UART to USB interface
  • I2C bus for communicating to SOM EEPROM and SI5338 PLL Chip
  • I2C bus for communicating to DevKit LTC2945 Power Monitor
  • Altera TripleSpeed Ethernet and SGDMA modules
  • FPGA Temperature Monitor
  • FPGA ADC
  • Access to the onboard QSPI FLASH interface
  • 10 Transceivers in Loop Back configuration at 8 GHz * Assumes a loop back FMC card is installed on the DevKit FMC connector * Includes Attached JTAG memory master to support Transciever Toolkit

The Makefile also supports a basic baremetal / HAL project for the NIOS to run to support
the following activities:

  • Display Temperature
  • Display ADC measurements
  • Program the SI5338 PLL Chip
  • Read and set the factory configuration EEPROM
  • Read the LTC2945 power monitor chip
  • Use the Altera Transciever Toolkit to validate Transceiver SI
  • Execute from DDR3

Build Instructions

These instructions assume you are running a command line version of Quartus in a linux environment.

Setting Up Your Environment

In order to build the Linux PATH variable will need to contain paths to the appropriate toolchains.

One methodology to achieve this is to make a function in your bashrc file that you can call in a new shell to set up your environment for buidling this project:

quartuspro_24_1() {                                                             
        export QSYS_ROOTDIR="/tools/intelFPGA_pro/24.1/qsys/bin"        
        export QUARTUS_ROOTDIR="/tools/intelFPGA_pro/24.1/quartus"      
        export PATH=${QUARTUS_ROOTDIR}/bin:${PATH}                              
        export PATH=${QUARTUS_ROOTDIR}/../niosv/bin:${PATH}                     
        export PATH=${QUARTUS_ROOTDIR}/../riscfree/build_tools/bin:${PATH}      
        export PATH=${QUARTUS_ROOTDIR}/../riscfree/build_tools/cmake/bin:${PATH}
        export PATH=${QUARTUS_ROOTDIR}/../riscfree/toolchain/riscv32-unknown-elf/bin:${PATH}
        export PATH=${QSYS_ROOTDIR}:${PATH}                                     
}

Setting Up the Project

Use git to clone the repository.

Checkout the desired branch.

Run the following command:

$ make generate_from_tcl && make generate_from_tcl

Note that "make generate_from_tcl" is intentionally run twice in order to properly generate all the necessary project files.

Generating the Bitstream / SOF

make sof

Generating the NIOS-V Baremetal Application

make hal

Programming the Bistream via JTAG

quartus_pgm -c 1 -m jtag -o "p;output_files/base_project.sof"

Downloading and Starting the Baremetal Application on the NIOS-V via JTAG

niosv-download -r -g software/app_hal/build/base_project.elf

The application communicates via J4, the USB_UART port, on the Devkit. The UART should be configured to
115200 BAUD with 1 stop bit and no parity correction.

Programming QSPI

Follow the steps in the sections below. For further details see Section "4.5.1.2. Nios V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (GSFI Bootloader)" in "Nios® V Embedded Processor Design Handbook" dated 2023.12.04.

Create NIOS-V .hex File (required for .jic creation)

First, run the following command to geneate flash.srec:

elf2flash --boot {QUARTUS_INSTALL_DIR}/niosv/components/bootloader/niosv_g_bootloader.srec --input software/app_hal/build/base_project.elf --output flash.srec --reset 0x03000000 --base 0x02000000 --end 0x03FFFFFF

Notes:
  • --reset 0x03000000 specifies "the reset offset + base address of GSFI AVL MEM" where "the reset offset" must match the value set in the NIOS V qsys component parameters
  • --base 0x02000000 is the "base address of GSFI AVL MEM"
  • --end 0x03FFFFFF is the "end address of GSFI AVL MEM"

Lastly, run the following command to generate base_project.hex:

riscv32-unknown-elf-objcopy --input-target srec --output-target ihex flash.srec base_project.hex

Create .jic File

Now you should have all the necessary files (base_project.sof and base_project.hex) to create the .jic file which allows Quartus to program the QSPI with the FPGA and BIOS binaries.

In order to generate the .jic file with the binaries in the proper places in QSPI, c10gx_create_jic.cof has been provided. Note that other steps in the build process may delete this file. If it is missing it can be checked back out using the command:

git checkout c10gx_create_jic.cof

Once you have verified c10gx_create_jic.cof is present follow these steps:
  • Open the Quartus GUI
  • Select File -> Convert Programming Files
  • Click "Open Conversion Setup Data..." and select c10gx_create_jic.cof.
  • Click "Generate" to create base_project.jic.

Program QSPI

Now that you have a .jic file you can use Quartus Programmer to program QSPI:
  • Open the Quartus GUI
  • Select "Tools -> Programmer"
  • Click "Hardware Setup..." to select the USB-BlasterII if necessary.
  • If necessary click "Auto Detect" to show the 10CX220YF780 device in the JTAG chain
  • Right click on the device and select "Change File," then choose base_project.jic
  • Make sure the Program/Configure boxes are checked
  • Click "Start" and make sure the Progress reports a success upon completion * It may take a minute or so to finish programming
  • Power the unit on and off and you should see the NIOS application print to the Console * Note that it will take a bit for the bootloader to copy the NIOS code from QSPI to DDR and execute, so you may have to wait a bit after power up to see console output

Transceiver Testing

The transceivers have been configured to work with the Kaya Instruments KY-FMCLPBK FMC loopback card. In order to repeat this testing connect KY-FMCLPBK (or a compatible card) to J6 while the board is powered off.

Note that the transceivers receive their reference clocks from U18 (Si5338C). In order for the transceivers to lock, you need to run the following command from the
UART on the devkit:

progpll

Then the FPGA needs to be reprogrammed. Pressing S1 will reset the FPGA and cause it to reprogram from the image in QSPI. Using the quartus_pgm command, as outlined previously, offers an option to reprogram the FPGA via JTAG if desired as well.

When the transceiver PLLs are locked, D5 will light on the devkit.

At this point you can launch the System Console to perform loopback testing. Detailed instructions are below:
  • Launch the Quartus GUI
  • Select Tools -> System Debugging Tools -> System Console
  • If no design populates, click "Load Design" and select the .sof file matching the currently programming FPGA bitstream
  • Now the Details Pane should populate and you can right click “Arria 10/Cyclone 10 Transceiver Native PHY Toolkit” and select “Add to Collection” -> “New Collection”
  • Now Collection_1 will show up in the Collections Pane. Double click on Collection_1 to have it show up in the upper right of the GUI
  • Select all the items in Collection_1 and Right Click -> Actions -> PRBS Pattern -> PRBS31 to set all the transceivers in this collection ot PRBS31.
  • Select all the RX Channels in Collection_1 and Right Click -> Actions -> Hard PRBS -> Reset to reset bit error calculations in preparation for the test
  • Select all the TX Channels in Collection_1 and Right Click -> Actions -> Hard PRBS -> Start
  • Select all the RX Channels in Collection_1 and Right Click -> Actions -> Hard PRBS -> Start * Verify the “Number of bits tested” is increasing
  • Let run for a couple minutes and verify the Bit error reported in near 0
  • Repeat for the other transceiver subsystem as desired

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