e:/hudson/workspace/MityDSP MDK Release/trunk/sw/inc/core/DspFirmware.h File Reference

#include <std.h>
#include <sem.h>
#include <tsk.h>
#include <stdio.h>

Classes
union	MityDSP::tuFirmwareVersion
union	MityDSP::tuInterruptInfo
union	MityDSP::tuBootstrapVerInfo
union	MityDSP::tuBootstrapDateInfo
class	MityDSP::tcDspFirmware
	Static class to provide access to core-independent features of the MityDSP firmware. More...
Namespaces
namespace	MityDSP
Defines
#define	GLOBAL_CORE_NAME   "Firmware"
#define	MITY_UART_CORE_NAME   "MityUART Core"
#define	ETHERNET_CORE_NAME   "Ethernet Core"
#define	HW_UART_CORE_NAME   "HW UART Core"
#define	GPIO_CORE_NAME   "GPIO Core"
#define	ADC9235_CORE_NAME   "ADC9235 ADC Core"
#define	SHIFT_REG_CORE_NAME   "Shift Register I/O Core"
#define	I2C_CORE_NAME   "I2C Core"
#define	PWM_CORE_NAME   "PWM Core"
#define	STEPPER_CORE_NAME   "Stepper Motor Ctlr Core"
#define	PULSE_INTEG_CORE_NAME   "Pulse Integrator Core"
#define	ADC8343_CORE_NAME   "ADC8343 ADC Core"
#define	EVENT_CNTR_CORE_NAME   "Event Counter Core"
#define	TIMER_CORE_NAME   "Timer Core"
#define	SPI_CORE_NAME   "SPI Transceiver Core"
#define	TMP05_CORE_NAME   "TMP05/06 Temp. Sensor Core"
#define	ADC8344_CORE_NAME   "ADC8344 ADC Core"
#define	RAM_BLOCK_CORE_NAME   "Generic RAM Block Interface"
#define	ADS8402_CORE_NAME   "ADS8402 ADC Core"
#define	AWG_CORE_NAME   "Waveform Generator Core"
#define	IIR_CORE_NAME   "IIR Filter Core"
#define	TIME_GEN_CORE_NAME   "Timing Generator Core"
#define	FPGA_DMA_CORE_NAME   "FPGA DMA Core"
#define	TOUCH_SCRN_CORE_NAME   "Touch Screen Core"
#define	ADS8329_CORE_NAME   "ADS8329 ADC Core"
#define	QVGA_16_CORE_NAME   "QVGA 16-bpp Display Core"
#define	LVDS_CORE_NAME   "LVDS Core"
#define	CAMERALINK_CORE_NAME   "Camera Link Core"
#define	AD7760_CORE_NAME   "AD7760 ADC Core"
#define	EZ_USB_CORE_NAME   "EZ-USB Core"
#define	RFC1305_CLK_CORE_NAME   "RFC-1305 Clock Core"
#define	LCD_EMIF_CORE_NAME   "FPGA DMA Controlled LCD Core"
#define	DAC9881_CORE_NAME   "DAC9881 Core"
#define	CORE_NAME_INITIALIZER
Functions
void	cpu_load_hook_function (TSK_Handle ahOld, TSK_Handle ahNew)
	This is a callback function for a task switch.
Variables
const unsigned int	MityDSP::IE_MASK_4 = 0x00000001
	< Masks for global interrupt enables.
const unsigned int	MityDSP::IE_MASK_5 = 0x00000002
const unsigned int	MityDSP::IE_MASK_6 = 0x00000004
const unsigned int	MityDSP::IE_MASK_7 = 0x00000008
const int	MityDSP::GLOBAL_CORE_ID = 0
const int	MityDSP::MITY_UART_CORE_ID = 1
const int	MityDSP::ETHERNET_CORE_ID = 2
const int	MityDSP::HW_UART_CORE_ID = 3
const int	MityDSP::GPIO_CORE_ID = 4
const int	MityDSP::ADC9235_CORE_ID = 5
const int	MityDSP::SHIFT_REG_CORE_ID = 6
const int	MityDSP::I2C_CORE_ID = 7
const int	MityDSP::PWM_CORE_ID = 8
const int	MityDSP::STEPPER_CORE_ID = 9
const int	MityDSP::PULSE_INTEG_CORE_ID = 10
const int	MityDSP::ADC8343_CORE_ID = 11
const int	MityDSP::EVENT_CNTR_CORE_ID = 12
const int	MityDSP::TIMER_CORE_ID = 13
const int	MityDSP::SPI_CORE_ID = 14
const int	MityDSP::TMP05_CORE_ID = 15
const int	MityDSP::ADC8344_CORE_ID = 16
const int	MityDSP::RAM_BLOCK_CORE_ID = 17
const int	MityDSP::ADS8402_CORE_ID = 18
const int	MityDSP::AWG_CORE_ID = 19
const int	MityDSP::IIR_CORE_ID = 20
const int	MityDSP::TIME_GEN_CORE_ID = 21
const int	MityDSP::FPGA_DMA_CORE_ID = 22
const int	MityDSP::TOUCH_SCRN_CORE_ID = 23
const int	MityDSP::ADS8329_CORE_ID = 24
const int	MityDSP::QVGA_16_CORE_ID = 25
const int	MityDSP::LVDS_CORE_ID = 26
const int	MityDSP::CAMERALINK_CORE_ID = 27
const int	MityDSP::AD7760_CORE_ID = 28
const int	MityDSP::EZ_USB_CORE_ID = 29
const int	MityDSP::RFC1305_CLK_CORE_ID = 30
const int	MityDSP::LCD_EMIF_CORE_ID = 31
const int	MityDSP::DAC9881_CORE_ID = 32
const int	MityDSP::NUM_CORE_IDS = 33
const int	MityDSP::gnAutoLevel = -1
	Indicates that automatic ISR level and vector installation should be attempted.
PLL Registers
const unsigned int	MityDSP::PLL_PID = 0x01B7C000
	Peripheral Identification Register.
const unsigned int	MityDSP::PLL_CSR = 0x01B7C100
	Control/Status Register.
const unsigned int	MityDSP::PLL_MULT = 0x01B7C110
	PLL Multiplier Control Register.
const unsigned int	MityDSP::PLL_DIV0 = 0x01B7C114
	PLL Divider D0 Control Register.
const unsigned int	MityDSP::PLL_DIV1 = 0x01B7C118
	PLL Divider D1 Control Register.
const unsigned int	MityDSP::PLL_DIV2 = 0x01B7C11C
	PLL Divider D2 Control Register.
const unsigned int	MityDSP::PLL_DIV3 = 0x01B7C120
	PLL Divider D3 Control Register.
const unsigned int	MityDSP::OSC_DIV1 = 0x01B7C124
	Oscillator Divider Control Register.
EMIF Registers
const unsigned int	MityDSP::EMIF_GCR = 0x1800000
	Address of EMIF global control.
const unsigned int	MityDSP::EMIF_CE0 = 0x1800008
	Address of EMIF CE0 control.
const unsigned int	MityDSP::EMIF_CE1 = 0x1800004
	Address of EMIF CE1 control.
const unsigned int	MityDSP::EMIF_CE2 = 0x1800010
	Address of EMIF CE2 control.
const unsigned int	MityDSP::EMIF_CE3 = 0x1800014
	Address of EMIF CE3 control.
const unsigned int	MityDSP::EMIF_SDCTRL = 0x1800018
	Address of EMIF SDRAM control.
const unsigned int	MityDSP::EMIF_SDRP = 0x180001c
	Address of EMIF SDRM refresh period.
const unsigned int	MityDSP::EMIF_SDEXT = 0x1800020
	Address of EMIF SDRAM extension.

---

Define Documentation

#define GLOBAL_CORE_NAME   "Firmware"

#define MITY_UART_CORE_NAME   "MityUART Core"

#define ETHERNET_CORE_NAME   "Ethernet Core"

#define HW_UART_CORE_NAME   "HW UART Core"

#define GPIO_CORE_NAME   "GPIO Core"

#define ADC9235_CORE_NAME   "ADC9235 ADC Core"

#define SHIFT_REG_CORE_NAME   "Shift Register I/O Core"

#define I2C_CORE_NAME   "I2C Core"

#define PWM_CORE_NAME   "PWM Core"

#define STEPPER_CORE_NAME   "Stepper Motor Ctlr Core"

#define PULSE_INTEG_CORE_NAME   "Pulse Integrator Core"

#define ADC8343_CORE_NAME   "ADC8343 ADC Core"

#define EVENT_CNTR_CORE_NAME   "Event Counter Core"

#define TIMER_CORE_NAME   "Timer Core"

#define SPI_CORE_NAME   "SPI Transceiver Core"

#define TMP05_CORE_NAME   "TMP05/06 Temp. Sensor Core"

#define ADC8344_CORE_NAME   "ADC8344 ADC Core"

#define RAM_BLOCK_CORE_NAME   "Generic RAM Block Interface"

#define ADS8402_CORE_NAME   "ADS8402 ADC Core"

#define AWG_CORE_NAME   "Waveform Generator Core"

#define IIR_CORE_NAME   "IIR Filter Core"

#define TIME_GEN_CORE_NAME   "Timing Generator Core"

#define FPGA_DMA_CORE_NAME   "FPGA DMA Core"

#define TOUCH_SCRN_CORE_NAME   "Touch Screen Core"

#define ADS8329_CORE_NAME   "ADS8329 ADC Core"

#define QVGA_16_CORE_NAME   "QVGA 16-bpp Display Core"

#define LVDS_CORE_NAME   "LVDS Core"

#define CAMERALINK_CORE_NAME   "Camera Link Core"

#define AD7760_CORE_NAME   "AD7760 ADC Core"

#define EZ_USB_CORE_NAME   "EZ-USB Core"

#define RFC1305_CLK_CORE_NAME   "RFC-1305 Clock Core"

#define LCD_EMIF_CORE_NAME   "FPGA DMA Controlled LCD Core"

#define DAC9881_CORE_NAME   "DAC9881 Core"

#define CORE_NAME_INITIALIZER

---

Function Documentation

void cpu_load_hook_function	(	TSK_Handle	ahOld,
		TSK_Handle	ahNew
	)

This is a callback function for a task switch.

It is used to light the MityDSP LED's to indicate CPU load. With a MityDSP-Pro, one LED will be fully on when the CPU is idle, the other will be fully on when the CPU is busy, and they will be somewhere inbetween based on load. For a standard MityDSP, only the busy LED exists.

Note:

In order to work, this function must be installed as a "switch function" with the Module Hook Manager in the DSP/BIOS configuration file.

Parameters:

[in]	ahOld	The thread being swithched out.
[in]	ahNew	The thread being swithched in.

Returns:

None.