Namespaces | |
| namespace | MityDSP |
Defines | |
| #define | UART_UPDATE_VERSION 2 |
| #define | UARTR_OFF_RHR_old 0 |
| #define | UARTW_OFF_THR 0 |
| #define | UART_OFF_IER 1 |
| #define | UARTR_OFF_IIR 2 |
| #define | UARTW_OFF_FCR 2 |
| #define | UART_OFF_LCR 3 |
| #define | UART_OFF_MCR 4 |
| #define | UARTR_OFF_LSR 5 |
| #define | UARTR_OFF_MSR_old 6 |
| #define | UART_OFF_SPR 7 |
| #define | UARTL_OFF_DLL 0 |
| #define | UARTL_OFF_DLH 1 |
| #define | UARTL_OFF_EFR 2 |
| #define | UARTL_OFF_XON1 4 |
| #define | UARTL_OFF_XON2 5 |
| #define | UARTL_OFF_XOFF1 6 |
| #define | UARTL_OFF_XOFF2 7 |
| #define | UARTL_OFF_TCR 6 |
| #define | UARTL_OFF_TLR 7 |
| #define | UARTR_OFF_RHR 8 |
| #define | UARTR_OFF_MSR 12 |
| #define | UART_IER_RX_AVAIL 0x01 |
| Receive data available. | |
| #define | UART_IER_THR_EMPT 0x02 |
| Transmit empty. | |
| #define | UART_IER_RX_LSTAT 0x04 |
| #define | UART_IER_MDM_STAT 0x08 |
| Modem line change. | |
| #define | UART_IER_SLEEP 0x10 |
| #define | UART_IER_nXOFF 0x20 |
| XOFF asserted. | |
| #define | UART_IER_nRTS 0x40 |
| Ready-to-Send. | |
| #define | UART_IER_nCTS 0x80 |
| Clear-to-Send. | |
| #define | UART_LCR_CHR6 0x01 |
| 6 data bits | |
| #define | UART_LCR_CHR7 0x02 |
| 7 data bits | |
| #define | UART_LCR_CHR8 0x03 |
| 8 data bits | |
| #define | UART_LCR_1_STOP 0x00 |
| 1 stop bit | |
| #define | UART_LCR_2_STOP 0x04 |
| 2 stop bits | |
| #define | UART_LCR_NOPARITY 0x00 |
| no parity | |
| #define | UART_LCR_EVENPARITY 0x18 |
| even parity | |
| #define | UART_LCR_ODDPARITY 0x08 |
| odd parity | |
| #define | UART_LCR_PARITY_0 0x38 |
| force parity bit to 0 (must set bit 3 to enable parity bit) | |
| #define | UART_LCR_PARITY_1 0x28 |
| force parity bit to 1 (must set bit 3 to enable parity bit) | |
| #define | UART_LCR_BREAK 0x40 |
| forces transmiter low | |
| #define | UART_LCR_DIV_LATCH 0x80 |
| #define | UART_LCR_ENHANCE_ACC 0xBF |
| #define | UART_FCR_ENABLE 0x01 |
| #define | UART_FCR_CLEAR_RX 0x02 |
| #define | UART_FCR_CLEAR_TX 0x04 |
| #define | UART_FCR_DMA_MODE1 0x08 |
| #define | UART_FCR_TXFIFO_32 0x20 |
| #define | UART_FCR_RXFIFO_16 0x40 |
| #define | UART_LSR_RXDATA 0x01 |
| data in fifo | |
| #define | UART_LSR_OVERRUN 0x02 |
| overrun err | |
| #define | UART_LSR_PARERR 0x04 |
| parity error | |
| #define | UART_LSR_FRAMERR 0x08 |
| framing error | |
| #define | UART_LSR_BREAKDET 0x10 |
| break condition occurred | |
| #define | UART_LSR_THRE 0x20 |
| transmit hold register empty | |
| #define | UART_LSR_TEMT 0x40 |
| transmitter hold AND shift reg. empty | |
| #define | UART_LSR_ERR 0x80 |
| at least one error stored in receiver | |
| #define | UART_EFR_ENHANCE 0x10 |
| #define | UART_EFR_SPECIAL 0x20 |
| #define | UART_EFR_nRTS_FLOW 0x40 |
| #define | UART_EFR_nCTS_FLOW 0x80 |
| #define | UART_MCR_nDTR_ACT 0x01 |
| force nDTR output to active (low) | |
| #define | UART_MCR_nRTS_ACT 0x02 |
| force nRTS output to active (low) | |
| #define | UART_MCR_FIFORdy 0x04 |
| enables the FIFORdy register | |
| #define | UART_MCR_IRQ_ACT 0x08 |
| forces IRQ(A-D)outputs to the active state | |
| #define | UART_MCR_INT_LOOP 0x10 |
| enable local loopback mode(internal) | |
| #define | UART_MCR_XON_ANY 0x20 |
| enable Xon Any function | |
| #define | UART_MCR_TCRTLR 0x40 |
| enable access to TCR and TLR registers | |
| #define | UART_MCR_DIV4 0x80 |
| divide by four clock input | |
| #define | UART_TX_FIFO_422 0x01 |
| #define | UART_TX_FIFO_UCOM 0x02 |
| #define | UART_TX_FIFO_LCOM 0x04 |
| #define | UART_TX_FIFO_DCOM 0x08 |
| #define | UART_RX_FIFO_422 0x10 |
| #define | UART_RX_FIFO_UCOM 0x20 |
| #define | UART_RX_FIFO_LCOM 0x40 |
| #define | UART_RX_FIFO_DCOM 0x80 |
| #define | UART_MSR_CTSCHG 0x01 |
| #define | UART_MSR_DSRCHG 0x02 |
| #define | UART_MSR_RITRAIL 0x04 |
| #define | UART_MSR_CDCHG 0x08 |
| #define | UART_MSR_CTS 0x10 |
| #define | UART_MSR_DSR 0x20 |
| #define | UART_MSR_RI 0x40 |
| #define | UART_MSR_CD 0x80 |
Variables | |
| const int | MityDSP::UART_TX_FIFO_DEPTH = 64 |
| Maximum depth of the UART internal TX FIFO. | |
| #define UART_UPDATE_VERSION 2 |
| #define UARTR_OFF_RHR_old 0 |
| #define UARTW_OFF_THR 0 |
| #define UART_OFF_IER 1 |
| #define UARTR_OFF_IIR 2 |
| #define UARTW_OFF_FCR 2 |
| #define UART_OFF_LCR 3 |
| #define UART_OFF_MCR 4 |
| #define UARTR_OFF_LSR 5 |
| #define UARTR_OFF_MSR_old 6 |
| #define UART_OFF_SPR 7 |
| #define UARTL_OFF_DLL 0 |
| #define UARTL_OFF_DLH 1 |
| #define UARTL_OFF_EFR 2 |
| #define UARTL_OFF_XON1 4 |
| #define UARTL_OFF_XON2 5 |
| #define UARTL_OFF_XOFF1 6 |
| #define UARTL_OFF_XOFF2 7 |
| #define UARTL_OFF_TCR 6 |
| #define UARTL_OFF_TLR 7 |
| #define UARTR_OFF_RHR 8 |
| #define UARTR_OFF_MSR 12 |
| #define UART_IER_RX_AVAIL 0x01 |
Receive data available.
| #define UART_IER_THR_EMPT 0x02 |
Transmit empty.
| #define UART_IER_RX_LSTAT 0x04 |
| #define UART_IER_MDM_STAT 0x08 |
Modem line change.
| #define UART_IER_SLEEP 0x10 |
| #define UART_IER_nXOFF 0x20 |
XOFF asserted.
| #define UART_IER_nRTS 0x40 |
Ready-to-Send.
| #define UART_IER_nCTS 0x80 |
Clear-to-Send.
| #define UART_LCR_CHR6 0x01 |
6 data bits
| #define UART_LCR_CHR7 0x02 |
7 data bits
| #define UART_LCR_CHR8 0x03 |
8 data bits
| #define UART_LCR_1_STOP 0x00 |
1 stop bit
| #define UART_LCR_2_STOP 0x04 |
2 stop bits
| #define UART_LCR_NOPARITY 0x00 |
no parity
| #define UART_LCR_EVENPARITY 0x18 |
even parity
| #define UART_LCR_ODDPARITY 0x08 |
odd parity
| #define UART_LCR_PARITY_0 0x38 |
force parity bit to 0 (must set bit 3 to enable parity bit)
| #define UART_LCR_PARITY_1 0x28 |
force parity bit to 1 (must set bit 3 to enable parity bit)
| #define UART_LCR_BREAK 0x40 |
forces transmiter low
| #define UART_LCR_DIV_LATCH 0x80 |
| #define UART_LCR_ENHANCE_ACC 0xBF |
| #define UART_FCR_ENABLE 0x01 |
| #define UART_FCR_CLEAR_RX 0x02 |
| #define UART_FCR_CLEAR_TX 0x04 |
| #define UART_FCR_DMA_MODE1 0x08 |
| #define UART_FCR_TXFIFO_32 0x20 |
| #define UART_FCR_RXFIFO_16 0x40 |
| #define UART_LSR_RXDATA 0x01 |
data in fifo
| #define UART_LSR_OVERRUN 0x02 |
overrun err
| #define UART_LSR_PARERR 0x04 |
parity error
| #define UART_LSR_FRAMERR 0x08 |
framing error
| #define UART_LSR_BREAKDET 0x10 |
break condition occurred
| #define UART_LSR_THRE 0x20 |
transmit hold register empty
| #define UART_LSR_TEMT 0x40 |
transmitter hold AND shift reg. empty
| #define UART_LSR_ERR 0x80 |
at least one error stored in receiver
| #define UART_EFR_ENHANCE 0x10 |
| #define UART_EFR_SPECIAL 0x20 |
| #define UART_EFR_nRTS_FLOW 0x40 |
| #define UART_EFR_nCTS_FLOW 0x80 |
| #define UART_MCR_nDTR_ACT 0x01 |
force nDTR output to active (low)
| #define UART_MCR_nRTS_ACT 0x02 |
force nRTS output to active (low)
| #define UART_MCR_FIFORdy 0x04 |
enables the FIFORdy register
| #define UART_MCR_IRQ_ACT 0x08 |
forces IRQ(A-D)outputs to the active state
| #define UART_MCR_INT_LOOP 0x10 |
enable local loopback mode(internal)
| #define UART_MCR_XON_ANY 0x20 |
enable Xon Any function
| #define UART_MCR_TCRTLR 0x40 |
enable access to TCR and TLR registers
| #define UART_MCR_DIV4 0x80 |
divide by four clock input
| #define UART_TX_FIFO_422 0x01 |
| #define UART_TX_FIFO_UCOM 0x02 |
| #define UART_TX_FIFO_LCOM 0x04 |
| #define UART_TX_FIFO_DCOM 0x08 |
| #define UART_RX_FIFO_422 0x10 |
| #define UART_RX_FIFO_UCOM 0x20 |
| #define UART_RX_FIFO_LCOM 0x40 |
| #define UART_RX_FIFO_DCOM 0x80 |
| #define UART_MSR_CTSCHG 0x01 |
| #define UART_MSR_DSRCHG 0x02 |
| #define UART_MSR_RITRAIL 0x04 |
| #define UART_MSR_CDCHG 0x08 |
| #define UART_MSR_CTS 0x10 |
| #define UART_MSR_DSR 0x20 |
| #define UART_MSR_RI 0x40 |
| #define UART_MSR_CD 0x80 |