MityDSP::tcDspFpgaDma Class Reference

The tcDspFpgaDma class provides the MityDSP FPGA with DMA access to blocks of DSP memory. More...

#include <core/DspFpgaDma.h>

Public Types
enum	teChannelIds { eeChannel1 = 0, eeChannel2 = 1, eeChannel3 = 2, eeChannel4 = 3 }
	Channel enumerator. More...
Public Member Functions
	tcDspFpgaDma (void *apAddress, int anLevel=gnAutoLevel)
	This constructor is used to create an instance of the tcDspFpgaDma class.
	~tcDspFpgaDma ()
	This destructor is used to close up and free tcDspFpgaDma resources.
bool	DmaToFpga (int anChannel, void *apDspAddr, int anLength, bool abContinuous=false, SEM_Handle ahDmaComplete=NULL, bool abReInitFpgaBuffer=false, unsigned int anFpgaBufferOffset=0)
	This routine schedules a DMA transfer from a buffer in DSP RAM to the specified FPGA DMA channel.
bool	DmaFromFpga (int anChannel, void *apDspAddr, int anLength, bool abContinuous=false, SEM_Handle ahDmaComplete=NULL, bool abReInitFpgaBuffer=false, unsigned int anFpgaBufferOffset=0)
	This routine schedules a DMA transfer from a specified FPGA DMA channel to a buffer in DSP RAM.
bool	IsDmaComplete (int anChannel)
	This routine indicates whether or not a specified DMA channel is currently in use.
void	DisableChannel (int anChannel)
	This routine disables all DMA transfers on a specified channel.
Public Attributes
unsigned int	mnInterruptCount
	ISR counter (debug).
Static Public Attributes
static const int	gnNUM_DMA_CHANNELS = 4
	Number of DMA channels available.
Protected Member Functions
void	DmaCompleteInterrupt (void)
	Interrupt service routine for DMA complete interrupts.
void	ImplementSize (int anIdx, int anLength, bool abReInit, unsigned int anOffset)
	Internal routine to set the DMA transfer size for a specified FPGA location.
void	ImplementFlags (int anIdx, bool abEnable, bool abToFpga, bool abContinuous, bool abIntEnable, void *apDspAddr)
	Internal routine to set-up the DMA transfer flags for a specified FPGA location.
Static Protected Member Functions
static int	interrupt_dispatch (Arg arMyObject)
	Static interrupt dispatch routine.
Protected Attributes
SEM_Handle	mhMutex
	Used to serialize access.
volatile unsigned int *	mpBaseAddr
	Core base address.
unsigned short	mnMyIntMask
	core interrupt mask
int	mnMyIntLevel
	core interrupt level
int	mnMyIntVector
	core interrupt vector
SEM_Handle	mhDoneSemaphore [gnNUM_DMA_CHANNELS]
	Storage for completion semaphores.
bool	mbDmaEnabled [gnNUM_DMA_CHANNELS]
	True if channel enabled.
bool	mbDmaContinuous [gnNUM_DMA_CHANNELS]
	True if continuous DMA.

Detailed Description

The tcDspFpgaDma class provides the MityDSP FPGA with DMA access to blocks of DSP memory.

The accesses may be continuous or one-shot, read or write.

See also:: tcDspFpgaDma Page

Member Enumeration Documentation

enum MityDSP::tcDspFpgaDma::teChannelIds

Channel enumerator.

Enumerator:

eeChannel1
eeChannel2
eeChannel3
eeChannel4

Constructor & Destructor Documentation

tcDspFpgaDma::tcDspFpgaDma	(	void *	apAddress,
		int	anLevel = `gnAutoLevel`
	)

This constructor is used to create an instance of the tcDspFpgaDma class.

An interrupt level may be specified to install a chained ISR at the proper level, otherwise automatic interrupt vectoring is employed.

Parameters:

`[in]`	apAddress	Base Address of the FPGA DMA core
`[in]`	anLevel	Optional interrupt level parameter

Returns:: None.

See also:: DspFpgaDma.h; DspIntDispatch.h

tcDspFpgaDma::~tcDspFpgaDma ( )

This destructor is used to close up and free tcDspFpgaDma resources.

Returns:: None.

See also:: DspFpgaDma.h

Member Function Documentation

bool tcDspFpgaDma::DmaToFpga	(	int	anChannel,
		void *	apDspAddr,
		int	anLength,
		bool	abContinuous = `false`,
		SEM_Handle	ahDmaComplete = `NULL`,
		bool	abReInitFpgaBuffer = `false`,
		unsigned int	anFpgaBufferOffset = `0`
	)

This routine schedules a DMA transfer from a buffer in DSP RAM to the specified FPGA DMA channel.

Parameters:

`[in]`	anChannel	The FPGA DMA channel to use.
`[in]`	apDspAddr	The address of the DSP buffer (must be 4-byte aligned).
`[in]`	anLength	The length of the buffer to copy from (multiple of 4 bytes).
`[in]`	abContinuous	True for repeated transfer, false for a single-shot (default: false).
`[in]`	ahDmaComplete	An optional semaphore to signal upon DMA completion (default: NULL).
`[in]`	abReInitFpgaBuffer	FPGA buffer should restart from the specified location each transfer (default: false).
`[in]`	anFpgaBufferOffset	FPGA buffer offset used when abReInitFpgaBuffer is true (default: 0).

Returns:: True if scheduled successfully.

See also:: DspFpgaDma.h

bool tcDspFpgaDma::DmaFromFpga	(	int	anChannel,
		void *	apDspAddr,
		int	anLength,
		bool	abContinuous = `false`,
		SEM_Handle	ahDmaComplete = `NULL`,
		bool	abReInitFpgaBuffer = `false`,
		unsigned int	anFpgaBufferOffset = `0`
	)

This routine schedules a DMA transfer from a specified FPGA DMA channel to a buffer in DSP RAM.

Parameters:

`[in]`	anChannel	The FPGA DMA channel to use.
`[in]`	apDspAddr	The address of the DSP buffer (must be 4-byte aligned).
`[in]`	anLength	The length of the buffer to copy to (multiple of 4 bytes).
`[in]`	abContinuous	True for repeated transfer, false for a single-shot (default: false).
`[in]`	ahDmaComplete	An optional semaphore to signal upon DMA completion (default: NULL).
`[in]`	abReInitFpgaBuffer	FPGA buffer should restart from the specified location each transfer (default: false).
`[in]`	anFpgaBufferOffset	FPGA buffer offset used when abReInitFpgaBuffer is true (default: 0).

Returns:: True if scheduled successfully.

See also:: DspFpgaDma.h

bool tcDspFpgaDma::IsDmaComplete ( int anChannel )

This routine indicates whether or not a specified DMA channel is currently in use.

Parameters:

[in] anChannel The FPGA DMA channel to query.

Returns:: True if there is currently not a DMA in progress.

See also:: DspFpgaDma.h

void tcDspFpgaDma::DisableChannel ( int anChannel )

This routine disables all DMA transfers on a specified channel.

Parameters:

[in] anChannel The FPGA DMA channel to disable.

Returns:: None.

See also:: DspFpgaDma.h

int tcDspFpgaDma::interrupt_dispatch ( Arg ahMyObject ) [static, protected]

Static interrupt dispatch routine.

Required because of the hidden this pointer associated with a member function, which cannot be passed directly to the interrupt dispatcher.

Parameters:

[in] ahMyObject The "this->" pointer for the instance of tcDspFpgaDma associated with this ISR.

Returns:: 0

void tcDspFpgaDma::DmaCompleteInterrupt ( void ) [protected]

Interrupt service routine for DMA complete interrupts.

Each channel is checked to see if the enable bit is low, and the interrupt enable bit is high. If so, the interrupt is acknowledged appropriately, and any semaphore registered for the channel is posted.

See also:: DspFpgaDma.h

void tcDspFpgaDma::ImplementSize	(	int	anIdx,
		int	anLength,
		bool	abReInit,
		unsigned int	anOffset
	)			`[protected]`

Internal routine to set the DMA transfer size for a specified FPGA location.

Parameters:

`[in]`	anIdx	The location of the FPGA register who's size is to be set.
`[in]`	anLength	The size to write to the register.
`[in]`	abReInit	Set to true to re-initialize any in-process transfers (default:false).
`[in]`	anOffset	Byte offset into buffer to begin at following a re-initialization (default: 0).

Returns:: None.

See also:: DspFpgaDma.h

void tcDspFpgaDma::ImplementFlags	(	int	anIdx,
		bool	abEnable,
		bool	abToFpga,
		bool	abContinuous,
		bool	abIntEnable,
		void *	apDspAddr
	)			`[protected]`

Internal routine to set-up the DMA transfer flags for a specified FPGA location.

Parameters:

`[in]`	anIdx	The location of the FPGA register who's flags are to be set.
`[in]`	abEnable	True to enable the channel.
`[in]`	abToFpga	True for a transfer to the FPGA.
`[in]`	abContinuous	True for a continuous transfer.
`[in]`	abIntEnable	True to enable the DMA complete interrupt.
`[in]`	apDspAddr	Address of the DSP buffer to be read or written.