tcDspFpgaDma

Introduction

The tcDspFpgaDma class is used to provide the MityDSP FPGA with direct access to the DSP's RAM. The FPGA accesses the RAM by "stealing" cycles on the EMIF bus. The class supports up to 4 DMA channels in the FPGA, each of which may be used to transfer data between the DSP and another core intenal to the FPGA.

The tcDspFpgaDma class supports both continuous (e.g., frame buffer), and one-shot (e.g. ADC buffer) transfers. An interrupt is available whcih can be used to signal an application-provided semaphore upon DMA completion. Otherwise, a method is provided to allow an application to poll for completion.

See also:

MityDSP::tcDspFpgaDma Class Reference

MityDSP::tcDspInterruptDispatch Class Reference

Example

This is a simple example of tcDspFpgaDma creation and usage:

 {
     unsigned int *myData;
     int           myDataSize = 4096;
     unsigned int  myBaseAddr = 0xB0000200;
     tcDspFpgaDma *myDma;
     SEM_handle    mySem = SEM_create(0, NULL);
 
     // create a DMA interface
     myDma = new tcDspFpgaDma((void *)myBaseAddr);

     // prepare the myData buffer (application specific)
     ...

     // DMA data to the FPGA
     myDma->DmaToFpga(tcDspFpgaDma::eeChannel1, 
                      (void *)myData, myDataSize, false, mySem);

     // wait for completion
     SEM_pend(mySem, SYS_FOREVER);

     ...
 }